From: Jan Michel <j.michel@gsi.de>
Date: Wed, 7 Mar 2018 12:38:23 +0000 (+0100)
Subject: re-add PLL to calibration pulse generation
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=be0f50ab6e0cea48001c205fbe919fe6d2ca751a;p=trb3sc.git

re-add PLL to calibration pulse generation
---

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 4b5e360..43d972d 100644
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -278,7 +278,11 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
     make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long;
   end process;      
 
-
+  pll_calibration : entity work.pll_in125_out33
+    port map (
+      CLK   => CLK_SUPPL_PCLK,
+      CLKOP => clk_cal,
+      LOCK  => open);
 
 ---------------------------------------------------------------------------
 -- PCSA
@@ -906,7 +910,7 @@ end generate;
       CLK_READOUT        => clk_sys,    -- Clock for the readout
       REFERENCE_TIME     => cts_trigger_out,  -- Reference time input
       HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
-      HIT_CAL_IN         => CLK_SUPPL_PCLK,    -- Hits for calibrating the TDC
+      HIT_CAL_IN         => clk_cal,    -- Hits for calibrating the TDC
       -- Trigger signals from handler
       BUSRDO_RX          => cts_rdo_rx,
       BUSRDO_TX          => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR),
diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index 7e30989..e6a7573 100644
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -183,11 +183,11 @@ begin
       DEBUG_OUT      => debug_clock_reset
       );
 
---   pll_calibration : entity work.pll_in125_out33
---     port map (
---       CLK   => CLK_SUPPL_PCLK,
---       CLKOP => clk_cal,
---       LOCK  => open);
+  pll_calibration : entity work.pll_in125_out33
+    port map (
+      CLK   => CLK_SUPPL_PCLK,
+      CLKOP => clk_cal,
+      LOCK  => open);
 
 -- GSR_N <= reset_i;      
       
@@ -480,7 +480,7 @@ TEST_LINE <=   med_stat_debug(15 downto 0);
       CLK_READOUT        => clk_sys,    -- Clock for the readout
       REFERENCE_TIME     => TRIG_LEFT,  -- Reference time input
       HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
-      HIT_CAL_IN         => CLK_SUPPL_PCLK,    -- Hits for calibrating the TDC
+      HIT_CAL_IN         => clk_cal,    -- Hits for calibrating the TDC
       -- Trigger signals from handler
       BUSRDO_RX          => readout_rx,
       BUSRDO_TX          => readout_tx(0),