From: hadeshyp Date: Tue, 29 Jan 2008 15:21:32 +0000 (+0000) Subject: changed fifo behaviour, tested most parts, Jan X-Git-Tag: oldGBE~613 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=bed56f426cb020390d2a6ffd2b15cf76c0cf8191;p=trbnet.git changed fifo behaviour, tested most parts, Jan --- diff --git a/testbench/trb_net16_dummy_apl.vhd b/testbench/trb_net16_dummy_apl.vhd index 8d89593..a216298 100644 --- a/testbench/trb_net16_dummy_apl.vhd +++ b/testbench/trb_net16_dummy_apl.vhd @@ -60,6 +60,7 @@ architecture trb_net16_dummy_apl_arch of trb_net16_dummy_apl is signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic; signal next_packet_counter, packet_counter : std_logic_vector(1 downto 0); signal address, reghigh, reglow : std_logic_vector(15 downto 0); + signal state_bits : std_logic_vector(2 downto 0); begin -- address <= x"0008"; @@ -69,7 +70,17 @@ begin reghigh <= x"000B"; reglow <= x"000D"; - + process(current_state) + begin + case current_state is + when IDLE => state_bits <= "000"; + when WRITING => state_bits <= "001"; + when RUNNING => state_bits <= "010"; + when WAITING => state_bits <= "011"; + when MY_ERROR => state_bits <= "100"; + when others => state_bits <= "111"; + end case; + end process; APL_READ_OUT <= '1'; --just read, do not check APL_DTYPE_OUT <= "1001"; diff --git a/testbench/trb_net16_dummy_passive_apl.vhd b/testbench/trb_net16_dummy_passive_apl.vhd index 5acfb7a..97020f5 100644 --- a/testbench/trb_net16_dummy_passive_apl.vhd +++ b/testbench/trb_net16_dummy_passive_apl.vhd @@ -166,7 +166,7 @@ begin -- WAITING ----------------------------------------------------------------------- elsif current_state = WAITING then - if (current_TYPE_IN = TYPE_TRM and APL_PACKET_NUM_IN = "11" and APL_DATAREADY_IN = '1') then + if (APL_TYP_IN = TYPE_TRM and APL_PACKET_NUM_IN = "11" and APL_DATAREADY_IN = '1') then next_state <= IDLE; next_counter <= (others => '0'); else diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index a86c88b..0548a74 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -9,12 +9,14 @@ use work.trb_net_std.all; entity trb_net16_api_base is generic ( - API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + API_TYPE : integer range 0 to 1 := c_API_ACTIVE; FIFO_TO_INT_DEPTH : integer range 1 to 6 := std_FIFO_DEPTH; FIFO_TO_APL_DEPTH : integer range 1 to 6 := std_FIFO_DEPTH; USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL; FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES ); port( @@ -177,6 +179,26 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is ); end component; + component trb_net_sbuf is + generic ( + DATA_WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH; + VERSION: integer := SBUF_VERSION); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); + end component; -- signals for the APL to INT fifo: signal fifo_to_int_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); @@ -210,7 +232,7 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic; signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0); signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0); + signal next_APL_TYP_OUT, reg_APL_TYP_OUT, buf_APL_TYP_OUT: std_logic_vector(2 downto 0); type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB); signal out_select, last_out_select: OUTPUT_SELECT; @@ -234,7 +256,13 @@ architecture trb_net16_api_base_arch of trb_net16_api_base is type API_STATE is (IDLE, SEND_HEADER, RUNNING, SHUTDOWN, SEND_SHORT, SEND_TRAILER, WAITING,MY_ERROR); signal current_state, next_state : API_STATE; + signal throw_away : std_logic; + signal fifo_to_apl_read_before : std_logic; + signal fifo_to_int_read_before : std_logic; + signal sbuf_to_apl_next_READ : std_logic; + signal sbuf_to_apl_free : std_logic; + signal sbuf_apl_type_dataready : std_logic; begin --------------------------------------- @@ -357,7 +385,7 @@ begin FULL_OUT => fifo_to_apl_full, EMPTY_OUT => fifo_to_apl_empty ); - end generate CHECK_BUFFER6; + end generate; STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0); STAT_FIFO_TO_APL(3) <= fifo_to_apl_write; @@ -375,37 +403,119 @@ begin --------------------------------------- -- a sbuf (to_int direction) --------------------------------------- - SBUF: trb_net16_sbuf - generic map ( - VERSION => SBUF_VERSION) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => next_INT_MASTER_DATAREADY_OUT, - COMB_next_READ_OUT => sbuf_next_READ, - COMB_READ_IN => '1', - COMB_DATA_IN => next_INT_MASTER_DATA_OUT, - COMB_PACKET_NUM_IN => next_INT_MASTER_PACKET_NUM_OUT, - SYN_DATAREADY_OUT => INT_MASTER_DATAREADY_OUT, - SYN_DATA_OUT => INT_MASTER_DATA_OUT, - SYN_PACKET_NUM_OUT => INT_MASTER_PACKET_NUM_OUT, - SYN_READ_IN => INT_MASTER_READ_IN - ); + gen_int_sbuf : if SECURE_MODE_TO_INT = 1 generate + SBUF: trb_net16_sbuf + generic map ( + VERSION => SBUF_VERSION) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => next_INT_MASTER_DATAREADY_OUT, + COMB_next_READ_OUT => sbuf_next_READ, + COMB_READ_IN => '1', + COMB_DATA_IN => next_INT_MASTER_DATA_OUT, + COMB_PACKET_NUM_IN => next_INT_MASTER_PACKET_NUM_OUT, + SYN_DATAREADY_OUT => INT_MASTER_DATAREADY_OUT, + SYN_DATA_OUT => INT_MASTER_DATA_OUT, + SYN_PACKET_NUM_OUT => INT_MASTER_PACKET_NUM_OUT, + SYN_READ_IN => INT_MASTER_READ_IN + ); + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + sbuf_free <= '0'; + else + sbuf_free <= sbuf_next_READ or INT_MASTER_READ_IN; + end if; + end if; + end process; + end generate; + gen_int_nonsbuf : if SECURE_MODE_TO_INT = 0 generate + INT_MASTER_DATAREADY_OUT <= next_INT_MASTER_DATAREADY_OUT; + INT_MASTER_DATA_OUT <= next_INT_MASTER_DATA_OUT; + INT_MASTER_PACKET_NUM_OUT <= next_INT_MASTER_PACKET_NUM_OUT; + sbuf_free <= INT_MASTER_READ_IN; + end generate; + +--------------------------------------- +-- a sbuf (to_apl direction) +--------------------------------------- + gen_apl_sbuf : if SECURE_MODE_TO_APL = 1 generate + SBUF_TO_APL: trb_net16_sbuf + generic map ( + VERSION => SBUF_VERSION) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => next_APL_DATAREADY_OUT, + COMB_next_READ_OUT => sbuf_to_apl_next_READ, + COMB_READ_IN => '1', + COMB_DATA_IN => next_APL_DATA_OUT, + COMB_PACKET_NUM_IN => next_APL_PACKET_NUM_OUT, + SYN_DATAREADY_OUT => reg_APL_DATAREADY_OUT, + SYN_DATA_OUT => reg_APL_DATA_OUT, + SYN_PACKET_NUM_OUT => reg_APL_PACKET_NUM_OUT, + SYN_READ_IN => APL_READ_IN + ); + SBUF_TO_APL2: trb_net_sbuf + generic map ( + VERSION => SBUF_VERSION, + DATA_WIDTH => 3) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => next_APL_DATAREADY_OUT, + COMB_next_READ_OUT => open, + COMB_READ_IN => '1', + COMB_DATA_IN => next_APL_TYP_OUT, + SYN_DATAREADY_OUT => sbuf_apl_type_dataready, + SYN_DATA_OUT => buf_APL_TYP_OUT, + SYN_READ_IN => APL_READ_IN + ); - sbuf_free <= sbuf_next_READ; + reg_APL_TYP_OUT <= TYPE_ILLEGAL when sbuf_apl_type_dataready = '0' else buf_APL_TYP_OUT; + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + sbuf_to_apl_free <= '0'; + else + sbuf_to_apl_free <= sbuf_to_apl_next_READ; + end if; + end if; + end process; + end generate; + gen_apl_nonsbuf : if SECURE_MODE_TO_APL = 0 generate + reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT; + reg_APL_DATA_OUT <= next_APL_DATA_OUT; + reg_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT; + reg_APL_TYP_OUT <= next_APL_TYP_OUT; + sbuf_to_apl_free <= APL_READ_IN; + end generate; next_APL_DATA_OUT <= fifo_to_apl_data_out; next_APL_PACKET_NUM_OUT <= fifo_to_apl_packet_num_out; next_APL_TYP_OUT <= current_fifo_to_apl_packet_type; + APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT; + APL_DATA_OUT <= reg_APL_DATA_OUT; + APL_PACKET_NUM_OUT <= reg_APL_PACKET_NUM_OUT; + APL_TYP_OUT <= reg_APL_TYP_OUT; + APL_SEQNR_OUT <= sequence_counter; +--------------------------------------- +-- save packet type +--------------------------------------- - --this holds the current packet type from fifo_to_apl process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then + if RESET = '1' or fifo_to_apl_packet_num_out = "11" then saved_fifo_to_apl_packet_type <= TYPE_ILLEGAL; elsif fifo_to_apl_packet_num_out = "00" then saved_fifo_to_apl_packet_type <= fifo_to_apl_data_out(2 downto 0); @@ -475,14 +585,48 @@ begin end process; +--------------------------------------- +-- keep track of fifo read operations +--------------------------------------- + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + fifo_to_apl_read_before <= '0'; + else + if fifo_to_apl_read = '1' then + fifo_to_apl_read_before <= '1'; + elsif sbuf_to_apl_free = '1' or throw_away = '1' then + fifo_to_apl_read_before <= '0'; + end if; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + fifo_to_int_read_before <= '0'; + else + if fifo_to_int_read = '1' then + fifo_to_int_read_before <= '1'; + elsif next_INT_MASTER_DATAREADY_OUT = '1' and master_counter /= "00" then --implies sbuf_free + fifo_to_int_read_before <= '0'; + end if; + end if; + end if; + end process; + + gen_pas_api_fsm : if API_TYPE = 0 generate --------------------------------------- --state machine for passive api --------------------------------------- to_apl : process(fifo_to_apl_full, reg_INT_SLAVE_READ_OUT, INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, fifo_to_apl_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT, - APL_READ_IN, INT_SLAVE_DATA_IN, INT_SLAVE_PACKET_NUM_IN, APL_MY_ADDRESS_IN, - reg_APL_DATAREADY_OUT, slave_running ) + sbuf_to_apl_free, INT_SLAVE_DATA_IN, INT_SLAVE_PACKET_NUM_IN, APL_MY_ADDRESS_IN, + reg_APL_DATAREADY_OUT, slave_running, fifo_to_apl_read_before, throw_away ) begin next_INT_SLAVE_READ_OUT <= not fifo_to_apl_full; fifo_to_apl_write <= reg_INT_SLAVE_READ_OUT and INT_SLAVE_DATAREADY_IN; @@ -493,7 +637,7 @@ begin next_wait_for_answer <= '0'; get_slave_running <= '0'; - if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and (APL_READ_IN = '1' or state_to_apl = WRONG_ADDR) then + if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and (sbuf_to_apl_free = '1' or state_to_apl = WRONG_ADDR) then next_state_to_apl <= IDLE; end if; @@ -519,14 +663,14 @@ begin when WRONG_ADDR => fifo_to_apl_read <= not fifo_to_apl_empty; when MY_ADDR => - next_APL_DATAREADY_OUT <= not fifo_to_apl_empty and or_all(fifo_to_apl_packet_num_out); - fifo_to_apl_read <= not fifo_to_apl_empty and( (not fifo_to_apl_empty and or_all(fifo_to_apl_packet_num_out) and APL_READ_IN) - or not or_all(fifo_to_apl_packet_num_out)); + next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and or_all(fifo_to_apl_packet_num_out); + fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not sbuf_to_apl_free and not throw_away); + throw_away <= not or_all(fifo_to_apl_packet_num_out); end case; end process; to_int : process(state_to_int, send_trm_wrong_addr, wait_for_answer, APL_SHORT_TRANSFER_IN, APL_SEND_IN, - master_counter, sbuf_free, fifo_to_int_empty, sequence_counter) + master_counter, sbuf_free, fifo_to_int_empty, sequence_counter, fifo_to_int_read_before) begin next_state_to_int <= state_to_int; update_registered_trailer <= '0'; @@ -548,62 +692,53 @@ begin if APL_SEND_IN = '1' then if APL_SHORT_TRANSFER_IN = '1' then next_state_to_int <= SEND_SHORT; - update_registered_trailer <= '1'; - else + else next_state_to_int <= SEND_HEADER; - out_select <= HDR; - next_INT_MASTER_DATAREADY_OUT <= '1'; end if; end if; when SEND_SHORT => - out_select <= TRM; if APL_SEND_IN = '0' then + update_registered_trailer <= '1'; next_state_to_int <= SEND_TRAILER; - next_INT_MASTER_DATAREADY_OUT <= '1'; end if; when SEND_HEADER => out_select <= HDR; next_INT_MASTER_DATAREADY_OUT <= sbuf_free; - if master_counter = "00" then + if master_counter = "11" and sbuf_free = '1' then next_state_to_int <= RUNNING; - next_INT_MASTER_DATAREADY_OUT <= '0'; end if; when RUNNING => - fifo_to_int_read <= sbuf_free; - next_INT_MASTER_DATAREADY_OUT <= sbuf_free and ((not fifo_to_int_empty and APL_SEND_IN) or not APL_SEND_IN); + fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(master_counter); + next_INT_MASTER_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or not or_all(master_counter)); if APL_SEND_IN = '0' then -- terminate the transfer update_registered_trailer <= '1'; - next_INT_MASTER_DATAREADY_OUT <= sbuf_free; +-- next_INT_MASTER_DATAREADY_OUT <= sbuf_free; if fifo_to_int_empty = '1' then -- immediate stop - if master_counter = "11" then + if master_counter = "11" and sbuf_free = '1' then next_state_to_int <= SEND_TRAILER; - out_select <= TRM_COMB; end if; else next_state_to_int <= SHUTDOWN; end if; end if; when SHUTDOWN => - next_INT_MASTER_DATAREADY_OUT <= sbuf_free; - fifo_to_int_read <= not fifo_to_int_empty and sbuf_free; - if master_counter = "00" and fifo_to_int_empty = '1' and sbuf_free = '1' then + fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(master_counter); + next_INT_MASTER_DATAREADY_OUT <= sbuf_free and fifo_to_int_read_before; + if master_counter = "11" and fifo_to_int_empty = '1' and sbuf_free = '1' then --implicit: fill with padding words next_state_to_int <= SEND_TRAILER; - out_select <= TRM; + --out_select <= TRM; end if; when SEND_TRAILER => out_select <= TRM; next_INT_MASTER_DATAREADY_OUT <= sbuf_free; - if master_counter = "00" then + if master_counter = "11" and sbuf_free = '1' then next_state_to_int <= IDLE; - next_INT_MASTER_DATAREADY_OUT <= '0'; + --next_INT_MASTER_DATAREADY_OUT <= '0'; next_sequence_counter <= sequence_counter +1; release_slave_running <= '1'; end if; end case; - if master_counter = "00" or fifo_to_int_empty = '1' then - fifo_to_int_read <= '0'; - end if; end process; process(CLK) @@ -647,26 +782,28 @@ begin APL_SHORT_TRANSFER_IN, APL_WRITE_IN, fifo_to_int_empty, sbuf_free, master_counter, fifo_to_apl_full, reg_APL_DATAREADY_OUT, reg_INT_SLAVE_READ_OUT, - INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, APL_READ_IN, + INT_SLAVE_DATAREADY_IN, fifo_to_apl_empty, sbuf_to_apl_free, fifo_to_apl_packet_num_out, reg_APL_TYP_OUT, - reg_APL_PACKET_NUM_OUT, last_out_select) + reg_APL_PACKET_NUM_OUT, last_out_select, fifo_to_int_read_before) begin - next_state <= MY_ERROR; - next_INT_MASTER_DATAREADY_OUT <= '0'; + next_state <= current_state; out_select <= DAT; update_registered_trailer <= '0'; fifo_to_int_read <= '0'; - next_INT_SLAVE_READ_OUT <= '0'; - fifo_to_apl_write <= '0'; - next_APL_DATAREADY_OUT <= '0'; - fifo_to_apl_read <= '0'; + --next_INT_SLAVE_READ_OUT <= '0'; + --fifo_to_apl_write <= '0'; + --next_APL_DATAREADY_OUT <= '0'; + --fifo_to_apl_read <= '0'; next_slave_running <= slave_running; next_sequence_counter <= sequence_counter; + + next_INT_MASTER_DATAREADY_OUT <= fifo_to_int_read_before; + ------------------------------------------------------------------------------- -- IDLE ------------------------------------------------------------------------------- if current_state = IDLE then - if APL_SEND_IN = '1' then + if APL_SEND_IN = '1' and sbuf_free = '1' then if APL_SHORT_TRANSFER_IN = '1' then -- and APL_WRITE_IN = '0' and fifo_to_int_empty = '1' next_state <= SEND_SHORT; -- no next data word, waiting for falling edge of APL_SEND_IN update_registered_trailer <= '1'; -- moved from SEND_SHORT @@ -675,16 +812,13 @@ begin out_select <= HDR; next_INT_MASTER_DATAREADY_OUT <= '1'; end if; -- next word will be a header - else - next_state <= IDLE; end if; -- APL_SEND_IN ------------------------------------------------------------------------------- -- SEND_SHORT ------------------------------------------------------------------------------- elsif current_state = SEND_SHORT then - next_state <= SEND_SHORT; out_select <= TRM; - if APL_SEND_IN = '0' then -- terminate the transfer + if APL_SEND_IN = '0' and sbuf_free = '1' then -- terminate the transfer next_state <= SEND_TRAILER; next_INT_MASTER_DATAREADY_OUT <= '1'; end if; @@ -692,69 +826,50 @@ begin -- SEND_HEADER ------------------------------------------------------------------------------- elsif current_state = SEND_HEADER then - out_select <= HDR; - if sbuf_free = '1' then - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; if master_counter = "00" then next_state <= RUNNING; - next_INT_MASTER_DATAREADY_OUT <= '0'; + out_select <= DAT; + --next_INT_MASTER_DATAREADY_OUT <= '0'; else - next_state <= SEND_HEADER; + out_select <= HDR; + next_INT_MASTER_DATAREADY_OUT <= '1'; end if; ------------------------------------------------------------------------------- -- RUNNING ------------------------------------------------------------------------------- elsif current_state = RUNNING then - if sbuf_free = '1' then - fifo_to_int_read <= '1'; - end if; + out_select <= DAT; + fifo_to_int_read <= not fifo_to_int_empty and not (fifo_to_int_read_before and not sbuf_free); + next_INT_MASTER_DATAREADY_OUT <= fifo_to_int_read_before or not or_all(master_counter); if APL_SEND_IN = '0' then -- terminate the transfer update_registered_trailer <= '1'; - if fifo_to_int_empty = '1' then -- immediate stop - next_INT_MASTER_DATAREADY_OUT <= sbuf_free; - if master_counter = "11" then + if fifo_to_int_empty = '1' and fifo_to_int_read_before = '0' and sbuf_free = '1' then -- immediate stop + next_INT_MASTER_DATAREADY_OUT <= '1'; + if master_counter = "00" then --????? next_state <= SEND_TRAILER; out_select <= TRM_COMB; end if; else next_state <= SHUTDOWN; - if sbuf_free = '1' then - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; end if; - else -- APL_SEND_IN: still running - next_state <= RUNNING; - if fifo_to_int_empty = '0' and sbuf_free = '1' then - -- data words have to be prepared - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; -- fifo_to_int_empty = '0' end if; ------------------------------------------------------------------------------- -- SHUTDOWN: Empty the pipe ------------------------------------------------------------------------------- elsif current_state = SHUTDOWN then - next_state <= SHUTDOWN; - if sbuf_free = '1' then - next_INT_MASTER_DATAREADY_OUT <= '1'; - if fifo_to_int_empty = '0' then - -- data words have to be prepared - fifo_to_int_read <= '1'; - elsif master_counter = "00" then - -- we are done - --implicit: fill with padding words - next_state <= SEND_TRAILER; - out_select <= TRM; - end if; + out_select <= DAT; + next_INT_MASTER_DATAREADY_OUT <= fifo_to_int_read_before or not or_all(master_counter); + fifo_to_int_read <= not fifo_to_int_empty and not (fifo_to_int_read_before and not sbuf_free); + if fifo_to_int_empty = '1' and fifo_to_int_read_before = '0' and sbuf_free = '1' then -- and master_counter = "00" + next_state <= SEND_TRAILER; + out_select <= TRM; end if; ------------------------------------------------------------------------------- -- SEND_TRAILER ------------------------------------------------------------------------------- elsif current_state = SEND_TRAILER then out_select <= TRM; - if sbuf_free = '1' then - next_INT_MASTER_DATAREADY_OUT <= '1'; - end if; + next_INT_MASTER_DATAREADY_OUT <= '1'; if master_counter = "00" then next_state <= WAITING; next_INT_MASTER_DATAREADY_OUT <= '0'; @@ -762,47 +877,34 @@ begin next_sequence_counter <= sequence_counter +1; next_slave_running <= '0'; end if; - else - next_state <= SEND_TRAILER; end if; ------------------------------------------------------------------------------- -- WAITING => for the answer or a request ------------------------------------------------------------------------------- elsif current_state = WAITING then - next_state <= WAITING; - -- here we have to supply the receiver port - -- part 1: connection to network - if fifo_to_apl_full = '0' or (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then - next_INT_SLAVE_READ_OUT <= '1'; - end if; - if reg_INT_SLAVE_READ_OUT = '1' and INT_SLAVE_DATAREADY_IN = '1' then - fifo_to_apl_write <= '1'; -- use fifo as the pipe - end if; - - -- part 2: connection to apl - -- if fifo_to_apl_empty = '0' then - if fifo_to_apl_empty = '0' --and not (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') - and fifo_to_apl_packet_num_out /= "00" then --is this really correct???? - next_APL_DATAREADY_OUT <= '1'; - end if; -- read/no read - - if (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') or fifo_to_apl_packet_num_out = "00" then - -- valid read - fifo_to_apl_read <= not fifo_to_apl_empty; - if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT= "11" and (APL_READ_IN = '1' and reg_APL_DATAREADY_OUT = '1') - then --fifo_to_apl_read = '1' + if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and (sbuf_to_apl_free = '1' and reg_APL_DATAREADY_OUT = '1') then + -- next_state <= IDLE; next_sequence_counter <= sequence_counter +1; - end if; end if; -- MISSING: SEQNR check - -- OPEN QUESTION: Address matching? makes sense for a reply transfer? - end if; + end if; if master_counter = "00" or fifo_to_int_empty = '1' then fifo_to_int_read <= '0'; end if; + if sbuf_free = '0' then + next_INT_MASTER_DATAREADY_OUT <= '0'; + end if; end process; - + + + next_INT_SLAVE_READ_OUT <= not fifo_to_apl_full; + fifo_to_apl_write <= reg_INT_SLAVE_READ_OUT and INT_SLAVE_DATAREADY_IN; + + fifo_to_apl_read <= sbuf_to_apl_free; + next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and or_all(fifo_to_apl_packet_num_out); + throw_away <= not or_all(fifo_to_apl_packet_num_out); + CLK_REG: process(CLK) begin if rising_edge(CLK) then @@ -873,40 +975,11 @@ begin INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT; - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_APL_DATA_OUT <= (others => '0'); - reg_APL_PACKET_NUM_OUT <= (others => '0'); - reg_APL_TYP_OUT <= (others => '0'); - elsif APL_READ_IN = '1' then --CLK_EN - reg_APL_DATA_OUT <= next_APL_DATA_OUT; - reg_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT; - reg_APL_TYP_OUT <= next_APL_TYP_OUT; - end if; - end if; - end process; - - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_APL_DATAREADY_OUT <= '0'; - elsif CLK_EN = '1' then - reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT; - end if; - end if; - end process; -- connect receiver fifo_to_apl_data_in <= INT_SLAVE_DATA_IN; fifo_to_apl_packet_num_in <= INT_SLAVE_PACKET_NUM_IN; - APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT; - APL_DATA_OUT <= reg_APL_DATA_OUT; - APL_PACKET_NUM_OUT <= reg_APL_PACKET_NUM_OUT; - APL_TYP_OUT <= reg_APL_TYP_OUT; genAPL_RUN_OUT_0: if API_TYPE = 0 generate APL_RUN_OUT <= slave_running; @@ -915,7 +988,7 @@ begin APL_RUN_OUT <= '0' when current_state = IDLE else '1'; end generate; - APL_SEQNR_OUT <= sequence_counter; + REG3 : process(CLK) begin diff --git a/trb_net16_endpoint_0_trg_1_api.vhd b/trb_net16_endpoint_0_trg_1_api.vhd index 5b295cb..85d8511 100644 --- a/trb_net16_endpoint_0_trg_1_api.vhd +++ b/trb_net16_endpoint_0_trg_1_api.vhd @@ -15,14 +15,14 @@ entity trb_net16_endpoint_0_trg_1_api is generic ( API_TYPE : integer range 0 to 1 := c_API_PASSIVE; INIT_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; - REPLY_DEPTH : integer range 0 to 6 := c_FIFO_NONE; + REPLY_DEPTH : integer range 0 to 6 := c_FIFO_SMALL; FIFO_TO_INT_DEPTH : integer range 0 to 6 := c_FIFO_SMALL; FIFO_TO_APL_DEPTH : integer range 0 to 6 := c_FIFO_SMALL; SBUF_VERSION : integer range 0 to 1 := c_SBUF_FULL; MUX_SECURE_MODE : integer range 0 to 1 := c_NON_SECURE_MODE; - IBUF_SECURE_MODE : integer range 0 to 1 := c_NON_SECURE_MODE; + IBUF_SECURE_MODE : integer range 0 to 1 := c_SECURE_MODE; OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; - INIT_CAN_SEND_DATA : integer range 0 to 1 := c_NO; + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES; DAT_CHANNEL : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL ); diff --git a/trb_net16_fifo.vhd b/trb_net16_fifo.vhd index 6b411ef..2ea2406 100644 --- a/trb_net16_fifo.vhd +++ b/trb_net16_fifo.vhd @@ -33,49 +33,49 @@ entity trb_net16_fifo is end entity; -architecture trb_net16_fifo_arch of trb_net16_fifo is - - component trb_net_fifo is - generic ( - WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH; -- FIFO word width - DEPTH : integer := DEPTH + 2; - FORCE_LUT : integer := 0 - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic; - DEPTH_OUT : out std_logic_vector(7 downto 0) - ); - end component; - - signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH-1 downto 0); - signal depth16 : std_logic_vector(7 downto 0); - -begin - din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; - din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; - DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH); - DEPTH_OUT <= conv_std_logic_vector(DEPTH, 8); - - fifo : trb_net_fifo - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => din, - WRITE_ENABLE_IN => WRITE_ENABLE_IN, - DATA_OUT => dout, - READ_ENABLE_IN => READ_ENABLE_IN, - FULL_OUT => FULL_OUT, - EMPTY_OUT => EMPTY_OUT, - DEPTH_OUT => depth16 - ); -end architecture; +--architecture trb_net16_fifo_arch of trb_net16_fifo is +-- +-- component trb_net16_fifo is +-- generic ( +-- WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH; -- FIFO word width +-- DEPTH : integer := DEPTH + 2; +-- FORCE_LUT : integer := 0 +-- ); +-- port ( +-- CLK : in std_logic; +-- RESET : in std_logic; +-- CLK_EN : in std_logic; +-- DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data +-- WRITE_ENABLE_IN : in std_logic; +-- DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data +-- READ_ENABLE_IN : in std_logic; +-- FULL_OUT : out std_logic; -- Full Flag +-- EMPTY_OUT : out std_logic; +-- DEPTH_OUT : out std_logic_vector(7 downto 0) +-- ); +-- end component; +-- +-- signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH-1 downto 0); +-- signal depth16 : std_logic_vector(7 downto 0); +-- +--begin +-- din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; +-- din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; +-- DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); +-- PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH); +-- DEPTH_OUT <= conv_std_logic_vector(DEPTH, 8); +-- +-- fifo : trb_net_fifo +-- port map( +-- CLK => CLK, +-- RESET => RESET, +-- CLK_EN => CLK_EN, +-- DATA_IN => din, +-- WRITE_ENABLE_IN => WRITE_ENABLE_IN, +-- DATA_OUT => dout, +-- READ_ENABLE_IN => READ_ENABLE_IN, +-- FULL_OUT => FULL_OUT, +-- EMPTY_OUT => EMPTY_OUT, +-- DEPTH_OUT => depth16 +-- ); +--end architecture; diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index 285aeb4..8128f3c 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -11,10 +11,10 @@ use work.trb_net_std.all; entity trb_net16_ibuf is generic ( - DEPTH : integer range 0 to 7 := std_FIFO_DEPTH; + DEPTH : integer range 0 to 7 := c_FIFO_BRAM; USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - SECURE_MODE : integer range 0 to 1 := std_IBUF_SECURE_MODE + SECURE_MODE : integer range 0 to 1 := c_YES --use sbuf in med_to_api direction? ); port( @@ -123,7 +123,13 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is signal next_rec_buffer_size_out, current_rec_buffer_size_out: std_logic_vector(3 downto 0); signal buf_INT_DATAREADY_OUT : std_logic; + signal last_fifo_read : std_logic; + signal throw_away : std_logic; + signal fifo_read_before : std_logic; begin +------------------------ +--the input fifo +------------------------ FIFO: trb_net16_fifo generic map ( DEPTH => DEPTH @@ -146,7 +152,9 @@ begin fifo_data_in <= MED_DATA_IN; fifo_packet_num_in <= MED_PACKET_NUM_IN; - --this holds the current packet type +------------------------ +--save the current packet type +------------------------ process(CLK) begin if rising_edge(CLK) then @@ -174,7 +182,9 @@ begin current_fifo_packet_type <= fifo_data_out(2 downto 0) when (fifo_packet_num_out = "00") else saved_fifo_packet_type; - +------------------------ +--control incoming data +------------------------ FILTER_DATAREADY_IN : process(MED_DATA_IN, MED_DATAREADY_IN, MED_ERROR_IN, MED_PACKET_NUM_IN, fifo_full, is_locked, current_rec_buffer_size_out, current_error_state, reg_read_out, current_packet_type) @@ -223,6 +233,9 @@ begin end if; end process; +------------------------ +--generate output logic +------------------------ gensecure : if SECURE_MODE = 1 generate SBUF: trb_net16_sbuf generic map ( @@ -243,7 +256,7 @@ begin SYN_READ_IN => INT_READ_IN ); - sbuf_free <= comb_next_read or INT_READ_IN; --sbuf killed + sbuf_free <= comb_next_read; --sbuf killed end generate; gen_notsecure : if SECURE_MODE = 0 generate INT_DATA_OUT <= tmp_INT_DATA_OUT; @@ -254,26 +267,61 @@ begin -- this process controls what will be forwarded to the internal point - DATA_OUT : process (INT_HEADER_IN, fifo_data_out, - release_locked, is_locked, sbuf_free, fifo_empty, - fifo_packet_num_out, current_fifo_packet_type) +-- DATA_OUT : process (INT_HEADER_IN, fifo_data_out, +-- release_locked, is_locked, sbuf_free, fifo_empty, +-- fifo_packet_num_out, current_fifo_packet_type) +-- begin +-- tmp_INT_DATA_OUT <= fifo_data_out; +-- tmp_INT_PACKET_NUM_OUT <= fifo_packet_num_out; +-- tmp_INT_DATAREADY_OUT <= '0'; +-- got_eob_out <= '0'; +-- got_locked <= is_locked; +-- if SECURE_MODE = 1 then +-- fifo_read <= sbuf_free and not fifo_empty; +-- else +-- fifo_read <= INT_READ_IN and buf_INT_DATAREADY_OUT and not fifo_empty; +-- end if; +-- -- if current_fifo_packet_type = TYPE_EOB and fifo_packet_num_out = "00" and USE_ACKNOWLEDGE = 1 then +-- -- tmp_INT_DATA_OUT(2 downto 0) <= TYPE_DAT; +-- -- end if; +-- if fifo_empty = '0' and sbuf_free = '1' then +-- if current_fifo_packet_type /= TYPE_EOB then +-- tmp_INT_DATAREADY_OUT <= '1'; +-- end if; +-- if USE_ACKNOWLEDGE = 1 then +-- if (current_fifo_packet_type = TYPE_EOB or current_fifo_packet_type = TYPE_TRM) +-- and fifo_packet_num_out = "11" then +-- got_eob_out <= '1'; +-- end if; +-- if current_fifo_packet_type = TYPE_TRM then +-- got_locked <= is_locked or not release_locked; +-- end if; +-- end if; +-- end if; +-- end process; + + +--gen_secure_output : if SECURE_MODE = 0 generate + process(fifo_data_out, fifo_packet_num_out, is_locked, sbuf_free, fifo_empty, last_fifo_read, current_fifo_packet_type, + release_locked) begin tmp_INT_DATA_OUT <= fifo_data_out; tmp_INT_PACKET_NUM_OUT <= fifo_packet_num_out; - tmp_INT_DATAREADY_OUT <= '0'; got_eob_out <= '0'; got_locked <= is_locked; - if SECURE_MODE = 1 then - fifo_read <= sbuf_free and not fifo_empty; + throw_away <= '0'; + + fifo_read <= not fifo_empty and not (fifo_read_before and not INT_READ_IN and not throw_away); + + if (fifo_read_before = '1' and (current_fifo_packet_type /= TYPE_EOB) and sbuf_free = '1') then + tmp_INT_DATAREADY_OUT <= '1'; else - fifo_read <= INT_READ_IN and buf_INT_DATAREADY_OUT and not fifo_empty; + tmp_INT_DATAREADY_OUT <= '0'; end if; --- if current_fifo_packet_type = TYPE_EOB and fifo_packet_num_out = "00" and USE_ACKNOWLEDGE = 1 then --- tmp_INT_DATA_OUT(2 downto 0) <= TYPE_DAT; --- end if; - if fifo_empty = '0' and sbuf_free = '1' then - if current_fifo_packet_type /= TYPE_EOB then - tmp_INT_DATAREADY_OUT <= '1'; + + if last_fifo_read = '1' then + if current_fifo_packet_type = TYPE_EOB then + throw_away <= '1'; end if; if USE_ACKNOWLEDGE = 1 then if (current_fifo_packet_type = TYPE_EOB or current_fifo_packet_type = TYPE_TRM) @@ -287,8 +335,34 @@ begin end if; end process; + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + last_fifo_read <= '0'; + else + last_fifo_read <= fifo_read; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + fifo_read_before <= '0'; + else + if fifo_read = '1' then + fifo_read_before <= '1'; + elsif INT_READ_IN = '1' or throw_away = '1' then + fifo_read_before <= '0'; + end if; + end if; + end if; + end process; +--end generate; + ---BUGBUG HDR retransmit needed -> not here but in HUB release_locked <= CTRL_LOCKED(0); STAT_LOCKED(0) <= is_locked; diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 1946a6a..d53ff12 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -129,7 +129,7 @@ begin send_DATA <= not TRANSMITTED_BUFFERS(1);--'1' when (TRANSMITTED_BUFFERS(1) = '0') else '0'; --only for full obuf - send_EOB <= '1' when (CURRENT_DATA_COUNT = max_DATA_COUNT_minus_one) else '0'; + send_EOB <= '1' when (CURRENT_DATA_COUNT = max_DATA_COUNT_minus_one and saved_packet_type /= TYPE_TRM) else '0'; -- buffer registers @@ -143,6 +143,7 @@ begin SEND_ACK_IN <= CTRL_BUFFER(8); GOT_ACK_IN <= CTRL_BUFFER(9); end generate; + gen1a : if USE_ACKNOWLEDGE = 0 generate send_EOB <= '0'; send_ACK <= '0'; @@ -156,7 +157,6 @@ begin max_DATA_COUNT_minus_one <= (others => '0'); next_max_DATA_COUNT_minus_one <= (others => '0'); next_TRANSMITTED_BUFFERS <= (others => '0'); - end generate; GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN, INT_DATA_IN) @@ -228,6 +228,9 @@ begin current_output_data_buffer <= current_DATA_word; -- end if; comb_dataready <= '1'; --I hope sbuf can store + if transfer_counter = "10" then + next_DATA_COUNT <= CURRENT_DATA_COUNT +1; + end if; if transfer_counter = "11" then if saved_packet_type = TYPE_TRM then -- or saved_packet_type = TYPE_EOB next_DATA_COUNT <= (others => '0'); @@ -235,8 +238,6 @@ begin if TRANSMITTED_BUFFERS(0) = '1' then next_INT_READ_OUT <= '0'; end if; - else - next_DATA_COUNT <= CURRENT_DATA_COUNT +1; end if; if send_EOB = '1' then next_INT_READ_OUT <= '0'; @@ -328,10 +329,11 @@ begin end if; end process; + next_max_DATA_COUNT_minus_one <= - conv_std_logic_vector(3, DATA_COUNT_WIDTH) when REC_BUFFER_SIZE_IN="0010" else - conv_std_logic_vector(7, DATA_COUNT_WIDTH) when REC_BUFFER_SIZE_IN="0011" else - (others => '1') when REC_BUFFER_SIZE_IN(3 downto 1)="011" else --this is bram or infty + conv_std_logic_vector(3, DATA_COUNT_WIDTH) when REC_BUFFER_SIZE_IN="0010" else + conv_std_logic_vector(7, DATA_COUNT_WIDTH) when REC_BUFFER_SIZE_IN="0011" else + conv_std_logic_vector(127, DATA_COUNT_WIDTH)when REC_BUFFER_SIZE_IN(3 downto 1)="011" else --this is bram or infty conv_std_logic_vector(1, DATA_COUNT_WIDTH); reg_max_DATA_COUNT : process(CLK) diff --git a/trb_net16_sbuf.vhd b/trb_net16_sbuf.vhd index a694d3a..a7a4504 100644 --- a/trb_net16_sbuf.vhd +++ b/trb_net16_sbuf.vhd @@ -64,17 +64,10 @@ component trb_net_sbuf is COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - -- the COMB_next_READ_OUT should be connected via comb. logic to a register - -- to provide COMB_READ_IN (feedback path with 1 cycle delay) - -- The "REAL" READ_OUT can be constructed in the comb via COMB_next_READ_ - -- OUT and the READ_IN: If one of these is ='1', no problem to read in next - -- step. COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - -- Port to synchronous output. SYN_DATAREADY_OUT: out STD_LOGIC; SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word SYN_READ_IN: in STD_LOGIC; - -- Status and control port STAT_BUFFER: out STD_LOGIC ); end component; diff --git a/trb_net_dummy_fifo.vhd b/trb_net_dummy_fifo.vhd index 6f8a20a..19835da 100644 --- a/trb_net_dummy_fifo.vhd +++ b/trb_net_dummy_fifo.vhd @@ -22,7 +22,7 @@ entity trb_net_dummy_fifo is FULL_OUT : out std_logic; -- Full Flag EMPTY_OUT : out std_logic; DEPTH_OUT : out std_logic_vector(7 downto 0) - ); + ); end trb_net_dummy_fifo; @@ -65,7 +65,7 @@ architecture arch_trb_net_dummy_fifo of trb_net_dummy_fifo is current_FULL <= '0'; elsif CLK_EN = '1' then current_EMPTY <= next_EMPTY; - current_FULL <= next_FULL; + current_FULL <= next_FULL; end if; end if; end process; @@ -77,8 +77,6 @@ architecture arch_trb_net_dummy_fifo of trb_net_dummy_fifo is current_DOUT <= (others => '0'); elsif WRITE_ENABLE_IN = '1' then current_DOUT <= DATA_IN; - else - current_DOUT <= current_DOUT; end if; end if; end process; diff --git a/xilinx/trb_net16_fifo_arch.vhd b/xilinx/trb_net16_fifo_arch.vhd new file mode 100644 index 0000000..76e6061 --- /dev/null +++ b/xilinx/trb_net16_fifo_arch.vhd @@ -0,0 +1,157 @@ +library ieee; + +use ieee.std_logic_1164.all; +USE ieee.std_logic_signed.ALL; +USE IEEE.numeric_std.ALL; +use work.trb_net_std.all; + +-- entity trb_net16_fifo is +-- generic ( +-- DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets +-- ); +-- port ( +-- CLK : in std_logic; +-- RESET : in std_logic; +-- CLK_EN : in std_logic; +-- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data +-- PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data +-- WRITE_ENABLE_IN : in std_logic; +-- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data +-- PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data +-- READ_ENABLE_IN : in std_logic; +-- FULL_OUT : out std_logic; -- Full Flag +-- EMPTY_OUT : out std_logic; +-- DEPTH_OUT : out std_logic_vector(7 downto 0) +-- ); +-- end entity; + +architecture arch_trb_net16_fifo of trb_net16_fifo is + component xilinx_fifo_18x1k + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic; + data_count: OUT std_logic_VECTOR(3 downto 0) + ); + end component; + + component xilinx_fifo_18x16 + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic + ); + end component; + + component xilinx_fifo_18x32 + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic + ); + end component; + + + component xilinx_fifo_18x64 + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic + ); + end component; + + signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH-1 downto 0); + signal depth16 : std_logic_vector(7 downto 0); + +begin + din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; + din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; + DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH); + + + gen_FIFO6 : if DEPTH = 6 generate + fifo:xilinx_fifo_18x1k + port map ( + clk => CLK, + rd_en => READ_ENABLE_IN, + wr_en => WRITE_ENABLE_IN, + din => din, + sinit => RESET, + dout => dout, + full => FULL_OUT, + empty => EMPTY_OUT, + data_count => open + ); + end generate; + + + gen_FIFO1 : if DEPTH = 1 generate + fifo:xilinx_fifo_18x16 + port map ( + clk => CLK, + rd_en => READ_ENABLE_IN, + wr_en => WRITE_ENABLE_IN, + din => din, + sinit => RESET, + dout => dout, + full => FULL_OUT, + empty => EMPTY_OUT + ); + end generate; + + gen_FIFO2 : if DEPTH = 2 generate + fifo:xilinx_fifo_18x32 + port map ( + clk => CLK, + rd_en => READ_ENABLE_IN, + wr_en => WRITE_ENABLE_IN, + din => din, + sinit => RESET, + dout => dout, + full => FULL_OUT, + empty => EMPTY_OUT + ); + end generate; + + + gen_FIFO3 : if DEPTH = 3 generate + fifo:xilinx_fifo_18x64 + port map ( + clk => CLK, + rd_en => READ_ENABLE_IN, + wr_en => WRITE_ENABLE_IN, + din => din, + sinit => RESET, + dout => dout, + full => FULL_OUT, + empty => EMPTY_OUT + ); + end generate; + + + DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8)); + +end architecture; + + diff --git a/xilinx/xilinx_fifo_18x16.vhd b/xilinx/xilinx_fifo_18x16.vhd new file mode 100644 index 0000000..c873934 --- /dev/null +++ b/xilinx/xilinx_fifo_18x16.vhd @@ -0,0 +1,105 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x16.vhd when simulating +-- the core, xilinx_fifo_18x16. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x16 IS + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +END xilinx_fifo_18x16; + +ARCHITECTURE xilinx_fifo_18x16_a OF xilinx_fifo_18x16 IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x16 + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x16 use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) + generic map( + c_read_data_width => 18, + c_has_wr_ack => 0, + c_dcount_width => 1, + c_has_wr_err => 0, + c_wr_err_low => 1, + c_wr_ack_low => 1, + c_enable_rlocs => 0, + c_has_dcount => 0, + c_rd_err_low => 1, + c_rd_ack_low => 1, + c_read_depth => 16, + c_has_rd_ack => 0, + c_write_depth => 16, + c_ports_differ => 0, + c_memory_type => 0, + c_write_data_width => 18, + c_has_rd_err => 0); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x16 + port map ( + clk => clk, + sinit => sinit, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty); +-- synopsys translate_on + +END xilinx_fifo_18x16_a; + diff --git a/xilinx/xilinx_fifo_18x16.xco b/xilinx/xilinx_fifo_18x16.xco new file mode 100644 index 0000000..ad8b95c --- /dev/null +++ b/xilinx/xilinx_fifo_18x16.xco @@ -0,0 +1,41 @@ +# BEGIN Project Options +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = . +SET speedgrade = -10 +SET simulationfiles = Behavioral +SET asysymbol = True +SET addpads = False +SET device = xc4vlx40 +SET implementationfiletype = Edif +SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = ff1148 +SET createndf = False +SET designentry = VHDL +SET devicefamily = virtex4 +SET formalverification = False +SET removerpms = False +# END Project Options +# BEGIN Select +SELECT Synchronous_FIFO family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET memory_type=Distributed_Memory +CSET write_acknowledge_flag=false +CSET data_width=18 +CSET write_error_flag=false +CSET read_acknowledge_sense=Active_Low +CSET data_count_width=1 +CSET fifo_depth=16 +CSET component_name=xilinx_fifo_18x16 +CSET data_count=false +CSET read_acknowledge_flag=false +CSET read_error_sense=Active_Low +CSET read_error_flag=false +CSET write_acknowledge_sense=Active_Low +CSET write_error_sense=Active_Low +# END Parameters +GENERATE + diff --git a/xilinx/xilinx_fifo_18x1k.vhd b/xilinx/xilinx_fifo_18x1k.vhd new file mode 100644 index 0000000..f654692 --- /dev/null +++ b/xilinx/xilinx_fifo_18x1k.vhd @@ -0,0 +1,108 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x1k.vhd when simulating +-- the core, xilinx_fifo_18x1k. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x1k IS + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic; + data_count: OUT std_logic_VECTOR(3 downto 0)); +END xilinx_fifo_18x1k; + +ARCHITECTURE xilinx_fifo_18x1k_a OF xilinx_fifo_18x1k IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x1k + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic; + data_count: OUT std_logic_VECTOR(3 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x1k use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) + generic map( + c_read_data_width => 18, + c_has_wr_ack => 0, + c_dcount_width => 4, + c_has_wr_err => 0, + c_wr_err_low => 1, + c_wr_ack_low => 1, + c_enable_rlocs => 0, + c_has_dcount => 1, + c_rd_err_low => 1, + c_rd_ack_low => 1, + c_read_depth => 1024, + c_has_rd_ack => 0, + c_write_depth => 1024, + c_ports_differ => 0, + c_memory_type => 1, + c_write_data_width => 18, + c_has_rd_err => 0); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x1k + port map ( + clk => clk, + sinit => sinit, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty, + data_count => data_count); +-- synopsys translate_on + +END xilinx_fifo_18x1k_a; + diff --git a/xilinx/xilinx_fifo_18x1k.xco b/xilinx/xilinx_fifo_18x1k.xco new file mode 100644 index 0000000..c913add --- /dev/null +++ b/xilinx/xilinx_fifo_18x1k.xco @@ -0,0 +1,41 @@ +# BEGIN Project Options +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = /d/jspc19/trb/ot_trb2/ise8 +SET speedgrade = -10 +SET simulationfiles = Behavioral +SET asysymbol = True +SET addpads = False +SET device = xc4vlx40 +SET implementationfiletype = Edif +SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = ff1148 +SET createndf = False +SET designentry = VHDL +SET devicefamily = virtex4 +SET formalverification = False +SET removerpms = False +# END Project Options +# BEGIN Select +SELECT Synchronous_FIFO family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET memory_type=Block_Memory +CSET write_acknowledge_flag=false +CSET data_width=18 +CSET write_error_flag=false +CSET read_acknowledge_sense=Active_Low +CSET data_count_width=4 +CSET fifo_depth=1024 +CSET component_name=xilinx_fifo_18x1k +CSET data_count=true +CSET read_acknowledge_flag=false +CSET read_error_sense=Active_Low +CSET read_error_flag=false +CSET write_acknowledge_sense=Active_Low +CSET write_error_sense=Active_Low +# END Parameters +GENERATE + diff --git a/xilinx/xilinx_fifo_18x32.vhd b/xilinx/xilinx_fifo_18x32.vhd new file mode 100644 index 0000000..3117180 --- /dev/null +++ b/xilinx/xilinx_fifo_18x32.vhd @@ -0,0 +1,105 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x32.vhd when simulating +-- the core, xilinx_fifo_18x32. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x32 IS + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +END xilinx_fifo_18x32; + +ARCHITECTURE xilinx_fifo_18x32_a OF xilinx_fifo_18x32 IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x32 + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x32 use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) + generic map( + c_read_data_width => 18, + c_has_wr_ack => 0, + c_dcount_width => 1, + c_has_wr_err => 0, + c_wr_err_low => 1, + c_wr_ack_low => 1, + c_enable_rlocs => 0, + c_has_dcount => 0, + c_rd_err_low => 1, + c_rd_ack_low => 1, + c_read_depth => 32, + c_has_rd_ack => 0, + c_write_depth => 32, + c_ports_differ => 0, + c_memory_type => 0, + c_write_data_width => 18, + c_has_rd_err => 0); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x32 + port map ( + clk => clk, + sinit => sinit, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty); +-- synopsys translate_on + +END xilinx_fifo_18x32_a; + diff --git a/xilinx/xilinx_fifo_18x32.xco b/xilinx/xilinx_fifo_18x32.xco new file mode 100644 index 0000000..bb3e5eb --- /dev/null +++ b/xilinx/xilinx_fifo_18x32.xco @@ -0,0 +1,41 @@ +# BEGIN Project Options +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = /d/jspc19/trb/ot_trb2/ise8 +SET speedgrade = -10 +SET simulationfiles = Behavioral +SET asysymbol = True +SET addpads = False +SET device = xc4vlx40 +SET implementationfiletype = Edif +SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = ff1148 +SET createndf = False +SET designentry = VHDL +SET devicefamily = virtex4 +SET formalverification = False +SET removerpms = False +# END Project Options +# BEGIN Select +SELECT Synchronous_FIFO family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET memory_type=Distributed_Memory +CSET write_acknowledge_flag=false +CSET data_width=18 +CSET write_error_flag=false +CSET read_acknowledge_sense=Active_Low +CSET data_count_width=1 +CSET fifo_depth=32 +CSET component_name=xilinx_fifo_18x32 +CSET data_count=false +CSET read_acknowledge_flag=false +CSET read_error_sense=Active_Low +CSET read_error_flag=false +CSET write_acknowledge_sense=Active_Low +CSET write_error_sense=Active_Low +# END Parameters +GENERATE + diff --git a/xilinx/xilinx_fifo_18x64.vhd b/xilinx/xilinx_fifo_18x64.vhd new file mode 100644 index 0000000..905c353 --- /dev/null +++ b/xilinx/xilinx_fifo_18x64.vhd @@ -0,0 +1,105 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_18x64.vhd when simulating +-- the core, xilinx_fifo_18x64. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_18x64 IS + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +END xilinx_fifo_18x64; + +ARCHITECTURE xilinx_fifo_18x64_a OF xilinx_fifo_18x64 IS +-- synopsys translate_off +component wrapped_xilinx_fifo_18x64 + port ( + clk: IN std_logic; + sinit: IN std_logic; + din: IN std_logic_VECTOR(17 downto 0); + wr_en: IN std_logic; + rd_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + full: OUT std_logic; + empty: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_18x64 use entity XilinxCoreLib.sync_fifo_v5_0(behavioral) + generic map( + c_read_data_width => 18, + c_has_wr_ack => 0, + c_dcount_width => 1, + c_has_wr_err => 0, + c_wr_err_low => 1, + c_wr_ack_low => 1, + c_enable_rlocs => 0, + c_has_dcount => 0, + c_rd_err_low => 1, + c_rd_ack_low => 1, + c_read_depth => 64, + c_has_rd_ack => 0, + c_write_depth => 64, + c_ports_differ => 0, + c_memory_type => 0, + c_write_data_width => 18, + c_has_rd_err => 0); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_18x64 + port map ( + clk => clk, + sinit => sinit, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty); +-- synopsys translate_on + +END xilinx_fifo_18x64_a; + diff --git a/xilinx/xilinx_fifo_18x64.xco b/xilinx/xilinx_fifo_18x64.xco new file mode 100644 index 0000000..9b17203 --- /dev/null +++ b/xilinx/xilinx_fifo_18x64.xco @@ -0,0 +1,41 @@ +# BEGIN Project Options +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = /d/jspc19/trb/ot_trb2/ise8 +SET speedgrade = -10 +SET simulationfiles = Behavioral +SET asysymbol = True +SET addpads = False +SET device = xc4vlx40 +SET implementationfiletype = Edif +SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = ff1148 +SET createndf = False +SET designentry = VHDL +SET devicefamily = virtex4 +SET formalverification = False +SET removerpms = False +# END Project Options +# BEGIN Select +SELECT Synchronous_FIFO family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET memory_type=Distributed_Memory +CSET write_acknowledge_flag=false +CSET data_width=18 +CSET write_error_flag=false +CSET read_acknowledge_sense=Active_Low +CSET data_count_width=1 +CSET fifo_depth=64 +CSET component_name=xilinx_fifo_18x64 +CSET data_count=false +CSET read_acknowledge_flag=false +CSET read_error_sense=Active_Low +CSET read_error_flag=false +CSET write_acknowledge_sense=Active_Low +CSET write_error_sense=Active_Low +# END Parameters +GENERATE +