From: hadeshyp Date: Tue, 17 Aug 2010 09:18:00 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=bf82b2872d3d73d781f48b8d2637fe4d60f3d629;p=daqdocu.git *** empty log message *** --- diff --git a/daqstartup.tex b/daqstartup.tex index 8821200..a3a9d80 100755 --- a/daqstartup.tex +++ b/daqstartup.tex @@ -32,18 +32,18 @@ Despite these common rules the structure of each type of file will be different \subsection{Script files} All tasks that have to be done during startup are listed in the \filename{startup.script}. This script is interpreted by the main startup script written in Perl. the available commands are: \begin{description} - \item[\cmdname{trbcmd \$command}] The \$command will be passed directly to trbcmd. \cmdname{-f \$filename} can be used to load a file with commands. - \item[\cmdname{daqop \$command}] The \$command will be passed directly to daqop. - \item[\cmdname{load\_register register\_*.db}] Loads registers with values as described in \ref{daqregisters}. - \item[\cmdname{set\_addresses serials\_*.db addresses\_*.db}] Sets the addresses of boards according to the two database files as described in \ref{daqserials}. - \item[\cmdname{read\_trb\_db trn.db}] Read the configuration file containing all subsystems and corresponding TRBs. - \item[\cmdname{read\_eb\_conf ../evtbuild/eb.conf}] Read the configuration file of the event builder. - \item[\cmdname{exec\_script\{system\} script\_*.script}] Executes (forks) the given script file remotely on all TRBs of a given system as if the commands where given directly in the parent script file. - \item[\cmdname{exec\_cmd\{system\} \$command}] Executes (forks) the given command remotely on all TRBs of a given system. - \item[\cmdname{exec\_cmd\{local\} \$command}] Executes the given command localy without sleep. - \item[\cmdname{wait}] Wait for the forked children. - \item[\cmdname{check\_versions designfiles.db addresses\_*.db}] Checks if the loaded design files correspond to the given settings in the database. See \ref{daqdesignfiles}. - \item[\cmdname{load\_fpgas designfiles.db addresses\_*.db}] Loads the designs described in designfiles.db to the boards listed in the address database. + \item[\cmdname{trbcmd \$command}]~\\ The \$command will be passed directly to trbcmd. \cmdname{-f \$filename} can be used to load a file with commands. + \item[\cmdname{daqop \$command}]~\\ The \$command will be passed directly to daqop. + \item[\cmdname{load\_register register\_*.db}]~\\ Loads registers with values as described in \ref{daqregisters}. + \item[\cmdname{set\_addresses serials\_*.db addresses\_*.db}]~\\ Sets the addresses of boards according to the two database files as described in \ref{daqserials}. + \item[\cmdname{read\_trb\_db trn.db}]~\\ Read the configuration file containing all subsystems and corresponding TRBs. + \item[\cmdname{read\_eb\_conf ../evtbuild/eb.conf}]~\\ Read the configuration file of the event builder. + \item[\cmdname{exec\_script\{system\} script\_*.script}]~\\ Executes (forks) the given script file remotely on all TRBs of a given system as if the commands where given directly in the parent script file. + \item[\cmdname{exec\_cmd\{system\} \$command}]~\\ Executes (forks) the given command remotely on all TRBs of a given system. + \item[\cmdname{exec\_cmd\{local\} \$command}]~\\ Executes the given command localy without sleep. + \item[\cmdname{wait}]~\\ Wait for the forked children. + \item[\cmdname{check\_versions designfiles.db addresses\_*.db}]~\\ Checks if the loaded design files correspond to the given settings in the database. See \ref{daqdesignfiles}. + \item[\cmdname{load\_fpgas designfiles.db addresses\_*.db}]~\\ Loads the designs described in designfiles.db to the boards listed in the address database. \end{description} In the scriptfile conditional expressions can be used. For this, \cmdname{!ifdef \$name} and \cmdname{!ifndef \$name} are available. The part of code following such a statement will be skipped until the closing \cmdname{!endif} statement. The identifiers \cmdname{\$name} are given to the main script using the option \cmdname{-m} (See the code excerpt below for an example. Here different thresholds are selected using \cmdname{-m thresh\_experimental}). diff --git a/hubs.tex b/hubs.tex index 2aa35f9..9fc50f1 100755 --- a/hubs.tex +++ b/hubs.tex @@ -30,24 +30,25 @@ \item[0x88 - 0x8B: Timeouts $\dagger$] One register for each TrbNet channel. Each bit gives the status of one port: 1 if there was a timeout on this port, 0 otherwise. These registers are cleared after being read. If a bit in these registers is set, it also causes the corresponding link LED to flash (approx. 2 Hz, 25\% off). \item[0x8C - 0x8F: Waiting for ACK] One register for each TrbNet channel. Each bit gives the status of one port: 1 if data transmission on this port is stopped because the receiver did not acknowledge previous EOB words, 0 otherwise. \item[0x90: Link error status] One bit for each port. 0 if normal operation / inactive, 1 in cave of error (e.g. code violation). - \item[0xA0 - 0xA3: Error-/Status-Bits $\dagger$] One register for each TrbNet channel. Each register is the last Error-/Status-Bits, combined from all ports. + \item[0xA0 -- 0xA3: Error-/Status-Bits $\dagger$] One register for each TrbNet channel. Each register is the last Error-/Status-Bits, combined from all ports. \item[0xA4: Slow Control Error $\dagger$] One bit for each port. 1 if either one of the Errorbits 1,3,6 on the slow control channel have been set before. This register is cleared after being read. \item[0xA5: Endpoint reached] One bit for each port. 1 if this port returned the ``Endpoint reached'' bit in the status word set in the last slow control access, 0 otherwise. This information can be used to track a single board in the network: First a read access using the network address of the selected board has to be done. Immediately afterward this register can be read. To secure this non-atomic operation, the register is only updated if the board also return the ``don't understand' bit, e.g. after a read memory access to register 0. \item[0xA6: Link packet timeout $\dagger$] One bit for each port, 1 if there was a timeout while receiving a full packet of data (i.e. only 1 to 4 words of a packet have been received within the given time limit). Register is reset when read. - \item[0x4000 - 0x400F: IPU Packet counter] One register for each port. Each register is a 32 bit counter of the packets (with 64bit payload each) received on the IPU channel on this port. A write to 0x4000 resets all counters. - \item[0x4010 - 0x401F: Slow Control Packet counter] One register for each port. Each register is a 32 bit counter of the packets (with 64bit payload each) received on the slow control channel on this port. A write to 0x4010 resets all counters. - \item[0x4020 - 0x402F: Error Bits $\dagger$] One register for each port. Contents are part of the last Error-/Status-Bits received on this port: + \item[0x4000 -- 0x400F: IPU Packet counter] One register for each port. Each register is a 32 bit counter of the packets (with 64bit payload each) received on the IPU channel on this port. A write to 0x4000 resets all counters. + \item[0x4010 -- 0x401F: Slow Control Packet counter] One register for each port. Each register is a 32 bit counter of the packets (with 64bit payload each) received on the slow control channel on this port. A write to 0x4010 resets all counters. + \item[0x4020 -- 0x402F: Error Bits $\dagger$] One register for each port. Contents are part of the last Error-/Status-Bits received on this port: \begin{itemize} - \item Bit 0 - 7 of each register: Bit 0 - 7 of Errorbits on LVL1 channel - \item Bit 8 - 15: Errorbits 16 - 23 on LVL1 channel - \item Bit 16 - 23: Errorbits 0 - 7 on IPU channel - \item Bit 24 - 31: Errorbits 16 - 23 on IPU channel + \item Bit 0 -- 7 of each register: Bit 0 - 7 of Errorbits on LVL1 channel + \item Bit 8 -- 15: Errorbits 16 - 23 on LVL1 channel + \item Bit 16 -- 23: Errorbits 0 - 7 on IPU channel + \item Bit 24 -- 31: Errorbits 16 - 23 on IPU channel \end{itemize} - \item[0x4030 - 0x403F: Inclusive busy counter]One register for each port counting the time the port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4030 clears all counters. - \item[0x4040 - 0x404F: Exclusive busy counter] One register for each port counting the time this port and only this port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4040 clears all counters. + \item[0x4030 -- 0x403F: Inclusive busy counter]One register for each port counting the time the port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4030 clears all counters. + \item[0x4040 -- 0x404F: Exclusive busy counter] One register for each port counting the time this port and only this port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4040 clears all counters. \item[0x4050: Global Time] Here, the global time also accessible in register 0x50 is readable. This allows to do a simultaneous readout with the busy counter registers to get exact time information. -\item[0x4060: LSM Status] Status of the media interfaces. Bit 2--0: med\_error\_out, Bit 7--4: Link state machine status bits. +\item[0x4060 -- 0x406F: LSM Status] Status of the media interfaces. Bit 2--0: med\_error\_out, Bit 7--4: Link state machine status bits, Bit 23 -- 16: Number of retransmit requests received by media interface, Bit 31 -- 24: Number of retransmit requests sent by media interface. + \end{description} $\dagger$: Register is not reset during network reset diff --git a/installation_ethernet.tex b/installation_ethernet.tex index c265ac7..355af5d 100644 --- a/installation_ethernet.tex +++ b/installation_ethernet.tex @@ -1 +1,4 @@ -t.b.d. \ No newline at end of file +\begin{center} + \LTXtable{\textwidth}{installation_ethernet_table} +\end{center} + diff --git a/lvl1trigger.tex b/lvl1trigger.tex index 64ee575..5c7019c 100755 --- a/lvl1trigger.tex +++ b/lvl1trigger.tex @@ -44,7 +44,7 @@ If deleting the data is not possible any more, the TTL trigger is ignored by the \item[Case 4: LVL1 trigger without timing trigger] In case a LVL1 timing trigger is received without a preceeding timing trigger, the trigger handler invalidates this trigger with a strobe on \portname{invalid\_trg}. Even though this is not a valid trigger, the user has to acknowledge by setting \portname{trg\_release} in the normal manner. This is because the FEE could already have been triggered and the logic needs some time to recover from this situation. See timing diagram \ref{fig:timingtriggercase4} for details. \item[Case 5: multiple timing triggers before LVl1 trigger] In case there is more than one timing trigger, only the first one is validated by a short pulse on \portname{timing\_trg\_valid}. When the second trigger arrives, the \portname{multiple\_trigger} signal goes high until the trigger has been released by the user. See timing diagram \ref{fig:timingtriggercase5} for details. \item[Case 6: Too short timing triggers (spikes)] A short pule (currently below 40~ns) on the timing trigger input will not cause any valid- or invalid signal from the trigger handler. It only sets the \portname{spike\_detected} output to inform the attached logic about this event. - \item[Case 7: Too long delay between timing trigger and LVL1] During normal operation, the LVL1 information should reach the endpoint within 5~us after the timing trigger. In case this time is much bigger it is very likely that the timing trigger signal that has been seen was not the real one but noise. Therefore, the trigger handler raises the \portname{timeout\_detected} signal and sets the corresponding error information on the LVL1 channel. + \item[Case 7: Too long delay after timing trigger] During normal operation, the LVL1 information should reach the endpoint within 5~us after the timing trigger. In case this time is much bigger it is very likely that the timing trigger signal that has been seen was not the real one but noise. Therefore, the trigger handler raises the \portname{timeout\_detected} signal and sets the corresponding error information on the LVL1 channel. \end{description} diff --git a/main.tex b/main.tex index 6f2f6fe..4849b30 100755 --- a/main.tex +++ b/main.tex @@ -1,5 +1,5 @@ -\documentclass[11pt,a4paper]{scrartcl} %twoside +\documentclass[11pt,a4paper,twoside]{scrartcl} %twoside %Einstellungen der Seitenr�nder \usepackage[left=4.0cm,right=2.5cm,top=2.5cm,bottom=2.5cm,includeheadfoot]{geometry} diff --git a/mdc.tex b/mdc.tex index ba32379..09e3498 100755 --- a/mdc.tex +++ b/mdc.tex @@ -270,7 +270,7 @@ The ADC monitoring most voltages on each OEP can be accessed using register addr \end{description} \item[0x9002: \filename{Data\_Handler} status register]~ \begin{description} - \item[Bit 3 -- 0] State machine status \\ 0: idle, 1: send data, 2: send long data, 3: send dummy, 4: finish, 5: write debug word, 6: prepare status information, 7: send status information + \item[Bit 3 -- 0] State machine status \\ 0: idle, 1: send data, 2: send long data, 3: send dummy, 4: finish, 5: write debug word, 6:status words set address, 7: status words calculate, 8: status words write, 9: status finished \item[Bit 4] Start Readout \item[Bit 5] Finished Readout \item[Bit 6] Data Write Enable diff --git a/mediainterface.tex b/mediainterface.tex index 61da854..0773445 100644 --- a/mediainterface.tex +++ b/mediainterface.tex @@ -2,7 +2,7 @@ \begin{table}[hbtp] \begin{center} -\begin{tabularx}{\textwidth}{|l|l|X|} +\begin{tabularx}{\textwidth}{|c|l|X|} \hline \textbf{Bit} & \textbf{Name} & \textbf{Description} \\ \hline\hline @@ -24,3 +24,22 @@ \end{center} \end{table} +\begin{table}[hbtp] +\begin{center} +\begin{tabularx}{\textwidth}{|c|l|X|} +\hline +\textbf{Bit} & \textbf{Name} & \textbf{Description} \\ +\hline\hline +15 & Send Reset & ``Reset network'' sequence has to be sent \\ +14 & Disable & Switch off media interface \\ +13 & Reset Interface & Reset Media Interface \\ +12 -- 9 & reserved & \\ +8 & Enable Error Correction & Enable error correction on links, e.g. retransmit after a bit error on optical links\\ +7 -- 0 & reserved & \\ + +\hline +\end{tabularx} +\caption{16bit Control Register of Media Interfaces} +\label{MediaInterfaceControl} +\end{center} +\end{table} diff --git a/networkaddresses.tex b/networkaddresses.tex index fec62c0..ae33bdc 100755 --- a/networkaddresses.tex +++ b/networkaddresses.tex @@ -8,11 +8,13 @@ On boards with two or more FPGAs each FPGA gets its own address. The FPGA provid \begin{table}[hb] \begin{center} -\begin{tabularx}{\textwidth}{l|l|X} +\begin{tabularx}{\textwidth}{|l|l|X|} +\hline \textbf{Address(es)} & \textbf{Board(s)} & \textbf{Description} \\ +\hline\hline 0000 - 00FF & CTS & \\ 0100 - 01FF & Slow Control & \\ -0200 - 02FF & Other CTS-like boards \\ +0200 - 02FF & Other CTS-like boards & \\ 1000 - 17FF & MDC Concentrator & 2nd digit: inner(0) / outer(1) MDC; 3rd digit: sector (0-5), 4th digit FPGA (0-4) \\ 2000 - 2FFF & MDC OEP & 2nd digit: MDC layer (0-3); 3rd digit: sector (0-5); 4th digit MBO (0-F) \\ 3000 - 31FF & RICH ADCM & 3rd digit: sector (0-5); 4th digit: segment (0-4) \\ @@ -32,8 +34,9 @@ On boards with two or more FPGAs each FPGA gets its own address. The FPGA provid 8700 - 87FF & Forward Wall Hub & \\ 8800 - 88FF & Start/Veto/CTS Hub & \\ F000 - FDFF & Test Setups & \\ -FE00 - FEFF & Reserved & Reserved for extension of broadcast addresses \\ -FF00 - FFFF & Broadcasts & +FE00 - FEFF & Special Broadcast & Special broadcast addresses to access groups of boards. See table \ref{HardwareInformation} for details. \\ +FF00 - FFFF & Broadcasts & \\ +\hline \end{tabularx} \caption{Network Addresses} \label{networkaddresses} diff --git a/slowcontrol.tex b/slowcontrol.tex index 7ca5d94..05e75e8 100755 --- a/slowcontrol.tex +++ b/slowcontrol.tex @@ -329,9 +329,9 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}. \hline \textbf{Bits} & \textbf{Description} \\ \hline\hline -31 -- 24 & Number of retransmit requests in media interface (written by media interface, connected in top level entity)\\ -23 -- 9 & reserved \\ -8 & link error, e.g. code violation received (written by endpoint)\\ +31 -- 24 & Number of retransmit requests sent by media interface (written by endpoint-hades-full)\\ +23 -- 16 & Number of retransmit requests received by media interface (written by endpoint-hades-full)\\ +%15 -- 8 & Number of transmission restarts received by media interface (written by endpoint-hades-full)\\ 7 -- 4 & reserved \\ 3 -- 0 & counter for received network resets (written by endpoint) \\ \hline @@ -381,7 +381,8 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}. 30 & enable debug \\ 29 & invert timing trigger \\ 28 & Single Event Upset Detection enable \\ -27 -- 24 & reserved \\ +27 & Enable error correction in media interface \\ +26 -- 24 & reserved \\ 23 -- 20 & data format \\ 19 -- 16 & reserved \\ 15 -- 0 & enable frontends \\ @@ -402,44 +403,44 @@ table~\ref{HardwareInformation} \begin{table}[htbp] \begin{center} -\begin{tabularx}{\textwidth}{|c|X|} +\begin{tabularx}{\textwidth}{|c|X|c|} \hline -\textbf{Value (hex)} & \textbf{Description} \\ +\textbf{Value (hex)} & \textbf{Description} & \textbf{Special Broadcast}\\ \hline \hline -1110 & MDC AddOn version 1 FPGA 1 \\ -1120 & MDC AddOn version 1 FPGA 2 \\ -1130 & MDC AddOn version 1 FPGA 3 \\ -1210 & MDC Hub version 2 FPGA 1 -- 4\\ -1250 & MDC Hub version 2 FPGA 5 \\ -2100 & MDC OEP version 1 \\ -2200 & MDC OEP version 2 \\ -2300 & MDC OEP version 3 \\ -3100 & RICH ADCM version 1 \\ -3200 & RICH ADCM version 2 \\ -3300 & RICH ADCM version 3 \\ -4100 & Shower AddOn version 1 \\ -4210 & Shower AddOn version 2 FPGA 1 \\ -4220 & Shower AddOn version 2 FPGA 2 \\ -4230 & Shower AddOn version 2 FPGA 3 \\ -5000 & Old CTS \\ -5100 & CTS AddOn FPGA 1 \\ -5200 & CTS AddOn FPGA 2 \\ -6100 & Hub AddOn version 1 \\ -6210 & Hub AddOn version 2 FPGA 1 \\ -6220 & Hub AddOn version 2 FPGA 2 without GbE\\ -6221 & Hub AddOn version 2 FPGA 2 with GbE\\ -7300 & PEXOR version 3 \\ -8000 & TRB using TDC readout (purpose not defined)\\ -8100 & TOF TRB \\ -8200 & Start/Veto TRB \\ -8300 & RPC TRB \\ -8800 & Other TRB \\ +1110 & MDC AddOn version 1 FPGA 1 & FE01 \\ +1120 & MDC AddOn version 1 FPGA 2 & FE02 \\ +1130 & MDC AddOn version 1 FPGA 3 & FE03 \\ +1210 & MDC Hub version 2 FPGA 1 -- 4 & FE11\\ +1250 & MDC Hub version 2 FPGA 5 & FE15 \\ +2100 & MDC OEP version 1 & -- \\ +2200 & MDC OEP version 2 & -- \\ +2300 & MDC OEP version 3 & -- \\ +3100 & RICH ADCM version 1 & -- \\ +3200 & RICH ADCM version 2 & -- \\ +3300 & RICH ADCM version 3 & -- \\ +4100 & Shower AddOn version 1 & -- \\ +4210 & Shower AddOn version 2 FPGA 1 & FE21 \\ +4220 & Shower AddOn version 2 FPGA 2 & FE22 \\ +4230 & Shower AddOn version 2 FPGA 3 & FE23 \\ +5000 & Old CTS & -- \\ +5100 & CTS AddOn FPGA 1 & -- \\ +5200 & CTS AddOn FPGA 2 & -- \\ +6100 & Hub AddOn version 1 & -- \\ +6210 & Hub AddOn version 2 FPGA 1 & FE31 \\ +6220 & Hub AddOn version 2 FPGA 2 without GbE & FE32 \\ +6221 & Hub AddOn version 2 FPGA 2 with GbE & FE33 \\ +7300 & PEXOR version 3 & -- \\ +8000 & TRB using TDC readout (purpose not defined) & -- \\ +8100 & TOF TRB & -- \\ +8200 & Start/Veto TRB & -- \\ +8300 & RPC TRB & -- \\ +8800 & Other TRB & -- \\ \hline \end{tabularx} \caption{Upper 16 bit in register 0x42 marking the hardware the design is belonging to. The value can be set by a generic value (\genericname{Regio\_Hardware\_Version}) of the TrbNet endpoint. The -lower 16bit are not globally defined.} +lower 16bit are not globally defined. The special broadcast is explained in section \ref{networkaddresses}}. \label{HardwareInformation} \end{center} \end{table}