From: hadeshyp Date: Thu, 30 Jul 2009 12:24:04 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~412 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c032100397a0e6bdbc915e854ec99e6647bce57e;p=trbnet.git *** empty log message *** --- diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 37914a0..e92b273 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -201,64 +201,7 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is begin -<<<<<<< trb_net16_hub_base.vhd - component trb_net16_iobuf is - generic ( - IBUF_DEPTH : integer range 2 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; - IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT : out std_logic; - MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN : in std_logic; - MED_REPLY_DATAREADY_OUT : out std_logic; - MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN : in std_logic; - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_ERROR_IN : in std_logic_vector (2 downto 0); - -- Internal direction port - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_IN : in std_logic; - INT_INIT_DATAREADY_IN : in std_logic; - INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT : out std_logic; - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN : in std_logic; - INT_REPLY_DATAREADY_IN : in std_logic; - INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT : out std_logic; - -- Status and control port - STAT_GEN : out std_logic_vector (31 downto 0); - STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); - CTRL_GEN : in std_logic_vector (31 downto 0); - STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0); - STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0) - ); - end component; -======= + --------------------------------------------------------------------- --Generate various reset signals --------------------------------------------------------------------- @@ -268,7 +211,7 @@ begin reset_i <= RESET; end if; end process; ->>>>>>> 1.57 + gen_internal_reset : for i in 0 to MII_NUMBER-1 generate diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 810c21a..d074621 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -150,24 +150,26 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal waiting_for_DHDR_word : std_logic_vector(POINT_NUMBER-1 downto 0); signal next_waiting_for_DHDR_word : std_logic_vector(POINT_NUMBER-1 downto 0); - signal reply_adder_input : std_logic_vector(17*16-1 downto 0); - signal reply_adder_start : std_logic; - signal reply_adder_overflow : std_logic; - signal reply_adder_ready : std_logic; + signal reply_adder_input : std_logic_vector(17*16-1 downto 0); + signal reply_adder_start : std_logic; + signal reg_reply_adder_start : std_logic; + signal reply_adder_overflow : std_logic; + signal reply_adder_ready : std_logic; signal reply_adder_val_enable : std_logic_vector(17-1 downto 0); signal reply_adder_result : std_logic_vector(15 downto 0); signal next_reply_adder_start : std_logic; signal next_reply_compare_start : std_logic; - signal reply_compare_start : std_logic; - signal reply_compare_finished : std_logic; - signal reply_compare_result : std_logic_vector(17-1 downto 0); - signal reply_compare_flag : std_logic; - signal reply_compare_input : std_logic_vector(17-1 downto 0); + signal reply_compare_start : std_logic; + signal reg_reply_compare_start : std_logic; + signal reply_compare_finished : std_logic; + signal reply_compare_result : std_logic_vector(17-1 downto 0); + signal reply_compare_flag : std_logic; + signal reply_compare_input : std_logic_vector(17-1 downto 0); - signal last_dhdr_addr : std_logic_vector(2 downto 0); - signal last_dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0); - signal next_last_dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0); + signal dhdr_addr : std_logic_vector(2 downto 0); + signal dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0); + signal next_dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0); signal current_point_length : unsigned(15 downto 0); signal start_read_padding : std_logic_vector(POINT_NUMBER-1 downto 0); @@ -459,8 +461,8 @@ begin PROC_reading_signals : process(CLK) begin if rising_edge(CLK) then - reg_current_reply_reading_TRM(i) <= current_reply_reading_TRM(i); - reg_current_reply_reading_HDR(i) <= current_reply_reading_HDR(i); + reg_current_reply_reading_TRM(i) <= current_reply_reading_TRM(i); + reg_current_reply_reading_HDR(i) <= current_reply_reading_HDR(i); reg_current_reply_reading_DHDR(i) <= current_reply_reading_DHDR(i); end if; end process; @@ -506,14 +508,6 @@ begin ---------------------------------- gen_saving_dhdr : for i in 0 to POINT_NUMBER-1 generate hdrram_write_enable(i) <= (reg_current_reply_reading_HDR(i) or reg_current_reply_reading_DHDR(i)) and not reply_reading_H0(i); - --- (current_reply_reading_HDR(i) and --- (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i) or reply_reading_F3(i))) or --- (current_reply_reading_DHDR(i) and --- (reply_reading_F0(i) or reply_reading_F1(i) or reply_reading_F2(i) --- (REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH) and not REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+2)) --- )); - --read normal HDR_F0 to DHDR_F1 and DHDR_F2 without read='1' hdrram_address(i*3+1 downto i*3) <= REPLY_PACKET_NUM_IN((i)*c_NUM_WIDTH+1 downto i*c_NUM_WIDTH); hdrram_address(i*3+2) <= '1' when current_reply_reading_DHDR(i)='1' else '0'; @@ -527,15 +521,25 @@ begin wr1 => hdrram_write_enable(i), a1 => hdrram_address(i*3+2 downto i*3), din1 => REPLY_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - a2 => last_dhdr_addr, - dout2 => next_last_dhdr_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) + a2 => dhdr_addr, + dout2 => next_dhdr_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) ); end generate; - PROC_REG_DHDR_RAM_OUT : process(CLK) + + PROC_dhdr_data_reg : process(CLK) begin if rising_edge(CLK) then - last_dhdr_data <= next_last_dhdr_data; + dhdr_data <= next_dhdr_data; + if RESET = '1' then + reply_adder_start <= '0'; + reply_compare_start <= '0'; + else + reg_reply_adder_start <= next_reply_adder_start; + reg_reply_compare_start <= next_reply_compare_start; + reply_adder_start <= reg_reply_adder_start; + reply_compare_start <= reg_reply_compare_start; + end if; end if; end process; @@ -556,20 +560,10 @@ begin READY_OUT => reply_adder_ready ); - PROC_LED : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reply_adder_start <= '0'; - reply_compare_start <= '0'; - else - reply_adder_start <= next_reply_adder_start; - reply_compare_start <= next_reply_compare_start; - end if; - end if; - end process; + reply_adder_val_enable(POINT_NUMBER-1 downto 0) <= (not locking_point and real_activepoints); + reply_adder_val_enable(reply_adder_val_enable'left downto POINT_NUMBER) <= (others => '0'); - reply_adder_input(POINT_NUMBER*16-1 downto 0) <= last_dhdr_data; + reply_adder_input(POINT_NUMBER*16-1 downto 0) <= dhdr_data; gen_spare_bits : if POINT_NUMBER < 17 generate reply_adder_input(reply_adder_input'left downto POINT_NUMBER*16) <= (others => '0'); end generate; @@ -582,7 +576,7 @@ begin else gen_current_length : for i in 0 to POINT_NUMBER-1 loop if reply_arbiter_result(i) = '1' then - current_point_length <= unsigned(last_dhdr_data((i)*c_DATA_WIDTH+c_DATA_WIDTH-1 downto i*c_DATA_WIDTH)); + current_point_length <= unsigned(dhdr_data((i)*c_DATA_WIDTH+c_DATA_WIDTH-1 downto i*c_DATA_WIDTH)); end if; end loop; end if; @@ -627,25 +621,22 @@ begin process(RESET, send_reply_trm, REPLY_PACKET_NUM_IN, REPLY_DATAREADY_IN, REPLY_DATA_IN, start_read_padding, saved_reading_padding) begin - if RESET = '1' or send_reply_trm = '1' then - reading_padding <= (others => '0'); - else - for i in 0 to POINT_NUMBER-1 loop - if REPLY_DATAREADY_IN(i) = '1' and REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = c_H0 and REPLY_DATA_IN(i*16+2 downto i*16) = TYPE_TRM then - reading_padding(i) <= '0'; - elsif start_read_padding(i) = '1' then - reading_padding(i) <= '1'; - else - reading_padding(i) <= saved_reading_padding(i); - end if; - end loop; - end if; + for i in 0 to POINT_NUMBER-1 loop + if reply_reading_F0(i) = '1' and reg_current_reply_reading_TRM(i) = '1' then + --REPLY_DATAREADY_IN(i) = '1' and REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = c_H0 and REPLY_DATA_IN(i*16+2 downto i*16) = TYPE_TRM then + reading_padding(i) <= '0'; + elsif start_read_padding(i) = '1' then + reading_padding(i) <= '1'; + else + reading_padding(i) <= saved_reading_padding(i); + end if; + end loop; end process; gen_saved_padding : process (CLK) begin if rising_edge(CLK) then - if locked = '0' then + if RESET = '1' or send_reply_trm = '1' or locked = '0' then saved_reading_padding <= (others => '0'); else saved_reading_padding <= reading_padding; @@ -679,7 +670,8 @@ begin if RESET = '1' or send_reply_trm = '1' or locked = '0' then got_trm <= (others => '0'); else - got_trm <= got_trm or locking_point or (reply_reading_F3 and reg_current_reply_reading_TRM) or not real_activepoints or connection_timed_out; + got_trm <= got_trm or locking_point or (reply_reading_F3 and reg_current_reply_reading_TRM) + or not real_activepoints or connection_timed_out; end if; end if; end process; @@ -733,11 +725,7 @@ begin PROC_REG_COMB_DATAREADY : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then - last_comb_REPLY_POOL_DATAREADY <= '0'; - else - last_comb_REPLY_POOL_DATAREADY <= comb_REPLY_POOL_DATAREADY; - end if; + last_comb_REPLY_POOL_DATAREADY <= comb_REPLY_POOL_DATAREADY; end if; end process; @@ -758,7 +746,7 @@ begin CTRL => (others => '0') ); - reply_arbiter_reset <= RESET or not locked; + reply_arbiter_reset <= RESET or not locked; reply_arbiter_input <= REPLY_DATAREADY_IN and not current_reply_reading_TRM and current_reply_reading_DHDR and not saved_reading_padding; -- reply_arbiter_CLK_EN <= not next_point_lock; REPLY_MUX_reading <= reply_arbiter_result; @@ -793,7 +781,7 @@ begin end generate; ---Muxed data is ready, when the selected port has data, and this is neither padding, H0 nor termination. +--Muxed data is ready, when the selected port has data, and this is neither padding, H0, padding nor termination. -- comb_REPLY_muxed_DATAREADY <= or_all(reply_arbiter_result and REPLY_DATAREADY_IN and not reg_current_reply_reading_trm and not reply_reading_H0 and not saved_reading_padding) @@ -810,26 +798,26 @@ begin variable tmp_code, tmp_number, tmp_pack : std_logic; begin if rising_edge(CLK) then - reply_compare_finished <= '0'; + reply_compare_finished <= reply_compare_finished and not REPLY_POOL_next_read; tmp_code := '0'; tmp_pack := '1'; tmp_number := '0'; if reply_compare_start = '1' then - if last_dhdr_addr = "100" then --upper part + if dhdr_addr = "100" then --upper part for i in 0 to POINT_NUMBER-1 loop - if last_dhdr_data(i*16+12) = '0' and reply_adder_val_enable(i) = '1' then + if dhdr_data(i*16+12) = '0' and reply_adder_val_enable(i) = '1' then tmp_pack := '0'; end if; - if last_dhdr_data(i*16+7 downto i*16) /= evt_random_code and reply_adder_val_enable(i) = '1' then + if dhdr_data(i*16+7 downto i*16) /= evt_random_code and reply_adder_val_enable(i) = '1' then tmp_code := '1'; end if; end loop; enable_packing <= tmp_pack; evt_code_mismatch <= tmp_code; reply_compare_finished <= '1'; - elsif last_dhdr_addr = "101" then + elsif dhdr_addr = "101" then for i in 0 to POINT_NUMBER-1 loop - if last_dhdr_data(i*16+15 downto i*16) /= evt_number and reply_adder_val_enable(i) = '1' then + if dhdr_data(i*16+15 downto i*16) /= evt_number and reply_adder_val_enable(i) = '1' then tmp_number := '1'; end if; end loop; @@ -866,11 +854,9 @@ begin comb_REPLY_POOL_DATA <= (others => '0'); next_waiting_for_DHDR_word <= waiting_for_DHDR_word and real_activepoints and not (reg_current_reply_reading_DHDR and reply_reading_F2); - last_dhdr_addr <= "000"; + dhdr_addr <= "000"; next_current_waiting_for_reply <= current_waiting_for_reply and not reg_current_reply_reading_HDR and real_activepoints; next_reply_adder_start <= '0'; - reply_adder_val_enable(POINT_NUMBER-1 downto 0) <= (not locking_point and real_activepoints); - reply_adder_val_enable(reply_adder_val_enable'left downto POINT_NUMBER) <= (others => '0'); reply_arbiter_enable <= '0'; next_reply_compare_start <= '0'; reply_arbiter_CLK_EN <= '0'; @@ -892,7 +878,7 @@ begin end if; when WAIT_FOR_HDR_DATA => --start writing HDR when first reply is received, stop waiting for length - last_dhdr_addr <= "010"; + dhdr_addr <= "010"; case packet_counter is when c_H0 => comb_REPLY_POOL_DATA <= (others => '0'); @@ -914,53 +900,50 @@ begin end case; when GEN_LENGTH => --now, all HDR are stored, calc sum of HDR lengths - last_dhdr_addr <= "010"; - comb_REPLY_POOL_DATAREADY <= '0'; + dhdr_addr <= "010"; next_reply_adder_final_result <= std_logic_vector(unsigned(reply_adder_result) - number_of_replies + 2); - if last_reply_adder_ready = '1' then - comb_REPLY_POOL_DATA <= reply_adder_final_result; - comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; - end if; - if packet_counter = c_F3 then - last_dhdr_addr <= "100"; - comb_REPLY_POOL_DATA <= "0000" & evt_seqnr & evt_dtype; - comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; - if REPLY_POOL_next_read = '1' then - next_state <= CHECK_DHDR; - end if; - end if; + comb_REPLY_POOL_DATAREADY <= '0'; + + case packet_counter is + when c_F2 => + comb_REPLY_POOL_DATA <= reply_adder_final_result; + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read and last_reply_adder_ready; + when c_F3 => + dhdr_addr <= "100"; + comb_REPLY_POOL_DATA <= "0000" & evt_seqnr & evt_dtype; + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; + if REPLY_POOL_next_read = '1' then + next_state <= CHECK_DHDR; + end if; + end case; when CHECK_DHDR => comb_REPLY_POOL_DATAREADY <= '0'; case packet_counter is when c_H0 => - last_dhdr_addr <= "100"; - if got_all_DHDR = '1' then - comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; - end if; + comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read and got_all_DHDR; comb_REPLY_POOL_DATA(2 downto 0) <= TYPE_DAT; comb_REPLY_POOL_DATA(c_DATA_WIDTH-1 downto 3) <= (others => '0'); + dhdr_addr <= "100"; + next_reply_compare_start <= REPLY_POOL_next_read and got_all_DHDR; when c_F0 => - last_dhdr_addr <= "100"; - next_reply_compare_start <= '1'; + dhdr_addr <= "100"; comb_REPLY_POOL_DATA <= "0001" & evt_dtype & evt_random_code; if reply_compare_finished = '1' then + next_reply_compare_start <= REPLY_POOL_next_read; comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; - next_reply_compare_start <= '0'; - last_dhdr_addr <= "101"; + dhdr_addr <= "101"; end if; when c_F1 => - last_dhdr_addr <= "101"; - next_reply_compare_start <= '1'; + dhdr_addr <= "101"; comb_REPLY_POOL_DATA <= evt_number; if reply_compare_finished = '1' then - next_reply_compare_start <= '0'; comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read; - last_dhdr_addr <= "110"; + next_reply_adder_start <= REPLY_POOL_next_read; + dhdr_addr <= "110"; end if; when c_F2 => - next_reply_adder_start <= '1'; - last_dhdr_addr <= "110"; + dhdr_addr <= "110"; next_reply_adder_final_result <= std_logic_vector(unsigned(reply_adder_result) + number_of_replies); if last_reply_adder_ready = '1' then comb_REPLY_POOL_DATA <= reply_adder_final_result; @@ -972,16 +955,15 @@ begin if REPLY_POOL_next_read = '1' then next_state <= SENDING_DATA; reply_arbiter_CLK_EN <= '1'; - reply_arbiter_CLK_EN <= '1'; reply_arbiter_enable <= '1'; - last_dhdr_addr <= "110"; + dhdr_addr <= "110"; reply_data_counter_reset <= '1'; end if; end case; when SENDING_DATA => reply_arbiter_enable <= '1'; - last_dhdr_addr <= "110"; --length + dhdr_addr <= "110"; --length if packet_counter = c_H0 then -- and not (comb_REPLY_muxed_PACKET_NUM = c_H0 and comb_REPLY_muxed_DATA(2 downto 0) = TYPE_TRM) @@ -1086,7 +1068,7 @@ begin number_of_replies <= to_unsigned(count_ones(expected_replies),5); expected_replies <= real_activepoints and not locking_point; reply_adder_final_result <= next_reply_adder_final_result; - last_reply_adder_ready <= reply_adder_ready; + last_reply_adder_ready <= reply_adder_ready or (last_reply_adder_ready and not REPLY_POOL_next_read); end if; end if; end process; @@ -1157,6 +1139,6 @@ begin STAT_FSM(8) <= reply_adder_start; STAT_FSM(9) <= reply_compare_start; STAT_FSM(12 downto 10)<= packet_counter; - STAT_FSM(15 downto 13)<= last_dhdr_addr; + STAT_FSM(15 downto 13)<= dhdr_addr; end architecture; diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index f07d73e..43531b6 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -48,10 +48,10 @@ entity trb_net16_ibuf is end entity; architecture trb_net16_ibuf_arch of trb_net16_ibuf is --- -- Placer Directives --- attribute HGROUP : string; --- -- for whole architecture --- attribute HGROUP of trb_net16_ibuf_arch : architecture is "IBUF_group"; + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of trb_net16_ibuf_arch : architecture is "IBUF_group"; signal fifo_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal fifo_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index a1a8764..ba7e64a 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -107,9 +107,9 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is signal sbuf_status : std_logic; -- Placer Directives - attribute HGROUP : string; + attribute HGROUP : string; -- for whole architecture - attribute HGROUP of trb_net16_io_multiplexer_arch : architecture is "MUX_group"; + attribute HGROUP of trb_net16_io_multiplexer_arch : architecture is "MUX_group"; begin ------------------------------------------------------------------------------- diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index 136f1f2..81760a3 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -76,10 +76,10 @@ entity trb_net16_iobuf is end entity; architecture trb_net16_iobuf_arch of trb_net16_iobuf is - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of trb_net16_iobuf_arch : architecture is "IOBUF_group"; +-- -- Placer Directives +-- attribute HGROUP : string; +-- -- for whole architecture +-- attribute HGROUP of trb_net16_iobuf_arch : architecture is "IOBUF_group"; @@ -98,7 +98,7 @@ begin MED_READ_OUT <= ibuf_read_out; -- MED_REPLY_READ_OUT <= ibuf_read_out; - IBUF : trb_net16_ibuf + THE_IBUF : trb_net16_ibuf generic map ( DEPTH => IBUF_DEPTH, USE_VENDOR_CORES => USE_VENDOR_CORES, @@ -132,7 +132,7 @@ begin end generate; GEN_TERM_IBUF: if IBUF_DEPTH=0 generate - IBUF : trb_net16_term_ibuf + THE_IBUF : trb_net16_term_ibuf generic map( SBUF_VERSION => SBUF_VERSION, SECURE_MODE => IBUF_SECURE_MODE diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index c7406b0..d19dc09 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -41,6 +41,11 @@ end entity; architecture trb_net16_obuf_arch of trb_net16_obuf is + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of trb_net16_obuf_arch : architecture is "OBUF_group"; + component trb_net16_sbuf is generic ( VERSION : integer := 0 diff --git a/trb_net16_obuf_nodata.vhd b/trb_net16_obuf_nodata.vhd index 0ef217f..10f6c5d 100644 --- a/trb_net16_obuf_nodata.vhd +++ b/trb_net16_obuf_nodata.vhd @@ -39,6 +39,13 @@ architecture trb_net16_obuf_nodata_arch of trb_net16_obuf_nodata is attribute syn_keep : boolean; attribute syn_keep of buf_MED_DATAREADY_OUT : signal is true; + attribute syn_sharing : string; + attribute syn_sharing of trb_net16_obuf_nodata_arch : architecture is "off"; + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of trb_net16_obuf_nodata_arch : architecture is "OBUF_group"; begin SEND_BUFFER_SIZE_IN <= CTRL_BUFFER(3 downto 0); diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 823549e..98d5e1f 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -399,7 +399,19 @@ package trb_net_components is - + component fifo_dualclock_width_16_reg is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic); + end component; component trb_net16_ibuf is