From: Maps Date: Tue, 28 Feb 2023 12:30:57 +0000 (+0100) Subject: new config files for sensors and to disable test mode X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c05e79cfe5a4225ffbef570e190d36d2b8e8c21f;p=mimosis_chain.git new config files for sensors and to disable test mode --- diff --git a/.gitignore b/.gitignore index 6a0aad4..d203a76 100644 --- a/.gitignore +++ b/.gitignore @@ -9,3 +9,8 @@ scratch git data/ +scripts/dac_scan/img/ +scripts/dac_scan/*.csv +*.d +*.so +*.pcm diff --git a/scripts/conf/CONF_M2.pl b/scripts/conf/CONF_M2.pl new file mode 100644 index 0000000..64ec5fb --- /dev/null +++ b/scripts/conf/CONF_M2.pl @@ -0,0 +1,136 @@ +#read files like my @config = do "CONF_allregisters.pl"; + + #General Control + [0x0020, ], #RUNMODE -> table 8 + [0x0021, ], #TRIMDAC -> table 9 + [0x0022, ], #INJCURR -> table 10 + [0x0023, ], #INJVOLT1 -> table 11 + [0x0024, ], #INJVOLT2 -> table 12 + [0x0025, ], #MONCURR -> table 13 + [0x0026, ], #MONVOLT -> table 14 + [0x0027, ], #CLKGEN1 -> table 15 + [0x0028, ], #CLKGEN2 -> table 16 + [0x0029, ], #PLL -> table 17 + [0x002a, ], #PLLLOCK -> table 18 + [0x002b, ], #MONTEMP -> table 19 + [0x002c, ], #SLVSTX -> table 20 + [0x002d, ], #SLVSRX -> table 21 + [0x002e, ], #OUTPUT -> table 22 + [0x002f, ], #MONPWR -> table 23 + + #DACs + [0x0040, ], #IBIAS 0 - 80 nA , 312 pA Pixel current + [0x0041, ], #ITHR 0 - 2.5 nA , 9.8 pA Pixel current + [0x0042, ], #IDB 0 - 40 nA , 157 pA Pixel current + [0x0043, ], #VRESET 0.37 - 1.79 V , 6 mV Pixel input amplifier reset voltage + [0x0044, ], #VPL 0.37 - 1.79 V , 6 mV Pixel voltage for charge injection (low value) + [0x0045, ], #VPH 0.37 - 1.79 V , 6 mV Pixel voltage for charge injection (high + [0x0046, ], #VPH_FINE 0 - 256 mV , 1 mV value) VPH+VPH_FINE + [0x0047, 66 ], #VCASP 0 - 1.54 V , 6 mV Pixel voltage + [0x0048, 169 ], #VCASNA 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix A + [0x0049, 183 ], #VCASNB 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix B + [0x004a, 233 ], #VCASNC 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix C + [0x004b, 182 ], #VCASND 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix D + [0x004c, 181 ], #VCASN2 0 - 1.54 V , 6 mV Pixel voltage + [0x004d, ], #VCLIP 0 - 1.54 V , 6 mV Pixel clipping amplifier voltage + [0x004e, ], #IBUFBIAS 0 - 10 μA , 312 pA Internal buffer bias (not in pixel) +#VCASP 66, VCASNA 169, VCASNB 183, VCASNC 233, VCASND 182, VCASN2 181 + + #Sequencer - 0x0100 registers are upper byte of the word + [0x0060, ], # PIXLOAD_A 0x00 + [0x0160, ], # 0x00 + [0x0070, ], # PIXLOAD_B 0x01 + [0x0170, ], # 0x00 + [0x0061, ], # PIXREAD_A 0x00 + [0x0161, ], # 0x00 + [0x0071, ], # PIXREAD_B 0x97 + [0x0171, ], # 0x00 + [0x0062, ], # PIXRSTB_A 0x98 + [0x0162, ], # 0x00 + [0x0072, ], # PIXRSTB_B 0x99 + [0x0172, ], # 0x00 + [0x0063, ], # DPSTART_A 0x00 + [0x0163, ], # 0x00 + [0x0073, ], # DPSTART_B 0x01 + [0x0173, ], # 0x00 + [0x0064, ], # DPTOKEN_A 0x01 + [0x0164, ], # 0x00 + [0x0074, ], # DPTOKEN_B 0x02 + [0x0174, ], # 0x00 + [0x0065, ], # DPEND_A 0x98 + [0x0165, ], # 0x00 + [0x0075, ], # DPEND_B 0x99 + [0x0175, ], # 0x00 + [0x0066, ], # PIXPULSEA_A 0x00 + [0x0166, ], # 0x00 + [0x0076, ], # PIXPULSEA_B 0x00 + [0x0176, ], # 0x00 + [0x0067, ], # PIXPULSED_A 0x00 + [0x0167, ], # 0x00 + [0x0077, ], # PIXPULSED_B 0x00 + [0x0177, ], # 0x00 + [0x0068, ], # MKSEQ1_A 0x00 + [0x0168, ], # 0x00 + [0x0078, ], # MKSEQ1_B 0x02 + [0x0178, ], # 0x00 + [0x0069, ], # MKSEQ2_A 0x00 + [0x0169, ], # 0x00 + [0x0079, ], # MKSEQ2_B 0x02 + [0x0179, ], # 0x00 + [0x007A, ], # POLARITY 0x05 + [0x017A, ], # 0x00 + [0x007B, ], # FRAMELENGTH 100 + [0x017B, ], # 0x00 + [0x007C, ], # MAXFRAME 0x00 + [0x017C, ], # 0x00 + [0x007D, ], # MODPULSE 0x00 + [0x007E, ], # MODPIXRSTB 0x00 + [0x007F, ], # MODMKSEQ1 0x00 + + #Monitoring (read only) + [0x00E0, ], # MON_POR_LOCK Power On Rest and PLL lock + [0x00E1, ], # MON_PAD PADs + [0x00E2, ], # MON_FR_CPT_0 Frame counter bits 7-0 + [0x00E3, ], # MON_FR_CPT_1 Frame counter bits 15-8 + [0x00E4, ], # MON_FR_CPT_2 Frame counter bits 23-16 + [0x00E5, ], # MON_FR_CPT_3 Frame counter bits 31-24 + [0x00E6, ], # EV_TMR_SEQ Triple Modular Redundancy Error in sequencer + [0x00E7, ], # EV_LOCK PLL lock + [0x00E8, ], # EV_LOCKFILTER PLL lock after filtering + [0x00E9, ], # EV_POR1 Power On Reset 1 + [0x00EA, ], # EV_POR2 Power On Reset 2 + [0x00EB, ], # EV_POR3 Power On Reset 3 + [0x00EC, ], # EV_RSTB RSTB pad + [0x00ED, ], # EV_START START all types (auto, pad, and soft) + [0x00EE, ], # EV_DPSTART Digital Periphery Start + + #Analog pixel selection + [0x8020, ], # SEL_ANAPIX0 Analogue Pixel Selection LSB + [0x8021, ], # SEL_ANAPIX1 Analogue Pixel Selection MSB + + #Readout test configuration + [0x8040, ], # PATTERN0 + [0x8041, ], # PATTERN1 + [0x8042, ], # PATTERN2 + [0x8043, ], # PATTERN3 + [0x8044, ], # PATTERN4 + [0x8045, ], # PATTERN5 + [0x8046, ], # PATTERN6 + [0x8047, ], # PATTERN7 + [0x8048, ], # PATTERN8 + [0x8049, ], # PATTERN9 + [0x804A, ], # PATTERN10 + [0x804B, ], # PATTERN11 + [0x804C, ], # PATTERN12 + [0x804D, ], # PATTERN13 + [0x804E, ], # PATTERN14 + [0x804F, ], # PATTERN15 + [0x8050, ], # BANDWIDTH0 + [0x8051, ], # BANDWIDTH1 + [0x8052, ], # FILLLEVEL0 #custom level at 1536 + [0x8053, ], # FILLLEVEL1 + + #Pixel control registers TBD + + #Multi frame emulation memories TBD + diff --git a/scripts/conf/CONF_S42.pl b/scripts/conf/CONF_S42.pl new file mode 100644 index 0000000..2c568f9 --- /dev/null +++ b/scripts/conf/CONF_S42.pl @@ -0,0 +1,136 @@ +#read files like my @config = do "CONF_allregisters.pl"; + + #General Control + [0x0020, ], #RUNMODE -> table 8 + [0x0021, ], #TRIMDAC -> table 9 + [0x0022, ], #INJCURR -> table 10 + [0x0023, ], #INJVOLT1 -> table 11 + [0x0024, ], #INJVOLT2 -> table 12 + [0x0025, ], #MONCURR -> table 13 + [0x0026, ], #MONVOLT -> table 14 + [0x0027, ], #CLKGEN1 -> table 15 + [0x0028, ], #CLKGEN2 -> table 16 + [0x0029, ], #PLL -> table 17 + [0x002a, ], #PLLLOCK -> table 18 + [0x002b, ], #MONTEMP -> table 19 + [0x002c, ], #SLVSTX -> table 20 + [0x002d, ], #SLVSRX -> table 21 + [0x002e, ], #OUTPUT -> table 22 + [0x002f, ], #MONPWR -> table 23 + + #DACs + [0x0040, ], #IBIAS 0 - 80 nA , 312 pA Pixel current + [0x0041, ], #ITHR 0 - 2.5 nA , 9.8 pA Pixel current + [0x0042, ], #IDB 0 - 40 nA , 157 pA Pixel current + [0x0043, ], #VRESET 0.37 - 1.79 V , 6 mV Pixel input amplifier reset voltage + [0x0044, ], #VPL 0.37 - 1.79 V , 6 mV Pixel voltage for charge injection (low value) + [0x0045, ], #VPH 0.37 - 1.79 V , 6 mV Pixel voltage for charge injection (high + [0x0046, ], #VPH_FINE 0 - 256 mV , 1 mV value) VPH+VPH_FINE + [0x0047, 66 ], #VCASP 0 - 1.54 V , 6 mV Pixel voltage + [0x0048, 112 ], #VCASNA 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix A + [0x0049, 113 ], #VCASNB 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix B + [0x004a, 123 ], #VCASNC 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix C + [0x004b, 90 ], #VCASND 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix D + [0x004c, 58 ], #VCASN2 0 - 1.54 V , 6 mV Pixel voltage + [0x004d, ], #VCLIP 0 - 1.54 V , 6 mV Pixel clipping amplifier voltage + [0x004e, ], #IBUFBIAS 0 - 10 μA , 312 pA Internal buffer bias (not in pixel) + + + #Sequencer - 0x0100 registers are upper byte of the word + [0x0060, ], # PIXLOAD_A 0x00 + [0x0160, ], # 0x00 + [0x0070, ], # PIXLOAD_B 0x01 + [0x0170, ], # 0x00 + [0x0061, ], # PIXREAD_A 0x00 + [0x0161, ], # 0x00 + [0x0071, ], # PIXREAD_B 0x97 + [0x0171, ], # 0x00 + [0x0062, ], # PIXRSTB_A 0x98 + [0x0162, ], # 0x00 + [0x0072, ], # PIXRSTB_B 0x99 + [0x0172, ], # 0x00 + [0x0063, ], # DPSTART_A 0x00 + [0x0163, ], # 0x00 + [0x0073, ], # DPSTART_B 0x01 + [0x0173, ], # 0x00 + [0x0064, ], # DPTOKEN_A 0x01 + [0x0164, ], # 0x00 + [0x0074, ], # DPTOKEN_B 0x02 + [0x0174, ], # 0x00 + [0x0065, ], # DPEND_A 0x98 + [0x0165, ], # 0x00 + [0x0075, ], # DPEND_B 0x99 + [0x0175, ], # 0x00 + [0x0066, ], # PIXPULSEA_A 0x00 + [0x0166, ], # 0x00 + [0x0076, ], # PIXPULSEA_B 0x00 + [0x0176, ], # 0x00 + [0x0067, ], # PIXPULSED_A 0x00 + [0x0167, ], # 0x00 + [0x0077, ], # PIXPULSED_B 0x00 + [0x0177, ], # 0x00 + [0x0068, ], # MKSEQ1_A 0x00 + [0x0168, ], # 0x00 + [0x0078, ], # MKSEQ1_B 0x02 + [0x0178, ], # 0x00 + [0x0069, ], # MKSEQ2_A 0x00 + [0x0169, ], # 0x00 + [0x0079, ], # MKSEQ2_B 0x02 + [0x0179, ], # 0x00 + [0x007A, ], # POLARITY 0x05 + [0x017A, ], # 0x00 + [0x007B, ], # FRAMELENGTH 100 + [0x017B, ], # 0x00 + [0x007C, ], # MAXFRAME 0x00 + [0x017C, ], # 0x00 + [0x007D, ], # MODPULSE 0x00 + [0x007E, ], # MODPIXRSTB 0x00 + [0x007F, ], # MODMKSEQ1 0x00 + + #Monitoring (read only) + [0x00E0, ], # MON_POR_LOCK Power On Rest and PLL lock + [0x00E1, ], # MON_PAD PADs + [0x00E2, ], # MON_FR_CPT_0 Frame counter bits 7-0 + [0x00E3, ], # MON_FR_CPT_1 Frame counter bits 15-8 + [0x00E4, ], # MON_FR_CPT_2 Frame counter bits 23-16 + [0x00E5, ], # MON_FR_CPT_3 Frame counter bits 31-24 + [0x00E6, ], # EV_TMR_SEQ Triple Modular Redundancy Error in sequencer + [0x00E7, ], # EV_LOCK PLL lock + [0x00E8, ], # EV_LOCKFILTER PLL lock after filtering + [0x00E9, ], # EV_POR1 Power On Reset 1 + [0x00EA, ], # EV_POR2 Power On Reset 2 + [0x00EB, ], # EV_POR3 Power On Reset 3 + [0x00EC, ], # EV_RSTB RSTB pad + [0x00ED, ], # EV_START START all types (auto, pad, and soft) + [0x00EE, ], # EV_DPSTART Digital Periphery Start + + #Analog pixel selection + [0x8020, ], # SEL_ANAPIX0 Analogue Pixel Selection LSB + [0x8021, ], # SEL_ANAPIX1 Analogue Pixel Selection MSB + + #Readout test configuration + [0x8040, ], # PATTERN0 + [0x8041, ], # PATTERN1 + [0x8042, ], # PATTERN2 + [0x8043, ], # PATTERN3 + [0x8044, ], # PATTERN4 + [0x8045, ], # PATTERN5 + [0x8046, ], # PATTERN6 + [0x8047, ], # PATTERN7 + [0x8048, ], # PATTERN8 + [0x8049, ], # PATTERN9 + [0x804A, ], # PATTERN10 + [0x804B, ], # PATTERN11 + [0x804C, ], # PATTERN12 + [0x804D, ], # PATTERN13 + [0x804E, ], # PATTERN14 + [0x804F, ], # PATTERN15 + [0x8050, ], # BANDWIDTH0 + [0x8051, ], # BANDWIDTH1 + [0x8052, ], # FILLLEVEL0 #custom level at 1536 + [0x8053, ], # FILLLEVEL1 + + #Pixel control registers TBD + + #Multi frame emulation memories TBD + diff --git a/scripts/conf/CONF_VCAS_high.pl b/scripts/conf/CONF_VCAS_high.pl new file mode 100644 index 0000000..afd6baf --- /dev/null +++ b/scripts/conf/CONF_VCAS_high.pl @@ -0,0 +1,135 @@ +#read files like my @config = do "CONF_allregisters.pl"; + + #General Control + [0x0020, ], #RUNMODE -> table 8 + [0x0021, ], #TRIMDAC -> table 9 + [0x0022, ], #INJCURR -> table 10 + [0x0023, ], #INJVOLT1 -> table 11 + [0x0024, ], #INJVOLT2 -> table 12 + [0x0025, ], #MONCURR -> table 13 + [0x0026, ], #MONVOLT -> table 14 + [0x0027, ], #CLKGEN1 -> table 15 + [0x0028, ], #CLKGEN2 -> table 16 + [0x0029, ], #PLL -> table 17 + [0x002a, ], #PLLLOCK -> table 18 + [0x002b, ], #MONTEMP -> table 19 + [0x002c, ], #SLVSTX -> table 20 + [0x002d, ], #SLVSRX -> table 21 + [0x002e, ], #OUTPUT -> table 22 + [0x002f, ], #MONPWR -> table 23 + + #DACs + [0x0040, ], #IBIAS 0 - 80 nA , 312 pA Pixel current + [0x0041, ], #ITHR 0 - 2.5 nA , 9.8 pA Pixel current + [0x0042, ], #IDB 0 - 40 nA , 157 pA Pixel current + [0x0043, ], #VRESET 0.37 - 1.79 V , 6 mV Pixel input amplifier reset voltage + [0x0044, ], #VPL 0.37 - 1.79 V , 6 mV Pixel voltage for charge injection (low value) + [0x0045, ], #VPH 0.37 - 1.79 V , 6 mV Pixel voltage for charge injection (high + [0x0046, ], #VPH_FINE 0 - 256 mV , 1 mV value) VPH+VPH_FINE + [0x0047, ], #VCASP 0 - 1.54 V , 6 mV Pixel voltage + [0x0048, 00 ], #VCASNA 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix A + [0x0049, 00 ], #VCASNB 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix B + [0x004a, 00 ], #VCASNC 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix C + [0x004b, 00 ], #VCASND 0 - 1.54 V , 6 mV Pixel threshold voltage for submatrix D + [0x004c, 5 ], #VCASN2 0 - 1.54 V , 6 mV Pixel voltage + [0x004d, ], #VCLIP 0 - 1.54 V , 6 mV Pixel clipping amplifier voltage + [0x004e, ], #IBUFBIAS 0 - 10 μA , 312 pA Internal buffer bias (not in pixel) + + #Sequencer - 0x0100 registers are upper byte of the word + [0x0060, ], # PIXLOAD_A 0x00 + [0x0160, ], # 0x00 + [0x0070, ], # PIXLOAD_B 0x01 + [0x0170, ], # 0x00 + [0x0061, ], # PIXREAD_A 0x00 + [0x0161, ], # 0x00 + [0x0071, ], # PIXREAD_B 0x97 + [0x0171, ], # 0x00 + [0x0062, ], # PIXRSTB_A 0x98 + [0x0162, ], # 0x00 + [0x0072, ], # PIXRSTB_B 0x99 + [0x0172, ], # 0x00 + [0x0063, ], # DPSTART_A 0x00 + [0x0163, ], # 0x00 + [0x0073, ], # DPSTART_B 0x01 + [0x0173, ], # 0x00 + [0x0064, ], # DPTOKEN_A 0x01 + [0x0164, ], # 0x00 + [0x0074, ], # DPTOKEN_B 0x02 + [0x0174, ], # 0x00 + [0x0065, ], # DPEND_A 0x98 + [0x0165, ], # 0x00 + [0x0075, ], # DPEND_B 0x99 + [0x0175, ], # 0x00 + [0x0066, ], # PIXPULSEA_A 0x00 + [0x0166, ], # 0x00 + [0x0076, ], # PIXPULSEA_B 0x00 + [0x0176, ], # 0x00 + [0x0067, ], # PIXPULSED_A 0x00 + [0x0167, ], # 0x00 + [0x0077, ], # PIXPULSED_B 0x00 + [0x0177, ], # 0x00 + [0x0068, ], # MKSEQ1_A 0x00 + [0x0168, ], # 0x00 + [0x0078, ], # MKSEQ1_B 0x02 + [0x0178, ], # 0x00 + [0x0069, ], # MKSEQ2_A 0x00 + [0x0169, ], # 0x00 + [0x0079, ], # MKSEQ2_B 0x02 + [0x0179, ], # 0x00 + [0x007A, ], # POLARITY 0x05 + [0x017A, ], # 0x00 + [0x007B, ], # FRAMELENGTH 100 + [0x017B, ], # 0x00 + [0x007C, ], # MAXFRAME 0x00 + [0x017C, ], # 0x00 + [0x007D, ], # MODPULSE 0x00 + [0x007E, ], # MODPIXRSTB 0x00 + [0x007F, ], # MODMKSEQ1 0x00 + + #Monitoring (read only) + [0x00E0, ], # MON_POR_LOCK Power On Rest and PLL lock + [0x00E1, ], # MON_PAD PADs + [0x00E2, ], # MON_FR_CPT_0 Frame counter bits 7-0 + [0x00E3, ], # MON_FR_CPT_1 Frame counter bits 15-8 + [0x00E4, ], # MON_FR_CPT_2 Frame counter bits 23-16 + [0x00E5, ], # MON_FR_CPT_3 Frame counter bits 31-24 + [0x00E6, ], # EV_TMR_SEQ Triple Modular Redundancy Error in sequencer + [0x00E7, ], # EV_LOCK PLL lock + [0x00E8, ], # EV_LOCKFILTER PLL lock after filtering + [0x00E9, ], # EV_POR1 Power On Reset 1 + [0x00EA, ], # EV_POR2 Power On Reset 2 + [0x00EB, ], # EV_POR3 Power On Reset 3 + [0x00EC, ], # EV_RSTB RSTB pad + [0x00ED, ], # EV_START START all types (auto, pad, and soft) + [0x00EE, ], # EV_DPSTART Digital Periphery Start + + #Analog pixel selection + [0x8020, ], # SEL_ANAPIX0 Analogue Pixel Selection LSB + [0x8021, ], # SEL_ANAPIX1 Analogue Pixel Selection MSB + + #Readout test configuration + [0x8040, ], # PATTERN0 + [0x8041, ], # PATTERN1 + [0x8042, ], # PATTERN2 + [0x8043, ], # PATTERN3 + [0x8044, ], # PATTERN4 + [0x8045, ], # PATTERN5 + [0x8046, ], # PATTERN6 + [0x8047, ], # PATTERN7 + [0x8048, ], # PATTERN8 + [0x8049, ], # PATTERN9 + [0x804A, ], # PATTERN10 + [0x804B, ], # PATTERN11 + [0x804C, ], # PATTERN12 + [0x804D, ], # PATTERN13 + [0x804E, ], # PATTERN14 + [0x804F, ], # PATTERN15 + [0x8050, ], # BANDWIDTH0 + [0x8051, ], # BANDWIDTH1 + [0x8052, ], # FILLLEVEL0 #custom level at 1536 + [0x8053, ], # FILLLEVEL1 + + #Pixel control registers TBD + + #Multi frame emulation memories TBD + diff --git a/scripts/conf/CONF_testmode_disable.pl b/scripts/conf/CONF_testmode_disable.pl new file mode 100644 index 0000000..1d51f04 --- /dev/null +++ b/scripts/conf/CONF_testmode_disable.pl @@ -0,0 +1,3 @@ +#read files like my @config = do "CONF_allregisters.pl"; +#same like testmode_enabled.pl + [0x0020, 0x40 ], # diff --git a/scripts/testmode_enable.sh b/scripts/testmode_enable.sh deleted file mode 100755 index a82a639..0000000 --- a/scripts/testmode_enable.sh +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/bash - -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x40aa -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x41fc -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x42aa -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x43fc -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x44aa -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x45fc -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x46aa -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x47fc -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x48aa -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x49fc -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x4aaa -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x4bfc -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x4caa -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x4dfc -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x4eaa -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x80 -d 0x4ffc - -./i2c_cmd2.pl -w 1 -f 0xa000 -a 0x12 -c 0x00 -d 0x2048 -