From: hadeshyp Date: Wed, 9 Jun 2010 16:17:36 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c06ca71c46318ec0151087c87cc7493863412323;p=daqdocu.git *** empty log message *** --- diff --git a/installation_ethernet.tex b/installation_ethernet.tex new file mode 100644 index 0000000..c265ac7 --- /dev/null +++ b/installation_ethernet.tex @@ -0,0 +1 @@ +t.b.d. \ No newline at end of file diff --git a/installation_trbnet.tex b/installation_trbnet.tex new file mode 100644 index 0000000..04ba821 --- /dev/null +++ b/installation_trbnet.tex @@ -0,0 +1,65 @@ +\subsection{TrbNet Hub} +The first FPGA handles ports 1 to 16, the second FPGA is connected to ports 17 to 20. The assignment of hardware (physical) ports to internal (logical) port numbers can be found below. The logical port number 0 is always the main up-link of the FPGA. +\begin{description} + \item[Port 1 -- 4] These ports are not used + \item[Port 5 -- 16] These ports are located on the long side of the AddOn. Internally, they are mapped to port number 2 -- 13 of FPGA 1 (network addresses ending with 1). Port 5 can be used as uplink (connection towards the CTS) if (and only if) the second FPGA on the board is not configured, all other ports are downlinks (from FEE). + \item[Port 17] Configured for GbE readout. + \item[Port 18] Configured to serve both as uplink or downlink. Mapped to port number 0 on FPGA 2 (network address ending with 0). On the central Hub this port is used to support the connection to the slow control TRB. + \item[Port 19] Spare downlink, mapped to logical port 1 of FPGA 1. + \item[Port 20] Main uplink. This port must provide the connection to the CTS. Mapped to logical port 3 of FPGA 2 (currently not listed as connected in the corresponding status registers) + \item[FPGA 1, logical port 0] This port is the link connecting both FPGA on the board. + \item[FPGA 2, logical port 2] This port is the link connecting both FPGA on the board. +\end{description} + +The internal endpoint used to control and monitor the hub is always connected to the next logical port number above the physically available ports. I.e. in FPGA 1 it is connected to logical port 13, on FPGA2 to logical port 4. + +The usage of physical ports 5 -- 16 on TrbNet Hubs is given in the following lists + +\begin{table} +\begin{center} +\begin{tabularx}{\textwidth}{|c|c|X|} +\hline +\textbf{Physical Port} & \textbf{Logical Port} & \textbf{Subsystem} \\ +\hline +\hline +- & 0 & Uplink to second FPGA \\ +5 & 1 & RPC sectors 1,2,3 \\ +6 & 2 & RPC sectors 4,5,6 \\ +7 & 3 & MDC planes 1,2 \\ +8 & 4 & MDC planes 3,4 \\ +9 & 5 & Forward Wall \\ +10 & 6 & TOF \\ +11 & 7 & Shower \\ +12 & 8 & RICH sectors 1,2 \\ +13 & 9 & RICH sectors 3,4 \\ +14 & 10 & RICH sectors 5,6 \\ +15 & 11 & Start/Veto/CTS \\ +\hline +\end{tabularx} +\caption{Port usage on central TrbNet hub} +\label{centralhubports} +\end{center} +\end{table} + +\begin{description} + \item[Central Hub (0x8001)] The central hub connects all subsystems together. Table \ref{centralhubports} shows the physical and logical port numbers and the subsystems connected to them. + \item[MDC Hub plane 1,2 (0x8101)] The hub connecting the six MDC Hubs for MDC planes 1 and 2. Logical ports 1 to 6 are used for sectors 1 to 6 (naturally in the same order) + \item[MDC Hub plane 3,4 (0x8111)] The hub connecting the six MDC Hubs for MDC planes 3 and 4. Logical ports 1 to 6 are used for sectors 1 to 6 (naturally in the same order) + \item[RICH Hub sector 1,2 (0x8301)] Port 1 to 5 connect to the ADCM in sector 1, port 6 to 10 connect to the boards in sector 2. + \item[RICH Hub sector 3,4 (0x8311)] Port 1 to 5 connect to the ADCM in sector 3, port 6 to 10 connect to the boards in sector 4. + \item[RICH Hub sector 3,4 (0x8321)] Port 1 to 5 connect to the ADCM in sector 5, port 6 to 10 connect to the boards in sector 6. + \item[RPC Hub Sector 1,2,3 (0x8401)] This hub connects all 12 TRB of the first three sectors. Sector 1 is connected to logical ports 1 to 4, sector 2 on ports 5 to 8, sector 3 on ports 9 to 12. The TRB in each sector are numbered from 0 to 3, the ports are connected in the same order. + \item[RPC Hub Sector 4,5,6 (0x8411)] This hub connects all 12 TRB of the last three sectors. Sector 4 is connected to logical ports 1 to 4, sector 5 on ports 5 to 8, sector 6 on ports 9 to 12. The TRB in each sector are numbered from 0 to 3, the ports are connected in the same order. + \item[Shower Hub (0x8501)] Port 1 to 6 connect to the Shower AddOn in each of the sectors. + \item[TOF Hub (0x8601)] Port 1 to 6 connect to the TRBs in each of the sectors, Port 7 is used for the additional TRB. + \item[Forward Wall (0x8701)] This hub connects the three TRB of Forward Wall. Ports 1 to 3 are used, connected in the same order as the TRB are numbered. + \item[Start/Veto/CTS Hub (0x8801)] Port 1 connects to the Start-TRB, Port 2 to the Veto TRB, Port 3 to the CTS. +\end{description} + +\subsection{MDC Hub} +The MDC Hub has 5 FPGAs: FPGA 1 serves the first 8 FOT, FPGA 2 the second 8 FOT, FPGA 3 controls FOT 17 to 24, FPGA 4 FOT 25 to 32. The fifth FPGA controls the Uplink (logical port 0) and connects to the other 4 FPGAs (FPGA1: port 1 -- FPGA4: port 4). + +Each MDC Hub is used to read out one sector of inner or outer MDC, two chambers on one board. FOT 1 to 16 connects the inner of the two chambers (planes 1 or 3), FOT 17 to 32 connect the outer chamber (plane 2 or 4). + +The OEPs on each sector are mounted in the same order as their numbers on the chamber, e.g. OEP 0 connects to FOT 0 (respectively FOT 17), OEP 8 connects to FOT 8 (24 resp.) and OEP 0xF connects to FOT 16 (or 32). +