From: Jan Michel Date: Fri, 11 Aug 2017 15:03:17 +0000 (+0200) Subject: Update backplane master: Use internal clock for sending data, not received clock... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c080bd12e79fa38b8ddc0e279c5fb8d33ee8818d;p=trb3sc.git Update backplane master: Use internal clock for sending data, not received clock from SFP. Update to new Diamond. --- diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd index c44a7ea..870783b 100644 --- a/backplanemaster/config.vhd +++ b/backplanemaster/config.vhd @@ -26,8 +26,8 @@ package config is constant INCLUDE_UART : integer := c_YES; constant INCLUDE_SPI : integer := c_YES; - constant INCLUDE_LCD : integer := c_YES; - constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + constant INCLUDE_LCD : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; --input monitor and trigger generation logic constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; diff --git a/backplanemaster/config_compile_frankfurt.pl b/backplanemaster/config_compile_frankfurt.pl index 1527acf..410d0c3 100644 --- a/backplanemaster/config_compile_frankfurt.pl +++ b/backplanemaster/config_compile_frankfurt.pl @@ -1,9 +1,9 @@ TOPNAME => "trb3sc_master", -lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/d/jspc29/lattice/diamond/3.6_x64', -synplify_path => '/d/jspc29/lattice/synplify/J-2014.09-SP2/', -synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +lattice_path => '/d/jspc29/lattice/diamond/3.9_x64/', +synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', +# synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", #synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", nodelist_file => 'nodelist_frankfurt.txt', diff --git a/backplanemaster/par.p2t b/backplanemaster/par.p2t index f72683d..d03f522 100644 --- a/backplanemaster/par.p2t +++ b/backplanemaster/par.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 24 +-t 15 -c 1 -e 2 #-g guidefile.ncd @@ -18,4 +18,5 @@ # -c 0 # -e 0 # --exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 +#-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 +-exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parHold=ON:parHoldLimit=10000 diff --git a/backplanemaster/trb3sc_master.lpf b/backplanemaster/trb3sc_master.lpf index 029bb98..6fc192d 100644 --- a/backplanemaster/trb3sc_master.lpf +++ b/backplanemaster/trb3sc_master.lpf @@ -1,12 +1,23 @@ -LOCATE COMP "THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST" SITE "PCSB" ; +LOCATE COMP "THE_MEDIA_INT_MIXED/THE_SERDES/PCSD_INST" SITE "PCSB" ; LOCATE COMP "THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST" SITE "PCSA" ; LOCATE COMP "THE_MEDIA_4_DOWN2/THE_SERDES/PCSD_INST" SITE "PCSC" ; -REGION "MEDIA_DOWN1" "R102C40D" 13 100; -LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_DOWN1" ; +#REGION "MEDIA_DOWN1" "R93C10D" 22 160; +#REGION "MEDIA_DOWN1" "R100C40D" 15 100; +#LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_DOWN1" ; LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; +REGION "MEDIA_A" "R75C100D" 45 46; +REGION "MEDIA_B" "R75C50D" 45 46; +REGION "MEDIA_C" "R75C135D" 45 46; +REGION "MEDIA_D" "R75C19D" 40 36; + +LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_A" ; +LOCATE UGROUP "THE_MEDIA_INT_MIXED/media_interface_group" REGION "MEDIA_B" ; +LOCATE UGROUP "THE_MEDIA_4_DOWN2/media_interface_group" REGION "MEDIA_C" ; +#LOCATE UGROUP "THE_MEDIA_4_DOWN_D/media_interface_group" REGION "MEDIA_D" ; + MULTICYCLE TO CELL "THE_MEDIA_4_DOW*/sci*" 20 ns; @@ -152,4 +163,4 @@ MAXDELAY TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns; # PRIORITIZE NET "GBE/pcs_rxd_q[6]" 100 ; # PRIORITIZE NET "GBE/pcs_rxd_q[7]" 100 ; # PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ; -# PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ; \ No newline at end of file +# PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ; diff --git a/backplanemaster/trb3sc_master.prj b/backplanemaster/trb3sc_master.prj index 02e544e..af8aef6 100644 --- a/backplanemaster/trb3sc_master.prj +++ b/backplanemaster/trb3sc_master.prj @@ -117,7 +117,7 @@ add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" -add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" #SlowControl files @@ -214,6 +214,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd" add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v" add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v" diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd index 5dc04b9..ff06daf 100644 --- a/backplanemaster/trb3sc_master.vhd +++ b/backplanemaster/trb3sc_master.vhd @@ -100,6 +100,7 @@ architecture trb3sc_arch of trb3sc_master is signal GSR_N : std_logic; signal reset_i : std_logic; signal clear_i : std_logic; + signal do_reboot_i, reboot_from_gbe : std_logic; signal time_counter : unsigned(31 downto 0) := (others => '0'); signal led : std_logic_vector(1 downto 0); @@ -207,7 +208,7 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_4_slave3 --PCSB IS_USED => (c_YES, c_YES, c_YES ,c_YES) ) port map( - CLK_REF_FULL => med2int(INTERFACE_NUM-1).clk_full, + CLK_REF_FULL => clk_full_osc, --med2int(INTERFACE_NUM-1).clk_full, CLK_INTERNAL_FULL => clk_full_osc, SYSCLK => clk_sys, RESET => reset_i, @@ -259,7 +260,7 @@ THE_MEDIA_4_DOWN : entity work.med_ecp3_sfp_sync_4 --PCSA IS_USED => (c_YES,c_YES ,c_YES ,c_YES) ) port map( - CLK_REF_FULL => med2int(INTERFACE_NUM-1).clk_full, + CLK_REF_FULL => clk_full_osc, --med2int(INTERFACE_NUM-1).clk_full, CLK_INTERNAL_FULL => clk_full_osc, SYSCLK => clk_sys, RESET => reset_i, @@ -295,7 +296,7 @@ THE_MEDIA_4_DOWN2 : entity work.med_ecp3_sfp_sync_4 --PCSC IS_USED => (c_YES,c_YES ,c_NO ,c_NO) ) port map( - CLK_REF_FULL => med2int(INTERFACE_NUM-1).clk_full, + CLK_REF_FULL => clk_full_osc, --med2int(INTERFACE_NUM-1).clk_full, CLK_INTERNAL_FULL => clk_full_osc, SYSCLK => clk_sys, RESET => reset_i, @@ -340,7 +341,7 @@ THE_MEDIA_4_DOWN2 : entity work.med_ecp3_sfp_sync_4 --PCSC gen_ready_signals : for i in 0 to 8 generate backplane_rx_present(i) <= BACK_SLAVE_READY(i); - BACK_MASTER_READY(i) <= backplane_tx_present(i); + BACK_MASTER_READY(i) <= backplane_tx_present(i) or SFP_LOS(1); monitor_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i); end generate; @@ -379,9 +380,7 @@ gen_GBE : if INCLUDE_GBE = 1 generate LINK_HAS_SLOWCTRL => "0001", LINK_HAS_DHCP => "0001", LINK_HAS_ARP => "0001", - LINK_HAS_PING => "0001", - - NUMBER_OF_OUTPUT_LINKS => 1 + LINK_HAS_PING => "0001" ) port map( @@ -415,6 +414,8 @@ gen_GBE : if INCLUDE_GBE = 1 generate FEE_BUSY_IN => fee_busy, MC_UNIQUE_ID_IN => mc_unique_id, + MY_TRBNET_ADDRESS_IN => my_address, + ISSUE_REBOOT_OUT => reboot_from_gbe, GSC_CLK_IN => clk_sys, GSC_INIT_DATAREADY_OUT => gsc_init_dataready, @@ -573,7 +574,7 @@ end generate; FLASH_IN => FLASH_OUT, FLASH_OUT => FLASH_IN, PROGRAMN => PROGRAMN, - REBOOT_IN => common_ctrl_reg(15), + REBOOT_IN => do_reboot_i, --SPI SPI_CS_OUT => spi_cs, SPI_MOSI_OUT=> spi_mosi, @@ -605,6 +606,8 @@ end generate; DEBUG_OUT => open ); +do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe; + --------------------------------------------------------------------------- -- Switches --------------------------------------------------------------------------- @@ -643,7 +646,7 @@ end generate; -- Backplane --------------------------------------------------------------------------- BACK_LVDS(0) <= clk_full; - BACK_LVDS(1) <= clk_sys; + BACK_LVDS(1) <= TRIG_LEFT; RJ_IO(3 downto 2) <= trig_gen_out_i(1 downto 0);