From: Jan Michel Date: Tue, 11 Feb 2014 17:47:46 +0000 (+0100) Subject: some new files for ADC addon X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c0a08b027b6334b806509d2b30517975dd0e010e;p=trb3.git some new files for ADC addon --- diff --git a/ADC/compile_periph_frankfurt.pl b/ADC/compile_periph_frankfurt.pl index 79066c3..97e8368 100755 --- a/ADC/compile_periph_frankfurt.pl +++ b/ADC/compile_periph_frankfurt.pl @@ -9,8 +9,8 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_adc"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/2.2_x64'; -my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/'; +my $lattice_path = '/d/jspc29/lattice/diamond/3.0_x64'; +my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; ################################################################################### diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd index 1b2617a..a8dc9c3 100644 --- a/ADC/trb3_periph_adc.vhd +++ b/ADC/trb3_periph_adc.vhd @@ -205,7 +205,9 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is signal clk_adcref_i : std_logic; signal debug_adc : std_logic_vector(31 downto 0); signal adc_restart_i : std_logic; - +type q_t is array(0 to 4) of std_logic_vector(19 downto 0); +signal q : q_t; +signal clk_data_left : std_logic; begin --------------------------------------------------------------------------- -- Reset Generation @@ -417,40 +419,74 @@ begin --------------------------------------------------------------------------- -- AddOn --------------------------------------------------------------------------- -THE_ADC : entity work.adc_ad9219 - generic map( - CHANNELS => 4, - DEVICES_LEFT => 7, - DEVICES_RIGHT => 5, - RESOLUTION => 10 - ) - port map( - CLK => clk_100_i, - CLK_ADCREF => clk_adcref_i, - CLK_ADCDAT => clk_adcfast_i, - RESTART_IN => adc_restart_i, - ADCCLK_OUT => P_CLOCK, - - ADC_DATA( 4 downto 0) => ADC1_CH, - ADC_DATA( 9 downto 5) => ADC2_CH, - ADC_DATA(14 downto 10) => ADC3_CH, - ADC_DATA(19 downto 15) => ADC4_CH, - ADC_DATA(24 downto 20) => ADC5_CH, - ADC_DATA(29 downto 25) => ADC6_CH, - ADC_DATA(34 downto 30) => ADC7_CH, - ADC_DATA(39 downto 35) => ADC8_CH, - ADC_DATA(44 downto 40) => ADC9_CH, - ADC_DATA(49 downto 45) => ADC10_CH, - ADC_DATA(54 downto 50) => ADC11_CH, - ADC_DATA(59 downto 55) => ADC12_CH, - - ADC_DCO => ADC_DCO, - - DATA_OUT => open, - FCO_OUT => open, - DATA_VALID_OUT => open, - DEBUG => debug_adc - ); +-- THE_ADC : entity work.adc_ad9219 +-- generic map( +-- CHANNELS => 4, +-- DEVICES_LEFT => 7, +-- DEVICES_RIGHT => 5, +-- RESOLUTION => 10 +-- ) +-- port map( +-- CLK => clk_100_i, +-- CLK_ADCREF => clk_adcref_i, +-- CLK_ADCDAT => clk_adcfast_i, +-- RESTART_IN => adc_restart_i, +-- ADCCLK_OUT => P_CLOCK, +-- +-- ADC_DATA( 4 downto 0) => ADC1_CH, +-- ADC_DATA( 9 downto 5) => ADC2_CH, +-- ADC_DATA(14 downto 10) => ADC3_CH, +-- ADC_DATA(19 downto 15) => ADC4_CH, +-- ADC_DATA(24 downto 20) => ADC5_CH, +-- ADC_DATA(29 downto 25) => ADC6_CH, +-- ADC_DATA(34 downto 30) => ADC7_CH, +-- ADC_DATA(39 downto 35) => ADC8_CH, +-- ADC_DATA(44 downto 40) => ADC9_CH, +-- ADC_DATA(49 downto 45) => ADC10_CH, +-- ADC_DATA(54 downto 50) => ADC11_CH, +-- ADC_DATA(59 downto 55) => ADC12_CH, +-- +-- ADC_DCO => ADC_DCO, +-- +-- DATA_OUT => open, +-- FCO_OUT => open, +-- DATA_VALID_OUT => open, +-- DEBUG => debug_adc +-- ); + + +THE_LEFT : entity work.dqsinput_5x5 + port map( + clk_0 => ADC_DCO(8), + clk_1 => ADC_DCO(9), + clk_2 => ADC_DCO(10), + clk_3 => ADC_DCO(11), + clk_4 => ADC_DCO(12), + clkdiv_reset => '0', + eclk => clk_adcref_i, + reset_0 => '0', + reset_1 => '0', + reset_2 => '0', + reset_3 => '0', + reset_4 => '0', + sclk => clk_data_left, + datain_0 => ADC8_CH, + datain_1 => ADC9_CH, + datain_2 => ADC10_CH, + datain_3 => ADC11_CH, + datain_4 => ADC12_CH, + q_0 => q(0), + q_1 => q(1), + q_2 => q(2), + q_3 => q(3), + q_4 => q(4) + ); + + +--Just to hinder optimization to remove the DDR buffers +LED_RED <= q(0)(0) or q(1)(0) or q(2)(0) or q(3)(0) or q(4)(0); + + adc_restart_i <= '0'; @@ -569,7 +605,7 @@ FPGA_SPI : spi_ltc2600 --------------------------------------------------------------------------- LED_GREEN <= not med_stat_op(9); LED_ORANGE <= not med_stat_op(10); -LED_RED <= not or_all(debug_adc) when rising_edge(clk_100_i); +-- LED_RED <= not or_all(debug_adc) when rising_edge(clk_100_i); LED_YELLOW <= not med_stat_op(11); --------------------------------------------------------------------------- diff --git a/base/cores/dqsinput_5x5.ipx b/base/cores/dqsinput_5x5.ipx index ec2de68..3950e26 100644 --- a/base/cores/dqsinput_5x5.ipx +++ b/base/cores/dqsinput_5x5.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/base/cores/dqsinput_5x5.lpc b/base/cores/dqsinput_5x5.lpc index 822c416..d1d2996 100644 --- a/base/cores/dqsinput_5x5.lpc +++ b/base/cores/dqsinput_5x5.lpc @@ -1,8 +1,8 @@ [Device] Family=latticeecp3 PartType=LFE3-150EA -PartName=LFE3-150EA-6FN672C -SpeedGrade=6 +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 Package=FPBGA672 OperatingCondition=COM Status=P @@ -17,7 +17,7 @@ ModuleName=dqsinput_5x5 SourceFormat=VHDL ParameterFileVersion=1.0 Date=02/03/2014 -Time=17:39:54 +Time=22:55:31 [Parameters] Verilog=0 diff --git a/base/cores/dqsinput_5x5.vhd b/base/cores/dqsinput_5x5.vhd index cd81aba..a54ef14 100644 --- a/base/cores/dqsinput_5x5.vhd +++ b/base/cores/dqsinput_5x5.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_2.2_Production (99) +-- VHDL netlist generated by SCUBA Diamond_3.0_Production (94) -- Module Version: 5.4 ---/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n dqsinput_5x5 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 200 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -dqs 3 5 -dqs 4 5 -dqs 5 5 -e +--/d/jspc29/lattice/diamond/3.0_x64/ispfpga/bin/lin64/scuba -w -n dqsinput_5x5 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 200 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -dqs 3 5 -dqs 4 5 -dqs 5 5 -e --- Mon Feb 3 17:39:55 2014 +-- Mon Feb 3 22:55:31 2014 library IEEE; use IEEE.std_logic_1164.all;