From: HeH Date: Mon, 13 Jun 2022 20:40:33 +0000 (+0200) Subject: Added RJ45 addon trigger or logic project X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c0fb037ba8f0534421c3c75b035d4346e372d17a;p=trb5sc.git Added RJ45 addon trigger or logic project --- diff --git a/or_logic_rj45/README b/or_logic_rj45/README new file mode 100644 index 0000000..eb6db9c --- /dev/null +++ b/or_logic_rj45/README @@ -0,0 +1,7 @@ +The tdc repository branch has to be set to sep17. + +Run + +$ git checkout sep17 + +in tdc repository folder. diff --git a/or_logic_rj45/compile.pl b/or_logic_rj45/compile.pl new file mode 120000 index 0000000..933ff60 --- /dev/null +++ b/or_logic_rj45/compile.pl @@ -0,0 +1 @@ +../../trb3/scripts/compile.pl \ No newline at end of file diff --git a/or_logic_rj45/config.vhd b/or_logic_rj45/config.vhd new file mode 100644 index 0000000..a71dfc9 --- /dev/null +++ b/or_logic_rj45/config.vhd @@ -0,0 +1,123 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + + +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 2; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size + -- mode: 0, 1, 2, 3, 7 + -- size: 32, 64, 96, 128, dyn + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC + -- 0: Single fine time as the sum of the two transitions + -- 1: Double fine time, individual transitions + -- 13: Debug - fine time + (if 0x3ff full chain) + -- 14: Debug - single fine time and the ROM addresses for the two transitions + -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F860"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"86"; + + constant INCLUDE_UART : integer := c_YES; --300 slices + constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 4; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 4; + + constant FPGA_SIZE : string := "85KUM"; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := (others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/or_logic_rj45/config_compile_frankfurt.pl b/or_logic_rj45/config_compile_frankfurt.pl new file mode 100644 index 0000000..9dc053b --- /dev/null +++ b/or_logic_rj45/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_template", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.12', +synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'trb5sc_tdc', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/or_logic_rj45/config_compile_gsi.pl b/or_logic_rj45/config_compile_gsi.pl new file mode 100644 index 0000000..a986848 --- /dev/null +++ b/or_logic_rj45/config_compile_gsi.pl @@ -0,0 +1,26 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + +TOPNAME => "trb5sc_or_logic_rj45", +lm_license_file_for_synplify => "27000\@lxcad04.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.12', +synplify_path => '/opt/synplicity/P-2019.09-SP1', +#synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/opt/synplicity/P-2019.09-SP1/bin/synplify_premier_dp", +synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier_dp", + +nodelist_file => "../nodelist_hades68.txt", +pinout_file => 'trb5sc_rj45', +par_options => '../par.p2t', + +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/or_logic_rj45/nodelist_frankfurt.txt b/or_logic_rj45/nodelist_frankfurt.txt new file mode 100644 index 0000000..2e858da --- /dev/null +++ b/or_logic_rj45/nodelist_frankfurt.txt @@ -0,0 +1,13 @@ +// nodes file for parallel place&route + +[jspc37] +SYSTEM = linux +CORENUM = 7 +ENV = /d/jspc29/lattice/310_settings.sh +WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir + +[jspc57] +SYSTEM = linux +CORENUM = 3 +ENV = /d/jspc29/lattice/310_settings.sh +WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir diff --git a/or_logic_rj45/nodelist_hades68.txt b/or_logic_rj45/nodelist_hades68.txt new file mode 100644 index 0000000..a202e90 --- /dev/null +++ b/or_logic_rj45/nodelist_hades68.txt @@ -0,0 +1,7 @@ +// nodes file for parallel place&route + +[hades68] +SYSTEM = linux +CORENUM = 8 +ENV = /home/hheggen/bin/diamond_setup_x64.sh +WORKDIR = /home/hheggen/projects/trb_hdl/trb5sc/template/workdir diff --git a/or_logic_rj45/or_logic.vhd b/or_logic_rj45/or_logic.vhd new file mode 100644 index 0000000..ce72c14 --- /dev/null +++ b/or_logic_rj45/or_logic.vhd @@ -0,0 +1,154 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; +library work; +use work.trb_net_std.all; + +library machxo2; +use machxo2.all; + + +entity or_logic is + port ( + CLK : in std_logic; + SIG_IN : in std_logic_vector(11 downto 0); + SIG_OUT : out std_logic_vector(7 downto 0); + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); +end or_logic; + + +architecture RTL of or_logic is + + component FD1S3DX + port ( + CK : in std_logic; + CD : in std_logic; + D : in std_logic; + Q : out std_logic + ); + end component; + + + signal invert : std_logic_vector(31 downto 0) := x"00000000"; + signal enable : std_logic_vector(31 downto 0) := x"00000003"; + signal stretch : std_logic_vector(3 downto 0) := x"8"; + signal del_val : integer range 0 to 15; + + signal sig_i : std_logic_vector(11 downto 0); + signal cre : std_logic_vector(11 downto 0); + + type cff_fsm_state_t is array(0 to 11) of integer range 0 to 15; + signal cff_fsm_state : cff_fsm_state_t := (others => 0); + + type ctr_array is array(0 to 11) of integer range 0 to 31; + signal del_ctr : ctr_array := (others => 20); + + signal reset_creff : std_logic_vector(11 downto 0); + + +------------------------------------------------------------------------------- +begin -- BEGIN -- BEGIN -- BEGIN -- BEGIN -- BEGIN -- BEGIN -- +------------------------------------------------------------------------------- + + -- Input signal enable/disable and invert logic + sig_i <= (SIG_IN xor invert(11 downto 0)) and enable(11 downto 0); + + -- Generate output signals (OR of captured signals) + g_OR_OUT : for i in 0 to 7 generate + SIG_OUT(i) <= or_all(cre); + end generate; + + -- Set length of stretched pulses (set via TRBnet) + del_val <= to_integer(unsigned(stretch)); + + -- Generate capture stages + g_CAPTURE_STAGES : for i in 0 to 11 generate + + -- Input signal rising edge capture flip-flop + -- Signal needs to be positive logic + CREFF : FD1S3DX + port map (CK => sig_i(i), + CD => reset_creff(i), + D => '1', + Q => cre(i)); + + CAPTURE_FSM : process(CLK) + begin + if rising_edge(CLK) then + case cff_fsm_state(i) is + -- Wait for rising edge of input signal + when 0 => + reset_creff(i) <= '0'; + del_ctr(i) <= del_val; + if cre(i) = '1' then + cff_fsm_state(i) <= cff_fsm_state(i) + 1; + else + cff_fsm_state(i) <= cff_fsm_state(i); + end if; + -- Synchronous delay after rising edge (defines pulse width) + when 1 => + reset_creff(i) <= '0'; + if del_ctr(i) > 0 then + del_ctr(i) <= del_ctr(i) - 1; + cff_fsm_state(i) <= cff_fsm_state(i); + else + cff_fsm_state(i) <= cff_fsm_state(i) + 1; + end if; + -- Reset capture flip-flop + when 2 => + reset_creff(i) <= '1'; + del_ctr(i) <= del_ctr(i); + cff_fsm_state(i) <= 0; + -- Catch erronous states + when others => + reset_creff(i) <= '1'; + del_ctr(i) <= del_val; + cff_fsm_state(i) <= 0; + end case; + end if; + end process; + + end generate; + + + -- TRBnet + proc_trb_net : process + begin + wait until rising_edge(CLK); + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.unknown <= '0'; + + if BUS_RX.write = '1' then + BUS_TX.ack <= '1'; + case BUS_RX.addr(1 downto 0) is + when "00" => + stretch <= BUS_RX.data(3 downto 0); + when "01" => + invert <= BUS_RX.data; + when "10" => + enable <= BUS_RX.data; + + when others => + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + end case; + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + case BUS_RX.addr(1 downto 0) is + when "00" => BUS_TX.data(3 downto 0) <= stretch; + + when "01" => BUS_TX.data <= invert; + + when "10" => BUS_TX.data <= enable; + + when others => BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + end case; + end if; + end process; + +end RTL; diff --git a/or_logic_rj45/par.p2t b/or_logic_rj45/par.p2t new file mode 100644 index 0000000..e168739 --- /dev/null +++ b/or_logic_rj45/par.p2t @@ -0,0 +1,69 @@ +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 11 +-c 2 +-e 2 +-i 10 +#-exp parPlcInLimit=0 +#-exp parPlcInNeighborSize=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 diff --git a/or_logic_rj45/tdc_release b/or_logic_rj45/tdc_release new file mode 120000 index 0000000..887cdbb --- /dev/null +++ b/or_logic_rj45/tdc_release @@ -0,0 +1 @@ +../../tdc/releases/tdc_v2.3/ \ No newline at end of file diff --git a/or_logic_rj45/trb5sc_or_logic_rj45.lpf b/or_logic_rj45/trb5sc_or_logic_rj45.lpf new file mode 100644 index 0000000..5ad9471 --- /dev/null +++ b/or_logic_rj45/trb5sc_or_logic_rj45.lpf @@ -0,0 +1,43 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK_200 200 MHz; +FREQUENCY PORT CLK_125 125 MHz; +FREQUENCY PORT CLK_EXT 200 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +# FREQUENCY NET "med_stat_debug[11]" 200 MHz; + +FREQUENCY NET "med2int_0.clk_full" 200 MHz; +# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz; + + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; + + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + diff --git a/or_logic_rj45/trb5sc_or_logic_rj45.prj b/or_logic_rj45/trb5sc_or_logic_rj45.prj new file mode 100644 index 0000000..e6964ef --- /dev/null +++ b/or_logic_rj45/trb5sc_or_logic_rj45.prj @@ -0,0 +1,247 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG756C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb5sc_or_logic_rj45" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb5sc_or_logic_rj45.edf" +set_option log_file "workdir/trb5sc_project.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "tdc_release/tdc_version.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" + +#channel 1, SFP +#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +########################################## + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +########################################## + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + + +add_file -vhdl -lib work "tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd" +add_file -vhdl -lib work "tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "tdc_release/Channel.vhd" +add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd" +add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "tdc_release/Readout_record.vhd" +add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd" +add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "tdc_release/TDC_record.vhd" +add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "tdc_release/up_counter.vhd" + +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" + +add_file -vhdl -lib work "./trb5sc_or_logic_rj45.vhd" +add_file -vhdl -lib work "./or_logic.vhd" + +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/or_logic_rj45/trb5sc_or_logic_rj45.vhd b/or_logic_rj45/trb5sc_or_logic_rj45.vhd new file mode 100644 index 0000000..8e2d4b8 --- /dev/null +++ b/or_logic_rj45/trb5sc_or_logic_rj45.vhd @@ -0,0 +1,453 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity trb5sc_or_logic_rj45 is + port( + CLK_200 : in std_logic; + CLK_125 : in std_logic; + CLK_EXT : in std_logic; + + TRIG_IN_BACKPL : in std_logic; --Reference Time + TRIG_IN_RJ45 : in std_logic; --Reference Time + IN_SELECT_EXT_CLOCK : in std_logic; + + SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3 + BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1 + + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_MOD_0 : in std_logic; + + --AddOn + --FE_GPIO : inout std_logic_vector(11 downto 0); + --FE_CLK : out std_logic_vector( 2 downto 1); + --FE_DIFF : inout std_logic_vector(63 downto 0); + --INP : inout std_logic_vector(63 downto 0); + FE_DIFF_IN : in std_logic_vector(11 downto 0); + FE_DIFF_OUT : out std_logic_vector(7 downto 0); + + CS : out std_logic_vector(4 downto 1); + MISO : in std_logic_vector(4 downto 1); + MOSI : out std_logic; + SCK : out std_logic; + + --ADC + ADC_SCLK : out std_logic; + ADC_NCS : out std_logic; + ADC_MOSI : out std_logic; + ADC_MISO : in std_logic; + --Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + PROGRAMN : out std_logic; + --I2C + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + TMP_ALERT : in std_logic; + + --LED + LED : out std_logic_vector(8 downto 1); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector(1 downto 0); + LED_RJ_RED : out std_logic_vector(1 downto 0); + LED_EXT_CLOCK : out std_logic; + + --Other Connectors + TEST : inout std_logic_vector(14 downto 1); + HDR_IO : inout std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + + +end entity; + +architecture arch of trb5sc_or_logic_rj45 is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; + + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busor_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busor_rx : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal clock_select : std_logic; + signal bus_master_active : std_logic; + signal flash_ncs_i : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal header_io_i : std_logic_vector(10 downto 1); + signal timer : TIMERS; + signal led_off : std_logic; + --TDC + signal hit_in_i : std_logic_vector(NUM_TDC_CHANNELS-1 downto 1); + signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); + signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0); + + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal link_stat_in_reg : std_logic; + + + +begin + + trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK); + + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + + DEBUG_OUT => debug_clock_reset + ); + + + + THE_CAL_PLL : entity work.pll_in125_out50 + port map( + CLKI => CLK_125, + CLKOP => clk_cal + ); + +--------------------------------------------------------------------------- +-- TrbNet Uplink +--------------------------------------------------------------------------- + + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + gen_sfp_con : if SERDES_NUM = 1 generate + sfp_los_i <= SFP_LOS; + sfp_prsnt_i <= SFP_MOD_0; + SFP_TX_DIS <= sfp_txdis_i; + end generate; + gen_bpl_con : if SERDES_NUM = 0 generate + sfp_los_i <= BACK_GPIO(1); + sfp_prsnt_i <= BACK_GPIO(1); + BACK_GPIO(0) <= sfp_txdis_i; + end generate; + + +--------------------------------------------------------------------------- +-- Endpoint +--------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_USE_1WIRE_INTERFACE => c_I2C, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, + + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + + ONEWIRE_INOUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + --Timing registers + TIMERS_OUT => timer + ); + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + + + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", 4 => x"e000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 2, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => bustdc_rx, + BUS_RX(4) => busor_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => bustdc_tx, + BUS_TX(4) => busor_tx, + + STAT_DEBUG => open + ); + + +--------------------------------------------------------------------------- +-- OR logic +--------------------------------------------------------------------------- + or_logic_1 : entity work.or_logic + port map ( + CLK => clk_sys, + SIG_IN => FE_DIFF_IN, + SIG_OUT => FE_DIFF_OUT, + BUS_RX => busor_rx, + BUS_TX => busor_tx + ); + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => HDR_IO(9 downto 0), + ADDITIONAL_REG(0) => led_off, + --LCD + LCD_DATA_IN => (others => '0'), + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => monitor_inputs_i, + TRIG_GEN_INPUTS => trigger_inputs_i, + TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), + TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + +--------------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------------- + + CS <= spi_cs(3 downto 0); + spi_miso(3 downto 0) <= MISO; + + MOSI <= spi_mosi(0) when spi_cs(0) = '0' + else spi_mosi(1) when spi_cs(1) = '0' + else spi_mosi(2) when spi_cs(2) = '0' + else spi_mosi(3) when spi_cs(3) = '0' + else '0'; + + SCK <= spi_clk(0) when spi_cs(0) = '0' + else spi_clk(1) when spi_cs(1) = '0' + else spi_clk(2) when spi_cs(2) = '0' + else spi_clk(3) when spi_cs(3) = '0' + else '1'; + + + monitor_inputs_i <= FE_DIFF_IN(MONITOR_INPUT_NUM-1 downto 0); + trigger_inputs_i <= FE_DIFF_IN(TRIG_GEN_INPUT_NUM-1 downto 0); + hit_in_i <= FE_DIFF_IN(NUM_TDC_CHANNELS-2 downto 0); + + assert DOUBLE_EDGE_TYPE /= 2 report "double edge in separate channels: connections missing" severity error; + + HDR_IO(15 downto 10) <= (others => '0'); + TEST(13 downto 1) <= (others => '0'); + TEST(14) <= flash_ncs_i; + FLASH_NCS <= flash_ncs_i; + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + + LED_SFP_GREEN <= not med2int(0).stat_op(9) or led_off; + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; + LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off; + LED <= x"AA"; + LED_RJ_GREEN <= "00"; + LED_RJ_RED <= "11"; + LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_NO, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => clk_full, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => trigger_in_i, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => readout_rx, + BUSRDO_TX => readout_tx(0), + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => open + ); + + +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; + +end architecture; + + + diff --git a/pinout/trb5sc_rj45.lpf b/pinout/trb5sc_rj45.lpf new file mode 100644 index 0000000..f61605b --- /dev/null +++ b/pinout/trb5sc_rj45.lpf @@ -0,0 +1,314 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; + +SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON +BANK 0 VCCIO 2.5 V; +BANK 1 VCCIO 2.5 V; +BANK 2 VCCIO 2.5 V; +BANK 3 VCCIO 2.5 V; +BANK 4 VCCIO 3.3 V; +BANK 6 VCCIO 2.5 V; +BANK 7 VCCIO 2.5 V; +BANK 8 VCCIO 3.3 V; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_125" SITE "AD1"; #was "OSC_CORE_125" +LOCATE COMP "CLK_200" SITE "AD32"; #was "OSC_CORE_200" +LOCATE COMP "CLK_EXT" SITE "C28"; #was "EXT_CLOCK" +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100; + + +# LOCATE COMP "ENPIRION_CLOCK" SITE "AM31"; +# IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVTTL33; + +################################################################# +# Trigger I/O +################################################################# +LOCATE COMP "TRIG_IN_BACKPL" SITE "AD3"; +LOCATE COMP "TRIG_IN_RJ45" SITE "AC2"; +DEFINE PORT GROUP "TRIG_IN_group" "TRIG_IN*" ; +IOBUF GROUP "TRIG_IN_group" IO_TYPE=LVDS DIFFRESISTOR=100; + + +LOCATE COMP "SPARE_0" SITE "AC3"; +LOCATE COMP "SPARE_1" SITE "AB1"; +DEFINE PORT GROUP "SPARE_group" "SPARE*" ; +IOBUF GROUP "SPARE_group" IO_TYPE=LVDS ; + +################################################################# +# SFP +################################################################# +LOCATE COMP "SFP_TX_DIS" SITE "AH28"; +LOCATE COMP "SFP_LOS" SITE "AK29"; +LOCATE COMP "SFP_MOD_0" SITE "AG28"; +IOBUF PORT "SFP_TX_DIS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_MOD_0" IO_TYPE=LVTTL33 PULLMODE=NONE ; + +# LOCATE COMP "SFP_RATE_SEL" SITE "AG30"; +# LOCATE COMP "SFP_TX_FAULT" SITE "AH30"; +# LOCATE COMP "SFP_MOD_1" SITE "AG29"; +# LOCATE COMP "SFP_MOD_2" SITE "AJ28"; + + +################################################################# +# Frontend +################################################################# +LOCATE COMP "CS_1" SITE "A18"; #"FE_GPIO_0" +LOCATE COMP "CS_2" SITE "C18"; #"FE_GPIO_1" +LOCATE COMP "MISO_1" SITE "D18"; #"FE_GPIO_2" +LOCATE COMP "MISO_2" SITE "F18"; #"FE_GPIO_3" +LOCATE COMP "CS_3" SITE "A19"; #"FE_GPIO_4" +LOCATE COMP "CS_4" SITE "B19"; #"FE_GPIO_5" +LOCATE COMP "MISO_3" SITE "C19"; #"FE_GPIO_6" +LOCATE COMP "MISO_4" SITE "D19"; #"FE_GPIO_7" +DEFINE PORT GROUP "MISO_group" "MISO*" ; +IOBUF GROUP "MISO_group" IO_TYPE=LVTTL33; +DEFINE PORT GROUP "CS_group" "CS*" ; +IOBUF GROUP "CS_group" IO_TYPE=LVCMOS25; + + +LOCATE COMP "SFP_ADD_LOS" SITE "E19"; #"FE_GPIO_8" +LOCATE COMP "SFP_ADD_MOD0" SITE "F19"; #"FE_GPIO_9" +LOCATE COMP "SFP_ADD_TX_DIS" SITE "A20"; #"FE_GPIO_10" +LOCATE COMP "SFP_ADD_LED" SITE "C20"; #"FE_GPIO_11" +IOBUF PORT "SFP_ADD_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_ADD_TX_DIS" IO_TYPE=LVCMOS25 ; +IOBUF PORT "SFP_ADD_MOD0" IO_TYPE=LVTTL33 PULLMODE=NONE ; +IOBUF PORT "SFP_ADD_LED" IO_TYPE=LVCMOS25 ; + +# DEFINE PORT GROUP "FE_GPIO_group" "FE_GPIO*" ; +# IOBUF GROUP "FE_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +LOCATE COMP "SCK" SITE "C5";#"FE_CLK_1" +LOCATE COMP "MOSI" SITE "P5";#"FE_CLK_2" +IOBUF PORT "SCK" IO_TYPE=LVDS ; +IOBUF PORT "MOSI" IO_TYPE=LVDS ; + +# DEFINE PORT GROUP "FE_CLK_group" "FE_CLK*" ; +# IOBUF GROUP "FE_CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100; + +#LOCATE COMP "FE_DIFF[0]" SITE "R29"; #"FE_DIFF[0]" +#LOCATE COMP "FE_DIFF[1]" SITE "T29"; #"FE_DIFF[1]" +#LOCATE COMP "FE_DIFF[2]" SITE "P31"; #"FE_DIFF[2]" +#LOCATE COMP "FE_DIFF[3]" SITE "R30"; #"FE_DIFF[3]" +#LOCATE COMP "FE_DIFF[4]" SITE "N32"; #"FE_DIFF[4]" +#LOCATE COMP "FE_DIFF[5]" SITE "U31"; #"FE_DIFF[5]" +#LOCATE COMP "FE_DIFF[6]" SITE "R32"; #"FE_DIFF[6]" +#LOCATE COMP "FE_DIFF[7]" SITE "W30"; #"FE_DIFF[7]" +#LOCATE COMP "FE_DIFF[8]" SITE "T32"; #"FE_DIFF[8]" +#LOCATE COMP "FE_DIFF[9]" SITE "V32"; #"FE_DIFF[9]" +#LOCATE COMP "FE_DIFF[10]" SITE "Y26"; #"FE_DIFF[10]" +#LOCATE COMP "FE_DIFF[11]" SITE "Y28"; #"FE_DIFF[11]" +#LOCATE COMP "FE_DIFF[12]" SITE "Y29"; #"FE_DIFF[12]" +#LOCATE COMP "FE_DIFF[13]" SITE "AB26"; #"FE_DIFF[13]" +#LOCATE COMP "FE_DIFF[14]" SITE "AB28"; #"FE_DIFF[14]" +#LOCATE COMP "FE_DIFF[15]" SITE "AC26"; #"FE_DIFF[15]" +#LOCATE COMP "FE_DIFF[16]" SITE "D29"; #"FE_DIFF[16]" +#LOCATE COMP "FE_DIFF[17]" SITE "F29"; #"FE_DIFF[17]" +#LOCATE COMP "FE_DIFF[18]" SITE "B32"; #"FE_DIFF[18]" +#LOCATE COMP "FE_DIFF[19]" SITE "D30"; #"FE_DIFF[19]" +#LOCATE COMP "FE_DIFF[20]" SITE "F30"; #"FE_DIFF[20]" +#LOCATE COMP "FE_DIFF[21]" SITE "C32"; #"FE_DIFF[21]" +#LOCATE COMP "FE_DIFF[22]" SITE "F31"; #"FE_DIFF[22]" +#LOCATE COMP "FE_DIFF[23]" SITE "F32"; #"FE_DIFF[23]" +#LOCATE COMP "FE_DIFF[24]" SITE "H31"; #"FE_DIFF[24]" +#LOCATE COMP "FE_DIFF[25]" SITE "J30"; #"FE_DIFF[25]" +#LOCATE COMP "FE_DIFF[26]" SITE "K31"; #"FE_DIFF[26]" +#LOCATE COMP "FE_DIFF[27]" SITE "K32"; #"FE_DIFF[27]" +#LOCATE COMP "FE_DIFF[28]" SITE "L31"; #"FE_DIFF[28]" +#LOCATE COMP "FE_DIFF[29]" SITE "J29"; #"FE_DIFF[29]" +#LOCATE COMP "FE_DIFF[30]" SITE "H27"; #"FE_DIFF[30]" +#LOCATE COMP "FE_DIFF[31]" SITE "K27"; #"FE_DIFF[31]" +#LOCATE COMP "FE_DIFF[32]" SITE "D4"; #"FE_DIFF[32]" +#LOCATE COMP "FE_DIFF[33]" SITE "F4"; #"FE_DIFF[33]" +#LOCATE COMP "FE_DIFF[34]" SITE "B1"; #"FE_DIFF[34]" +#LOCATE COMP "FE_DIFF[35]" SITE "D3"; #"FE_DIFF[35]" +#LOCATE COMP "FE_DIFF[36]" SITE "F3"; #"FE_DIFF[36]" +#LOCATE COMP "FE_DIFF[37]" SITE "C1"; #"FE_DIFF[37]" +#LOCATE COMP "FE_DIFF[38]" SITE "F2"; #"FE_DIFF[38]" +#LOCATE COMP "FE_DIFF[39]" SITE "F1"; #"FE_DIFF[39]" +#LOCATE COMP "FE_DIFF[40]" SITE "H2"; #"FE_DIFF[40]" +#LOCATE COMP "FE_DIFF[41]" SITE "J3"; #"FE_DIFF[41]" +#LOCATE COMP "FE_DIFF[42]" SITE "K2"; #"FE_DIFF[42]" +#LOCATE COMP "FE_DIFF[43]" SITE "K1"; #"FE_DIFF[43]" +#LOCATE COMP "FE_DIFF[44]" SITE "L2"; #"FE_DIFF[44]" +#LOCATE COMP "FE_DIFF[45]" SITE "J4"; #"FE_DIFF[45]" +#LOCATE COMP "FE_DIFF[46]" SITE "H6"; #"FE_DIFF[46]" +#LOCATE COMP "FE_DIFF[47]" SITE "K6"; #"FE_DIFF[47]" +#LOCATE COMP "FE_DIFF[48]" SITE "R4"; #"FE_DIFF[48]" +#LOCATE COMP "FE_DIFF[49]" SITE "T4"; #"FE_DIFF[49]" +#LOCATE COMP "FE_DIFF[50]" SITE "P2"; #"FE_DIFF[50]" +#LOCATE COMP "FE_DIFF[51]" SITE "R3"; #"FE_DIFF[51]" +#LOCATE COMP "FE_DIFF[52]" SITE "N1"; #"FE_DIFF[52]" +#LOCATE COMP "FE_DIFF[53]" SITE "U2"; #"FE_DIFF[53]" +#LOCATE COMP "FE_DIFF[54]" SITE "R1"; #"FE_DIFF[54]" +#LOCATE COMP "FE_DIFF[55]" SITE "W3"; #"FE_DIFF[55]" +#LOCATE COMP "FE_DIFF[56]" SITE "T1"; #"FE_DIFF[56]" +#LOCATE COMP "FE_DIFF[57]" SITE "V1"; #"FE_DIFF[57]" +#LOCATE COMP "FE_DIFF[58]" SITE "Y7"; #"FE_DIFF[58]" +#LOCATE COMP "FE_DIFF[59]" SITE "Y5"; #"FE_DIFF[59]" +#LOCATE COMP "FE_DIFF[60]" SITE "Y4"; #"FE_DIFF[60]" +#LOCATE COMP "FE_DIFF[61]" SITE "AB7"; #"FE_DIFF[61]" +#LOCATE COMP "FE_DIFF[62]" SITE "AB5"; #"FE_DIFF[62]" +#LOCATE COMP "FE_DIFF[63]" SITE "AC7"; #"FE_DIFF[63]" + +LOCATE COMP "FE_DIFF_IN[0]" SITE "F31"; #"FE_DIFF[22]" +LOCATE COMP "FE_DIFF_IN[1]" SITE "H27"; #"FE_DIFF[30]" +LOCATE COMP "FE_DIFF_IN[2]" SITE "F2"; #"FE_DIFF[38]" +LOCATE COMP "FE_DIFF_IN[3]" SITE "H6"; #"FE_DIFF[46]" +LOCATE COMP "FE_DIFF_IN[4]" SITE "R1"; #"FE_DIFF[54]" +LOCATE COMP "FE_DIFF_IN[5]" SITE "AB5"; #"FE_DIFF[62]" +LOCATE COMP "FE_DIFF_IN[6]" SITE "D29"; #"FE_DIFF[16]" +LOCATE COMP "FE_DIFF_IN[7]" SITE "H31"; #"FE_DIFF[24]" +LOCATE COMP "FE_DIFF_IN[8]" SITE "D4"; #"FE_DIFF[32]" +LOCATE COMP "FE_DIFF_IN[9]" SITE "H2"; #"FE_DIFF[40]" +LOCATE COMP "FE_DIFF_IN[10]" SITE "R4"; #"FE_DIFF[48]" +LOCATE COMP "FE_DIFF_IN[11]" SITE "T1"; #"FE_DIFF[56]" + +DEFINE PORT GROUP "FE_DIFF_IN_group" "FE_DIFF_IN*" ; +IOBUF GROUP "FE_DIFF_IN_group" IO_TYPE=LVDS DIFFRESISTOR=100; + + +LOCATE COMP "FE_DIFF_OUT[0]" SITE "R29"; #"FE_DIFF[0]" - J11 +LOCATE COMP "FE_DIFF_OUT[1]" SITE "P31"; #"FE_DIFF[2]" - J11 +LOCATE COMP "FE_DIFF_OUT[2]" SITE "N32"; #"FE_DIFF[4]" - J11 +LOCATE COMP "FE_DIFF_OUT[3]" SITE "R32"; #"FE_DIFF[6]" - J11 +LOCATE COMP "FE_DIFF_OUT[4]" SITE "T32"; #"FE_DIFF[8]" - J12 +LOCATE COMP "FE_DIFF_OUT[5]" SITE "Y26"; #"FE_DIFF[10]" - J12 +LOCATE COMP "FE_DIFF_OUT[6]" SITE "Y29"; #"FE_DIFF[12]" - J12 +LOCATE COMP "FE_DIFF_OUT[7]" SITE "AB28"; #"FE_DIFF[14]" - J12 + +DEFINE PORT GROUP "FE_DIFF_OUT_group" "FE_DIFF_OUT*"; +IOBUF GROUP "FE_DIFF_OUT_group" IO_TYPE=LVDS; + + +################################################################# +# Temperature, Flash & ID +################################################################# +LOCATE COMP "I2C_SDA" SITE "A11"; +LOCATE COMP "I2C_SCL" SITE "B11"; +LOCATE COMP "TMP_ALERT" SITE "C11"; +IOBUF PORT "I2C_SDA" IO_TYPE=LVCMOS25 ; +IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS25 ; +IOBUF PORT "TMP_ALERT" IO_TYPE=LVCMOS25 ; + + +LOCATE COMP "PROGRAMN" SITE "AH1"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + +LOCATE COMP "IN_SELECT_EXT_CLOCK" SITE "A16"; +IOBUF PORT "IN_SELECT_EXT_CLOCK" IO_TYPE=LVCMOS25 ; + + +LOCATE COMP "FLASH_HOLD" SITE "AL1"; +LOCATE COMP "FLASH_MISO" SITE "AJ2"; +LOCATE COMP "FLASH_MOSI" SITE "AK2"; +LOCATE COMP "FLASH_NCS" SITE "AJ3"; +LOCATE COMP "FLASH_SCLK" SITE "AJ1"; +LOCATE COMP "FLASH_WP" SITE "AM2"; +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; + + +LOCATE COMP "ADC_MISO" SITE "AK3"; +LOCATE COMP "ADC_MOSI" SITE "AL3"; +LOCATE COMP "ADC_NCS" SITE "AH3"; +LOCATE COMP "ADC_SCLK" SITE "AG3"; +IOBUF PORT "ADC_SCLK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_NCS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_MOSI" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_MISO" IO_TYPE=LVTTL33 PULLMODE=UP ; + + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_SFP_YELLOW" SITE "AG32"; +LOCATE COMP "LED_SFP_GREEN" SITE "AK30"; +LOCATE COMP "LED_SFP_RED" SITE "AH32"; +DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ; +IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ; + +LOCATE COMP "LED_1" SITE "A26"; +LOCATE COMP "LED_2" SITE "B26"; +LOCATE COMP "LED_3" SITE "A28"; +LOCATE COMP "LED_4" SITE "A29"; +LOCATE COMP "LED_5" SITE "A30"; +LOCATE COMP "LED_6" SITE "A31"; +LOCATE COMP "LED_7" SITE "B29"; +LOCATE COMP "LED_8" SITE "B30"; +IOBUF PORT "LED_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_2" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_3" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_4" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_5" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_6" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_7" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_8" IO_TYPE=LVCMOS25 ; + + +LOCATE COMP "LED_RJ_GREEN_0" SITE "AK32"; +LOCATE COMP "LED_RJ_RED_0" SITE "AJ32"; +LOCATE COMP "LED_EXT_CLOCK" SITE "AJ30"; +LOCATE COMP "LED_RJ_GREEN_1" SITE "AM30"; +LOCATE COMP "LED_RJ_RED_1" SITE "AL30"; +IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_EXT_CLOCK" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVTTL33 ; +IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVTTL33 ; + +################################################################# +# Test & Other IO +################################################################# +LOCATE COMP "TEST_1" SITE "A7"; +LOCATE COMP "TEST_2" SITE "A5"; +LOCATE COMP "TEST_3" SITE "A4"; +LOCATE COMP "TEST_4" SITE "A3"; +LOCATE COMP "TEST_5" SITE "A2"; +LOCATE COMP "TEST_6" SITE "B3"; +LOCATE COMP "TEST_7" SITE "B4"; +LOCATE COMP "TEST_8" SITE "B7"; +LOCATE COMP "TEST_9" SITE "C7"; +LOCATE COMP "TEST_10" SITE "C8"; +LOCATE COMP "TEST_11" SITE "D7"; +LOCATE COMP "TEST_12" SITE "D8"; +LOCATE COMP "TEST_13" SITE "E8"; +LOCATE COMP "TEST_14" SITE "F8"; +DEFINE PORT GROUP "TEST_group" "TEST*" ; +IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 DRIVE=8; + + +LOCATE COMP "HDR_IO_0" SITE "A23"; +LOCATE COMP "HDR_IO_1" SITE "A22"; +LOCATE COMP "HDR_IO_2" SITE "B22"; +LOCATE COMP "HDR_IO_3" SITE "A24"; +LOCATE COMP "HDR_IO_4" SITE "C23"; +LOCATE COMP "HDR_IO_5" SITE "B23"; +LOCATE COMP "HDR_IO_6" SITE "C22"; +LOCATE COMP "HDR_IO_7" SITE "C24"; +LOCATE COMP "HDR_IO_8" SITE "D23"; +LOCATE COMP "HDR_IO_9" SITE "D24"; +LOCATE COMP "HDR_IO_10" SITE "E23"; +LOCATE COMP "HDR_IO_11" SITE "D22"; +LOCATE COMP "HDR_IO_12" SITE "F23"; +LOCATE COMP "HDR_IO_13" SITE "E22"; +LOCATE COMP "HDR_IO_14" SITE "F20"; +LOCATE COMP "HDR_IO_15" SITE "F22"; +DEFINE PORT GROUP "HDR_group" "HDR*" ; +IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + + +LOCATE COMP "BACK_GPIO_0" SITE "P28"; +LOCATE COMP "BACK_GPIO_1" SITE "P29"; +LOCATE COMP "BACK_GPIO_2" SITE "R27"; +LOCATE COMP "BACK_GPIO_3" SITE "T27"; +DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ; +IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; diff --git a/template/README b/template/README index ce23de4..eb6db9c 100644 --- a/template/README +++ b/template/README @@ -1,4 +1,7 @@ -The tdc branch has to be -sep17 +The tdc repository branch has to be set to sep17. + +Run $ git checkout sep17 + +in tdc repository folder. diff --git a/template/config_compile_gsi.pl b/template/config_compile_gsi.pl index 94d1fcf..f8c1cf8 100644 --- a/template/config_compile_gsi.pl +++ b/template/config_compile_gsi.pl @@ -3,25 +3,19 @@ Devicename => 'LFE5UM-85F', Package => 'CABGA756', Speedgrade => '8', - TOPNAME => "trb5sc_template", -lm_license_file_for_synplify => "27000\@lxcad03.gsi.de:27000\@lxcad04.gsi.de", -#lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", +lm_license_file_for_synplify => "27000\@lxcad04.gsi.de", lm_license_file_for_par => "1702\@hadeb05.gsi.de", lattice_path => '/opt/lattice/diamond/3.12', -synplify_path => '/opt/synplicity/R-2020.09-SP1/',#K-2015.09', -synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier_dp", +synplify_path => '/opt/synplicity/P-2019.09-SP1', #synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options", -#synplify_path => '',#K-2015.09', -#synplify_command => "/opt/lattice/diamond/3.12/bin/lin64/synpwrap -fg -options", +#synplify_command => "/opt/synplicity/P-2019.09-SP1/bin/synplify_premier_dp", +synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier_dp", -nodelist_file => 'nodes_gsi_template.txt', +nodelist_file => "../nodelist_hades68.txt", pinout_file => 'trb5sc_tdc', par_options => '../par.p2t', - - -#pinout_file => 'trb3sc_richSensor', - + #Include only necessary lpf files include_TDC => 1, include_GBE => 0, @@ -30,4 +24,3 @@ include_GBE => 0, firefox_open => 0, twr_number_of_errors => 20, no_ltxt2ptxt => 1, #if there is no serdes being used -