From: Manuel Penschuck Date: Wed, 4 Jun 2014 15:43:27 +0000 (+0200) Subject: Changes before adopting to new CBMNet version X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c17cbcbea81a717bfd44c1d2300ed6142d326fb5;p=trb3.git Changes before adopting to new CBMNet version --- diff --git a/cbmnet/code/cbmnet_phy_ecp3.vhd b/cbmnet/code/cbmnet_phy_ecp3.vhd index 6e1b699..346ea87 100755 --- a/cbmnet/code/cbmnet_phy_ecp3.vhd +++ b/cbmnet/code/cbmnet_phy_ecp3.vhd @@ -165,8 +165,8 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal tx_gear_allow_relock_i : std_logic; - signal rx_gear_debug_i : std_logic_vector(31 downto 0) := (others => '0'); - signal tx_gear_debug_i : std_logic_vector(31 downto 0) := (others => '0'); + signal rx_gear_debug_i : std_logic_vector(31 downto 0); + signal tx_gear_debug_i : std_logic_vector(31 downto 0); -- CBMNet Ready Managers signal rm_rx_ready_i : std_logic; @@ -198,7 +198,9 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal low_level_rx_see_dlm0 : std_logic; signal low_level_tx_see_dlm0 : std_logic; - signal low_level_tx_see_dlm0_125 : std_logic; + signal low_level_tx_see_dlm0_125 : std_logic; + + signal stat_dlm_counter_i : unsigned(15 downto 0); begin clk_125_local <= CLK; CLK_RX_HALF_OUT <= rclk_125_i when IS_SYNC_SLAVE = c_YES or 1=1 else clk_tx_half_i; @@ -664,7 +666,17 @@ begin if tx_data_i = "10" & x"fb6a" then low_level_tx_see_dlm0_125 <= '1'; end if; - end process; + end process; + + PROC_SENSE_DLMS: process begin + wait until rising_edge(clk_125_i); + + if serdes_ready_i = '0' then + stat_dlm_counter_i <= (others => '0'); + elsif rx_data_i(17) = '1' and rx_data_i(15 downto 8) = K277 then + stat_dlm_counter_i <= stat_dlm_counter_i + TO_UNSIGNED(1,1); + end if; + end process; -- DEBUG_OUT_BEGIN DEBUG_OUT(19 downto 0) <= "00" & tx_data_i(17 downto 0); @@ -690,7 +702,8 @@ begin DEBUG_OUT(147 downto 128) <= "00" & rx_data_debug_i(17 downto 0) when rising_edge(clk_125_local); DEBUG_OUT(179 downto 148) <= stat_last_reconnect_duration_i(31 downto 0); DEBUG_OUT(195 downto 180) <= stat_reconnect_counter_i(15 downto 0); - DEBUG_OUT(211 downto 196) <= stat_wa_int_i(15 downto 0); + DEBUG_OUT(211 downto 196) <= stat_wa_int_i(15 downto 0); + DEBUG_OUT(227 downto 212) <= stat_dlm_counter_i(15 downto 0); --DEBUG_OUT(255 downto 170) <= (others => '0'); -- DEBUG_OUT_END diff --git a/cbmnet/code/cbmnet_phy_rx_gear.vhd b/cbmnet/code/cbmnet_phy_rx_gear.vhd index 7c9d848..92dd294 100644 --- a/cbmnet/code/cbmnet_phy_rx_gear.vhd +++ b/cbmnet/code/cbmnet_phy_rx_gear.vhd @@ -36,8 +36,8 @@ architecture CBMNET_PHY_RX_GEAR_ARCH of CBMNET_PHY_RX_GEAR is signal fsm_i : FSM_STATES_T; signal fsm_state_i : std_logic_vector(3 downto 0); - signal delay_clock_i : std_logic; - + signal delay_clock_i : std_logic; + signal indi_alignment_i : std_logic; signal indi_misalignment_i : std_logic; @@ -47,7 +47,17 @@ architecture CBMNET_PHY_RX_GEAR_ARCH of CBMNET_PHY_RX_GEAR is signal reset_timer_i : std_logic; signal timeout_i : std_logic; + + signal data_in_buf_i : std_logic_vector( 8 downto 0); + + + signal delay_clock_buf_i : std_logic; + signal delay_clock_buf1_i : std_logic; + signal last_delay_clock_i : std_logic := '0'; + signal word_idx_i : std_logic := '0'; begin + data_in_buf_i <= DATA_IN when rising_edge(CLK_250_IN); + -- FSM sync part process is begin wait until rising_edge(clk_125_i); @@ -133,27 +143,36 @@ begin timeout_i <= timer_v(idx); end process; --- Implement the 2:1 gearing and clock down-sampling - proc_gear: process is - variable last_delay_clock_v : std_logic := '0'; - variable word_idx_v : std_logic := '0'; +-- Implement the 2:1 gearing and clock down-sampling + delay_clock_buf1_i <= delay_clock_i when rising_edge(CLK_250_IN); + delay_clock_buf_i <= delay_clock_buf1_i when rising_edge(CLK_250_IN); + + proc_ctrl_gear: process + begin + wait until rising_edge(CLK_250_IN); + + if not (delay_clock_buf_i = '1' and last_delay_clock_i = '0') then + word_idx_i <= not word_idx_i; + end if; + + last_delay_clock_i <= delay_clock_buf_i; + end process; + + proc_gear: process begin wait until rising_edge(CLK_250_IN); - if word_idx_v = '0' then - data_delay_i <= DATA_IN; + if word_idx_i = '0' then + data_delay_i <= data_in_buf_i; clk_125_i <= '0'; else - data_out_buf_i <= data_delay_i(8) & DATA_IN(8) & data_delay_i(7 downto 0) & DATA_IN(7 downto 0); + data_out_buf_i <= data_delay_i(8) & data_in_buf_i(8) & data_delay_i(7 downto 0) & data_in_buf_i(7 downto 0); clk_125_i <= '1'; end if; - if not (delay_clock_i = '1' and last_delay_clock_v = '0') then - word_idx_v := not word_idx_v; - end if; - - last_delay_clock_v := delay_clock_i; - end process; + end process; + + DATA_OUT <= data_out_buf_i; CLK_125_OUT <= clk_125_i; diff --git a/cbmnet/compile_constraints.pl b/cbmnet/compile_constraints.pl new file mode 100755 index 0000000..276744b --- /dev/null +++ b/cbmnet/compile_constraints.pl @@ -0,0 +1,35 @@ +#!/usr/bin/perl +use warnings; +use strict; +use File::Basename; +use Cwd 'realpath'; + +my $TOPNAME = 'trb3_periph_cbmnet'; +my $workdir = './workdir'; + +my $script_dir = dirname(realpath(__FILE__)); +$workdir = $ARGV[0] if (@ARGV); + +die("workdir has to be relative to compile_constraints.pl") if $workdir =~ m/^\//; +die("workdir must not contain ..") if $workdir =~ m/\.\./; +$workdir =~ s/(\.\/|\/$)//g; # remove ./ and trailing slash +$workdir =~ s/\/{2,}/\//g; # remove multiple // in path + +my $back = "../" x ($workdir =~ tr/\///); +$back = './' unless $back; + +chdir($script_dir); + +unless(-e $workdir) { + print "Creating workdir\n"; + system ("mkdir $workdir"); +} + +chdir($workdir); +system ("$back/../../base/linkdesignfiles.sh '$back'"); +symlink "$back/../cores/cbmnet_sfp1.txt", 'cbmnet_sfp1.txt'; + +chdir($script_dir); + +system("cp ../base/$TOPNAME.lpf $workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> $workdir/$TOPNAME.lpf"); diff --git a/cbmnet/compile_periph_frankfurt.pl b/cbmnet/compile_periph_frankfurt.pl index a2a3248..d4b145c 100755 --- a/cbmnet/compile_periph_frankfurt.pl +++ b/cbmnet/compile_periph_frankfurt.pl @@ -7,34 +7,6 @@ use File::stat; use POSIX; - -my $build_master = 1; -my $build_slave = 1; - -my $mode = $ARGV[0]; -$mode = 's' unless defined $mode; - -$build_master = 0 if $mode eq 's'; -$build_slave = 0 if $mode eq 'm' or $mode eq 'w'; - -print "Will build:\n"; -print " -> Slave\n" if $build_slave; -print " -> Master\n" if $build_master; - -if ($build_master and $build_slave) { - if (fork()) { - system "xterm -geometry 200x25 -e './compile_periph_frankfurt.pl s;'"; - exit; - } - if (fork()) { - system "xterm -geometry 200x25 -e './compile_periph_frankfurt.pl m;'"; - exit; - } - wait; - exit (-e 'workdir_master/trb3_periph_cbmnet.bit') && (-e 'workdir_slave/trb3_periph_cbmnet.bit') ? 1 : 0; -} - - ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_cbmnet"; #Name of top-level entity @@ -51,29 +23,12 @@ my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/'; #my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/'; ################################################################################### -my $btype = ($build_slave ? 'slave' : 'master'); - +my $btype = 'slave'; -if (-e "../cbmnet_build_$btype/workdir/trb3_periph_cbmnet.bit") { - my $cd = stat("../cbmnet_build_$btype/workdir/trb3_periph_cbmnet.bit")->ctime; - system "mv ../cbmnet_build_$btype /tmp/cbmnet_build_" . $btype . "_" . POSIX::strftime("%Y%m%d_%H%M%S", localtime $cd); -} else { - system "rm -rf ../cbmnet_build_$btype"; -} - - -system "cp -ar . ../cbmnet_build_$btype"; -mkdir "../cbmnet_build_$btype/workdir"; -symlink "../cbmnet_build_$btype/workdir", "workdir_$btype"; -chdir "../cbmnet_build_$btype"; +system("./compile_constraints.pl"); symlink($CbmNetPath, 'cbmnet') unless (-e 'cbmnet'); -chdir "workdir"; -system '../../base/linkdesignfiles.sh'; -symlink '../cores/cbmnet_sfp1.txt', 'cbmnet_sfp1.txt'; -chdir '..'; - use FileHandle; $ENV{'SYNPLIFY'}=$synplify_path; @@ -87,8 +42,6 @@ my $PACKAGE="FPBGA672"; my $SPEEDGRADE="8"; #create full lpf file -system("cp $BasePath/$TOPNAME.lpf workdir/$TOPNAME.lpf"); -system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); #set -e #set -o errexit @@ -109,7 +62,7 @@ use ieee.numeric_std.all; package version is constant VERSION_NUMBER_TIME : integer := $t; - constant CBM_FEE_MODE_C : integer := $build_slave; + constant CBM_FEE_MODE_C : integer := 1; constant INCLUDE_TRBNET_C : integer := 1; end package version; @@ -156,8 +109,6 @@ execute($c); my $tpmap = $TOPNAME . "_map" ; -execute('env'); - $c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; execute($c); diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj index dfed18a..945c1f1 100644 --- a/cts/trb3_central.prj +++ b/cts/trb3_central.prj @@ -256,30 +256,30 @@ add_file -vhdl -lib work "source/cts.vhd" ############### # don't use vhd but link Adder_304.ngo to workdir! #add_file -vhdl -lib "work" "tdc_release/Adder_304.vhd" -add_file -vhdl -lib "work" "tdc_release/fallingEdgeDetect.vhd" -add_file -vhdl -lib "work" "tdc_release/bit_sync.vhd" -add_file -vhdl -lib "work" "tdc_release/BusHandler.vhd" -add_file -vhdl -lib "work" "tdc_release/Channel_200.vhd" -add_file -vhdl -lib "work" "tdc_release/Channel.vhd" -add_file -vhdl -lib "work" "tdc_release/hit_mux.vhd" -add_file -vhdl -lib "work" "tdc_release/Encoder_304_Bit.vhd" +#add_file -vhdl -lib "work" "tdc_release/fallingEdgeDetect.vhd" +#add_file -vhdl -lib "work" "tdc_release/bit_sync.vhd" +#add_file -vhdl -lib "work" "tdc_release/BusHandler.vhd" +#add_file -vhdl -lib "work" "tdc_release/Channel_200.vhd" +#add_file -vhdl -lib "work" "tdc_release/Channel.vhd" +#add_file -vhdl -lib "work" "tdc_release/hit_mux.vhd" +#add_file -vhdl -lib "work" "tdc_release/Encoder_304_Bit.vhd" #add_file -vhdl -lib "work" "tdc_release/FIFO_32x32_OutReg.vhd" -add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd" -add_file -vhdl -lib "work" "tdc_release/Readout.vhd" +#add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd" +#add_file -vhdl -lib "work" "tdc_release/Readout.vhd" #add_file -vhdl -lib "work" "tdc_release/Reference_Channel_200.vhd" #add_file -vhdl -lib "work" "tdc_release/Reference_Channel.vhd" -add_file -vhdl -lib "work" "tdc_release/ROM_encoder_3.vhd" -#add_file -vhdl -lib "work" "tdc_release/ROM_FIFO.vhd" -add_file -vhdl -lib "work" "tdc_release/ShiftRegisterSISO.vhd" -add_file -vhdl -lib "work" "tdc_release/TDC.vhd" -add_file -vhdl -lib "work" "tdc_release/up_counter.vhd" -add_file -vhdl -lib "work" "tdc_release/FIFO_36x128_OutReg_Counter.vhd" -add_file -vhdl -lib "work" "tdc_release/risingEdgeDetect.vhd" -add_file -vhdl -lib "work" "tdc_release/ROM4_Encoder.vhd" -add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd" -add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd" -add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x64_OutReg.vhd" -add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd" +#add_file -vhdl -lib "work" "tdc_release/ROM_encoder_3.vhd" +##add_file -vhdl -lib "work" "tdc_release/ROM_FIFO.vhd" +#add_file -vhdl -lib "work" "tdc_release/ShiftRegisterSISO.vhd" +#add_file -vhdl -lib "work" "tdc_release/TDC.vhd" +#add_file -vhdl -lib "work" "tdc_release/up_counter.vhd" +#add_file -vhdl -lib "work" "tdc_release/FIFO_36x128_OutReg_Counter.vhd" +#add_file -vhdl -lib "work" "tdc_release/risingEdgeDetect.vhd" +#add_file -vhdl -lib "work" "tdc_release/ROM4_Encoder.vhd" +#add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd" +#add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd" +#add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x64_OutReg.vhd" +#add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd" add_file -vhdl -lib work "./trb3_central.vhd"