From: Jan Michel Date: Tue, 23 Jun 2015 16:19:53 +0000 (+0200) Subject: adding some IO lines X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c1bd19699987d17c4a603958f58954bea31330c0;p=trb3sc.git adding some IO lines --- diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd index 4b21470..49b241d 100644 --- a/template/trb3sc_basic.vhd +++ b/template/trb3sc_basic.vhd @@ -43,7 +43,7 @@ entity trb3sc_basic is -- KEL : inout std_logic_vector(40 downto 1); --Additional IO - HDR_IO : inout std_logic_vector( 9 downto 0); + HDR_IO : inout std_logic_vector(10 downto 1); RJ_IO : inout std_logic_vector( 3 downto 0); SPARE_IN : in std_logic_vector( 1 downto 0); @@ -118,17 +118,18 @@ architecture trb3sc_arch of trb3sc_basic is signal reset_i : std_logic; signal clear_i : std_logic; - signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal led : std_logic_vector(1 downto 0); signal debug_clock_reset : std_logic_vector(31 downto 0); --Media Interface - signal med2int : med2int_array_t(0 to 0); - signal int2med : int2med_array_t(0 to 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); --READOUT - signal readout_rx : READOUT_RX; - signal readout_tx : readout_tx_array_t(0 to 0); + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx : CTRLBUS_RX; signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx : CTRLBUS_TX; @@ -138,8 +139,12 @@ architecture trb3sc_arch of trb3sc_basic is signal sed_error_i : std_logic; signal clock_select : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal uart_tx, uart_rx : std_logic; signal timer : TIMERS; + attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -313,13 +318,13 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record PROGRAMN => PROGRAMN, REBOOT_IN => common_ctrl_reg(15), --SPI - SPI_CS_OUT => open, - SPI_MOSI_OUT=> open, - SPI_MISO_IN => open, - SPI_CLK_OUT => open, + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT=> spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, --UART - UART_TX => open, - UART_RX => open, + UART_TX => uart_tx, + UART_RX => uart_rx, --ADC ADC_CS => ADC_CS, ADC_MOSI => ADC_DIN, @@ -346,7 +351,14 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record --------------------------------------------------------------------------- -- I/O --------------------------------------------------------------------------- - HDR_IO <= (others => '0'); + HDR_IO(1) <= uart_tx; + uart_rx <= HDR_IO(2); + HDR_IO(3) <= spi_mosi(8); + spi_miso(8) <= HDR_IO(4); + HDR_IO(5) <= spi_clk(8); + HDR_IO(6) <= spi_cs(8); + HDR_IO(10 downto 7) <= (others => '0'); + RJ_IO <= "0000"; BACK_GPIO <= (others => 'Z'); @@ -361,7 +373,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record LED_ORANGE <= debug_clock_reset(1); LED_RED <= not sed_error_i; LED_YELLOW <= debug_clock_reset(2); - LED_WHITE <= time_counter(26) & time_counter(28); + LED_WHITE <= led; LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX @@ -380,6 +392,10 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record end if; end process; + led(0) <= time_counter(26) and time_counter(19); + led(1) <= time_counter(20); + + -- TEST_LINE <= med_stat_debug(15 downto 0); end architecture;