From: Jan Michel Date: Tue, 26 Jan 2016 17:14:27 +0000 (+0100) Subject: Fixing readout of scaler registers in CTS X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c1d0fa34a9a4e158d509efe9cfe5f9c5072d358b;p=trb3.git Fixing readout of scaler registers in CTS --- diff --git a/base/code/input_statistics.vhd b/base/code/input_statistics.vhd index fab23ee..99ebf73 100644 --- a/base/code/input_statistics.vhd +++ b/base/code/input_statistics.vhd @@ -111,7 +111,7 @@ begin when x"0" => DATA_OUT <= enable(31 downto 0); when x"1" => DATA_OUT <= invert(31 downto 0); when x"2" => DATA_OUT <= std_logic_vector(rate); - when x"3" => DATA_OUT <= timer; + when x"3" => DATA_OUT <= std_logic_vector(timer); when x"4" => DATA_OUT <= status_reg; when x"5" => DATA_OUT <= enable(63 downto 32); when x"6" => DATA_OUT <= invert(63 downto 32); @@ -130,7 +130,7 @@ begin fifo_select <= to_integer(unsigned(ADDR_IN(4 downto 0))); fifo_wait <= '1'; elsif ADDR_IN(6 downto 5) = "10" and tmp < INPUTS then - DATA_OUT(23 downto 0) <= cnt(to_integer(unsigned(ADDR_IN(4 downto 0)))); + DATA_OUT(23 downto 0) <= std_logic_vector(cnt(to_integer(unsigned(ADDR_IN(4 downto 0))))); ACK_OUT <= '1'; else NACK_OUT <= '1'; @@ -244,7 +244,7 @@ end generate; status_reg(10 downto 0) <= fifo_count(0); status_reg(11) <= fifo_write; status_reg(15 downto 12)<= (others => '0'); -status_reg(27 downto 16)<= word_cnt; +status_reg(27 downto 16)<= std_logic_vector(word_cnt); status_reg(31 downto 28)<= (others => '0'); diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl index fd71812..ada63bb 100755 --- a/cts/compile_central_frankfurt.pl +++ b/cts/compile_central_frankfurt.pl @@ -17,7 +17,7 @@ my $lm_license_file_for_synplify = "1702\@hadeb05.gsi.de"; #"27000\@lxcad01.gsi. my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; my $lattice_path = '/d/jspc29/lattice/diamond/3.6_x64'; -my $synplify_path = '/d/jspc29/lattice/synplify/K-2015.09/'; +my $synplify_path = '/d/jspc29/lattice/synplify/J-2015.03-SP1/'; ################################################################################### diff --git a/cts/source/cts.vhd b/cts/source/cts.vhd index 7e795c5..bae75af 100755 --- a/cts/source/cts.vhd +++ b/cts/source/cts.vhd @@ -438,6 +438,9 @@ begin fifo_data_in_i <= "----" & trigger_type_buf_i & td_random_number_i & td_trigger_id_i; td_fsm_i <= TD_FSM_WAIT_FEE_RECV_TRIGGER; + + fee_input_counter_v := 0; + fee_channel_counter_v := 0; when TD_FSM_WAIT_FEE_RECV_TRIGGER => if LVL1_TRG_DATA_VALID_IN = '1' then @@ -467,24 +470,24 @@ begin if ro_configuration_buf_i(0) = '1' then FEE_DATA_WRITE_OUT <= '1'; if fee_input_counter_v mod 2 = 0 then - FEE_DATA_OUT <= input_counters_buf_i(32*fee_input_counter_v + 31 downto 32*fee_input_counter_v); + FEE_DATA_OUT <= input_counters_buf_i(32*(fee_input_counter_v/2) + 31 downto 32*(fee_input_counter_v/2)); else - FEE_DATA_OUT <= input_edge_counters_buf_i(32*fee_input_counter_v + 31 downto 32*fee_input_counter_v); + FEE_DATA_OUT <= input_edge_counters_buf_i(32*(fee_input_counter_v/2) + 31 downto 32*(fee_input_counter_v/2)); end if; end if; if fee_input_counter_v = 2*EFFECTIVE_INPUT_COUNT - 1 or ro_configuration_buf_i(0) = '0' then td_fsm_i <= TD_FSM_FEE_ENQUEUE_CHANNEL_COUNTER; - end if; - - fee_input_counter_v := fee_input_counter_v + 1; + else + fee_input_counter_v := fee_input_counter_v + 1; + end if; when TD_FSM_FEE_ENQUEUE_CHANNEL_COUNTER => if ro_configuration_buf_i(1) = '1' then if fee_channel_counter_v mod 2 = 0 then - FEE_DATA_OUT <= channel_counters_buf_i(32*fee_channel_counter_v + 31 downto 32*fee_channel_counter_v/2); + FEE_DATA_OUT <= channel_counters_buf_i(32*(fee_channel_counter_v/2) + 31 downto 32*(fee_channel_counter_v/2)); else - FEE_DATA_OUT <= channel_edge_counters_buf_i(32*fee_channel_counter_v + 31 downto 32*fee_channel_counter_v/2); + FEE_DATA_OUT <= channel_edge_counters_buf_i(32*(fee_channel_counter_v/2) + 31 downto 32*(fee_channel_counter_v/2)); end if; FEE_DATA_WRITE_OUT <= '1'; @@ -492,9 +495,9 @@ begin if fee_channel_counter_v = 2*to_integer(unsigned(num_of_itc_used_i)) - 1 or ro_configuration_buf_i(1) = '0' then td_fsm_i <= TD_FSM_FEE_ENQUEUE_IDLE_COUNTER; - end if; - - fee_channel_counter_v := fee_channel_counter_v + 1; + else + fee_channel_counter_v := fee_channel_counter_v + 1; + end if; when TD_FSM_FEE_ENQUEUE_IDLE_COUNTER => FEE_DATA_OUT <= stat_idle_time_buf_i;