From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Tue, 10 May 2022 19:00:09 +0000 (+0200)
Subject: forgotten :)
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c22da387750ae7349248395d0b57037f99fa60b1;p=daqdocu.git

forgotten :)
---

diff --git a/trb3/DS_SignalDescription.tex b/trb3/DS_SignalDescription.tex
index 80a9a78..720c93e 100644
--- a/trb3/DS_SignalDescription.tex
+++ b/trb3/DS_SignalDescription.tex
@@ -17,7 +17,8 @@ to include TX channel serializer synchronization and RX channel WordAlignment.
   \item \texttt{RX{\_}DLM{\_}WORD{\_}OUT} -- DLM data byte received, per channel. 
   \item \texttt{TX{\_}DLM{\_}IN} -- send one DLM komma.\newline
         Data byte must be valid when this signal is set for one clock cycle
-        of \texttt{TXI{\_}CLK}.
+        of \texttt{TXI{\_}CLK}.\newline
+        Signal must be in phase with \texttt{TX{\_}K} for correct operation.
   \item \texttt{TX{\_}DLM{\_}WORD{\_}IN} -- DLM data byte to be sent.\newline
         A SP needs to connect these ports directly together to implement \texttt{DLM} komma
         ping functionality, used for link delay measurements.
@@ -34,13 +35,24 @@ to include TX channel serializer synchronization and RX channel WordAlignment.
         SP \texttt{WORD{\_}SYNC{\_}OUT} to keep links word aligned.
   \item \texttt{WORD{\_}SYNC{\_}OUT} -- only valid if a SP is in the MI. Connects to 
         \texttt{WORD{\_}SYNC{\_}IN} of all Quads containing MPs.
-  \item \texttt{MASTER{\_}CLK{\_}IN} -- clock used on TX PLL inside Quad.
+  \item \texttt{MASTER{\_}CLK{\_}IN} -- clock used on TX PLL inside Quad.\newline
+        On root MP, connect to local oscillator to be used as root clock.
   \item \texttt{MASTER{\_}CLK{\_}OUT} -- recovered RX clock, if SP is available in the Quad.
-  \item \texttt{GLOBAL{\_}RESET{\_}IN} -- used for initial Quad reset (\texttt{RST{\_}QD{\_}C}) and keeping
-        SerDes related function blocks in reset. Usually connects to \texttt{GLOBAL{\_}RESET{\_}OUT} of 
-        the SP.
-  \item \texttt{GLOBAL{\_}RESET{\_}OUT} -- only valid on SP, signal is derived from \texttt{SFP{\_}LOS} signal
-        on uplink. Used to keep FPGA logic in hard reset. 
+  \item \texttt{QUAD{\_}RST{\_}IN} -- used for initial Quad reset (\texttt{RST{\_}QD{\_}C}) 
+        and keeping SerDes related function blocks in reset. Usually connects to 
+        \texttt{GLOBAL{\_}RESET{\_}OUT} of the SP.\newline
+        Handle with care. If connected the wrong way, deadlocks may occur.
+  \item \texttt{GLOBAL{\_}RESET{\_}OUT} -- only valid on SP, signal is derived from 
+        \texttt{SFP{\_}LOS} signal on uplink. Used to keep FPGA logic in hard reset.\newline
+        Usually connects to \texttt{clock{\_}reset{\_}handler} entity.
+  \item \texttt{SLAVE{\_}ACTIVE{\_}OUT} -- indicates up- and downlink stable on SP.\newline
+        Used to delay link establishment on hub MPs, usually connects to 
+        \texttt{SLAVE{\_}ACTIVE{\_}IN} of all Quads.
+  \item \texttt{SLAVE{\_}ACTIVE{\_}IN} -- used to delay link establishment on hubs.\newline
+        Connects to \texttt{SLAVE{\_}ACTIVE{\_}OUT} of Quad containing the SP in hubs,
+        is set to static high otherwise. It MPs are affected by this signal.\newline
+        Forces \texttt{TX{\_}DIS} high to keep connected boards in reset while up- and 
+        downlink on SP are established.   
   \item \texttt{TX{\_}PLL{\_}LOL{\_}IN} -- wired or of all \texttt{TX{\_}PLL{\_}LOL} signals of all Quads used in
         the FPGA. Usually originates from \texttt{main{\_}tx{\_}reset{\_}RS} component.
   \item \texttt{TX{\_}PLL{\_}LOL{\_}OUT} -- TX PLL lock signal from SerDes inside the MI. Usually connected to
@@ -52,6 +64,6 @@ to include TX channel serializer synchronization and RX channel WordAlignment.
   \item \texttt{SYNC{\_}TX{\_}PLL{\_}IN} -- TX Serializer sync signal. Usually connected to \texttt{main{\_}tx{\_}reset{\_}RS} 
         component. 
   \item \texttt{DESTROY{\_}LINK{\_}IN} -- one bit signal per channel, only used for MPs. If set, the 
-        \texttt{SFP{\_}TX{\_}DISABLE} line to SFP is set and all connected boards will be forced into
+        \texttt{SFP{\_}TX{\_}DIS} line to SFP is set and all connected boards will be forced into
         hard reset. 
 \end{itemize*}