From: Jan Michel Date: Tue, 23 Aug 2022 15:23:41 +0000 (+0200) Subject: add automatic ADC reader to Trb5sc designs X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c2c559ea50025e9bb04dbdb26a96f1598ccb2b42;p=trb5sc.git add automatic ADC reader to Trb5sc designs --- diff --git a/gbe_standalone/config.vhd b/gbe_standalone/config.vhd index c91c178..381e7d9 100644 --- a/gbe_standalone/config.vhd +++ b/gbe_standalone/config.vhd @@ -49,6 +49,7 @@ package config is constant INCLUDE_UART : integer := c_YES; --300 slices constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_ADC : integer := c_YES; constant INCLUDE_LCD : integer := c_NO; --800 slices constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices diff --git a/gbe_standalone/trb5sc_gbe_template.prj b/gbe_standalone/trb5sc_gbe_template.prj index b88dd1c..9cd3de6 100644 --- a/gbe_standalone/trb5sc_gbe_template.prj +++ b/gbe_standalone/trb5sc_gbe_template.prj @@ -116,6 +116,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/gbe_standalone/trb5sc_gbe_template.vhd b/gbe_standalone/trb5sc_gbe_template.vhd index 0303ba8..4ca55d3 100644 --- a/gbe_standalone/trb5sc_gbe_template.vhd +++ b/gbe_standalone/trb5sc_gbe_template.vhd @@ -330,6 +330,13 @@ begin -- Control Tools ------------------------------------------------------------------------------- THE_TOOLS : entity work.trb3sc_tools + generic map( + ADC_CMD_1 => x"2c3cb", + ADC_CMD_2 => x"1d5cb", + ADC_CMD_3 => x"1e3cb", + ADC_CMD_4 => x"2f5cb", + ADC_CMD_T => x"1F393" + ) port map( CLK => clk_sys, RESET => reset_i, diff --git a/mimosis/config.vhd b/mimosis/config.vhd index b2db444..4b4a76a 100644 --- a/mimosis/config.vhd +++ b/mimosis/config.vhd @@ -51,6 +51,7 @@ package config is constant INCLUDE_UART : integer := c_NO; --300 slices constant INCLUDE_SPI : integer := c_NO; --300 slices + constant INCLUDE_ADC : integer := c_YES; constant INCLUDE_LCD : integer := c_NO; --800 slices constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices diff --git a/mimosis/trb5sc_mimosis.prj b/mimosis/trb5sc_mimosis.prj index 79f9de9..da91664 100644 --- a/mimosis/trb5sc_mimosis.prj +++ b/mimosis/trb5sc_mimosis.prj @@ -117,6 +117,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/mimosis/trb5sc_mimosis.vhd b/mimosis/trb5sc_mimosis.vhd index c38e979..748735e 100644 --- a/mimosis/trb5sc_mimosis.vhd +++ b/mimosis/trb5sc_mimosis.vhd @@ -346,6 +346,13 @@ RJ(0) <= clk_40; -- Control Tools --------------------------------------------------------------------------- THE_TOOLS : entity work.trb3sc_tools + generic map( + ADC_CMD_1 => x"2c3cb", + ADC_CMD_2 => x"1d5cb", + ADC_CMD_3 => x"1e3cb", + ADC_CMD_4 => x"2f5cb", + ADC_CMD_T => x"1F393" + ) port map( CLK => clk_sys, RESET => reset_i, diff --git a/template/config.vhd b/template/config.vhd index da29651..1973faf 100644 --- a/template/config.vhd +++ b/template/config.vhd @@ -49,6 +49,7 @@ package config is constant INCLUDE_UART : integer := c_YES; --300 slices constant INCLUDE_SPI : integer := c_YES; --300 slices + constant INCLUDE_ADC : integer := c_YES; constant INCLUDE_LCD : integer := c_NO; --800 slices constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices diff --git a/template/trb5sc_template.prj b/template/trb5sc_template.prj index 1212a85..ab9a75d 100644 --- a/template/trb5sc_template.prj +++ b/template/trb5sc_template.prj @@ -114,6 +114,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd" +add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/template/trb5sc_template.vhd b/template/trb5sc_template.vhd index 3613255..4b0c911 100644 --- a/template/trb5sc_template.vhd +++ b/template/trb5sc_template.vhd @@ -303,6 +303,13 @@ THE_CAL_PLL : entity work.pll_in125_out50 -- Control Tools --------------------------------------------------------------------------- THE_TOOLS : entity work.trb3sc_tools + generic map( + ADC_CMD_1 => x"2c3cb", + ADC_CMD_2 => x"1d5cb", + ADC_CMD_3 => x"1e3cb", + ADC_CMD_4 => x"2f5cb", + ADC_CMD_T => x"1F393" + ) port map( CLK => clk_sys, RESET => reset_i,