From: Michael Boehmer Date: Sun, 30 Jan 2022 20:51:46 +0000 (+0100) Subject: phase_core with PFU placement X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c30c2d9bb02523b02ed6d2e6339391e50a31ef6a;p=trb3sc.git phase_core with PFU placement --- diff --git a/cts/par.p2t b/cts/par.p2t index f17afe1..343654d 100644 --- a/cts/par.p2t +++ b/cts/par.p2t @@ -1,7 +1,7 @@ -w -l 5 -s 10 --t 3 # seed setting here! +-t 51 # seed setting here! 3 4 13 17 37 -c 0 -e 0 -i 6 diff --git a/cts/trb3sc_cts.lpf b/cts/trb3sc_cts.lpf index dc9b367..10b3336 100644 --- a/cts/trb3sc_cts.lpf +++ b/cts/trb3sc_cts.lpf @@ -7,6 +7,11 @@ REGION "MEDIA_LEFT" "R102C17D" 13 75; # LEFT is for PCSD/PCSB REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_LEFT"; +#LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/gen_control.3.gen_phaser.THE_PHASER/THE_PHASER_CORE/phaser_core_group" SITE "R113C61D"; # 181039 +#LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/gen_control.3.gen_phaser.THE_PHASER/THE_PHASER_CORE/phaser_core_group" SITE "R114C90D"; # 184235 +#LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/gen_control.3.gen_phaser.THE_PHASER/THE_PHASER_CORE/phaser_core_group" SITE "R107C74D"; # 191203 +LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/gen_control.3.gen_phaser.THE_PHASER/THE_PHASER_CORE/phaser_core_group" SITE "R111C77D"; # + BLOCK PATH FROM CELL THE_TDC/calibration_o*; BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*; BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/TheTriggerHandler/trg_in_r[0]; diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj index 8c31ac5..b190322 100644 --- a/cts/trb3sc_cts.prj +++ b/cts/trb3sc_cts.prj @@ -140,6 +140,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" add_file -vhdl -lib work "../../trbnet/special/phaser.vhd" +add_file -vhdl -lib work "../../trbnet/special/phaser_core.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 5e9612d..10f2519 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -318,7 +318,9 @@ THE_CLOCK_RESET : entity work.clock_reset_handler make_reset_by_gbe <= last_reset_via_gbe_long and not reset_via_gbe_long; -- pulse, 1 clock cycle end process; -- REMARK: this should be transfered to GbE part. - +-- BUG: for some reasons, some TRB3sc refuse to work with this reset. Links are not destroyed reliably, +-- and strange things happen with WAP. + pll_calibration : entity work.pll_in125_out33 port map ( CLK => CLK_SUPPL_PCLK, @@ -347,6 +349,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate -- Clocks and reset CLK_REF_FULL => clk_full_osc, SYSCLK => clk_sys, + SAMPLE_CLK => CLK_SUPPL_PCLK, RESET => reset_i, -- check -- Media Interface TX/RX MEDIA_MED2INT(0) => open, @@ -390,6 +393,10 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate DESTROY_LINK_IN(3) => destroy_link_i, WAP_REQUESTED_IN => wap_requested_i, RX_INDEX_OUT => rx_index_i, + DLM_RESULT_OUT(0*32+31 downto 0*32) => open, + DLM_RESULT_OUT(1*32+31 downto 1*32) => open, + DLM_RESULT_OUT(2*32+31 downto 2*32) => open, + DLM_RESULT_OUT(3*32+31 downto 3*32) => phaser_data, --SFP Connection SD_PRSNT_N_IN(0) => '1', SD_LOS_IN(0) => '1', @@ -430,37 +437,6 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate STATE_OUT => tx_reset_state ); - -------------------------------------------------------------------- - -------------------------------------------------------------------- - THE_PHASER: entity phaser - port map( - SAMPLE_CLK => CLK_SUPPL_PCLK, - RESET => reset_i, - SIGNAL_A_IN => word_sync_i, - SIGNAL_B_IN => rx_index_i(3), - LOW_CNT_OUT => open, - HI_CNT_OUT => phaser_data(31 downto 16), - UPDATE_OUT => phaser_update - ); - - THE_COARSE_COUNTER_PROC: process( clk_full_osc ) - begin - if( rising_edge(clk_full_osc) ) then - if( tx_dlm_i = '1' ) then - coarse_counter <= (others => '0'); - else - coarse_counter <= coarse_counter + 1; - end if; - if( rx_dlm_i = '1' ) then - coarse_delay <= std_logic_vector(coarse_counter); - end if; - end if; - end process THE_COARSE_COUNTER_PROC; - - phaser_data(15 downto 0) <= coarse_delay; - -------------------------------------------------------------------- - -------------------------------------------------------------------- - PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 -- just for testing