From: Michael Boehmer Date: Sun, 20 Mar 2022 21:22:48 +0000 (+0100) Subject: BETA. changed TX_DIS to K_NULL X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c33e7ff764636ece846c4a70969d4a0ae1e85776;p=trbnet.git BETA. changed TX_DIS to K_NULL --- diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index a8dee63..d7d1697 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -37,10 +37,9 @@ entity med_ecp3_sfp_sync_all_RS is MASTER_CLK_IN : in std_logic; -- recovered RX clock in (only master ports in quad) MASTER_CLK_OUT : out std_logic; -- recovered RX clock out (slave port in quad) QUAD_RST_IN : in std_logic; -- HANDLE WITH CARE - GLOBAL_RESET_OUT : out std_logic; -- only available on MI with slave port + LINK_TX_NULL_IN : in std_logic; -- + LINK_RX_NULL_OUT : out std_logic; -- SLAVE_ACTIVE_OUT : out std_logic; -- for delaying MPs in hub - SLAVE_ACTIVE_IN : in std_logic; -- set to '1' on normal endpoints - TX_PLL_LOL_IN : in std_logic; -- and'ed TX PLL LOL to sync startup TX_PLL_LOL_OUT : out std_logic; -- status signal of TX PLL TX_CLK_AVAIL_OUT : out std_logic; -- stable RX recovered clock available TX_PCS_RST_IN : in std_logic; -- TX PCS reset signal @@ -130,13 +129,13 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is signal rx_rst_i : std_logic_vector(3 downto 0); signal rx_dlm_i : std_logic_vector(3 downto 0); - signal global_reset_i : std_logic_vector(3 downto 0); - signal pll_lol_i : std_logic; signal link_rx_ready_i : std_logic_vector(3 downto 0); - signal tx_clk_avail_sel : std_logic; - + + signal link_rx_null_i : std_logic_vector(3 downto 0); + signal link_tx_null_i : std_logic_vector(3 downto 0); + signal word_sync_i : std_logic_vector(3 downto 0); signal word_sync_sel : std_logic; @@ -166,59 +165,45 @@ begin ------------------------------------------------- -- SFPs are disabled on unused SerDes channels ------------------------------------------------- --- BUG: slave ports need also disable with link_tx_ready(i) - SD_TXDIS_OUT(3) <= DESTROY_LINK_IN(3) or (not SLAVE_ACTIVE_IN) --or RESET - when IS_MODE(3) = c_IS_MASTER else - not link_rx_ready_i(3) when IS_MODE(3) = c_IS_SLAVE else - '1' when IS_MODE(3) = c_IS_UNUSED else - '0'; - SD_TXDIS_OUT(2) <= DESTROY_LINK_IN(2) or (not SLAVE_ACTIVE_IN) --or RESET - when IS_MODE(2) = c_IS_MASTER else - not link_rx_ready_i(2) when IS_MODE(2) = c_IS_SLAVE else - '1' when IS_MODE(2) = c_IS_UNUSED else - '0'; - SD_TXDIS_OUT(1) <= DESTROY_LINK_IN(1) or (not SLAVE_ACTIVE_IN) --or RESET - when IS_MODE(1) = c_IS_MASTER else - not link_rx_ready_i(1) when IS_MODE(1) = c_IS_SLAVE else - '1' when IS_MODE(1) = c_IS_UNUSED else - '0'; - SD_TXDIS_OUT(0) <= DESTROY_LINK_IN(0) or (not SLAVE_ACTIVE_IN) --or RESET - when IS_MODE(0) = c_IS_MASTER else - not link_rx_ready_i(0) when IS_MODE(0) = c_IS_SLAVE else - '1' when IS_MODE(0) = c_IS_UNUSED else - '0'; - -------------------------------------------------- + SD_TXDIS_OUT(3) <= '1' when (IS_MODE(3) = c_IS_UNUSED) else '0'; + SD_TXDIS_OUT(2) <= '1' when (IS_MODE(2) = c_IS_UNUSED) else '0'; + SD_TXDIS_OUT(1) <= '1' when (IS_MODE(1) = c_IS_UNUSED) else '0'; + SD_TXDIS_OUT(0) <= '1' when (IS_MODE(0) = c_IS_UNUSED) else '0'; + +------------------------------------------------- -- TX ref clock -- output only if a slave port is available in QUAD -------------------------------------------------- +------------------------------------------------- MASTER_CLK_OUT <= clk_rx_full(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else clk_rx_full(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else clk_rx_full(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else clk_rx_full(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else '0'; -------------------------------------------------- +------------------------------------------------- -- global reset -- output only if a slave port is available in QUAD -------------------------------------------------- - GLOBAL_RESET_OUT <= global_reset_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else - global_reset_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else - global_reset_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else - global_reset_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else +------------------------------------------------- + LINK_RX_NULL_OUT <= link_rx_null_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else + link_rx_null_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else + link_rx_null_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else + link_rx_null_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else '0'; + link_tx_null_i(3) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(3)) when (IS_MODE(3) = c_IS_MASTER) else '0'; + link_tx_null_i(2) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(2)) when (IS_MODE(2) = c_IS_MASTER) else '0'; + link_tx_null_i(1) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(1)) when (IS_MODE(1) = c_IS_MASTER) else '0'; + link_tx_null_i(0) <= (LINK_TX_NULL_IN or DESTROY_LINK_IN(0)) when (IS_MODE(0) = c_IS_MASTER) else '0'; + ------------------------------------------------- -- stable RX recovered clock available ------------------------------------------------- - tx_clk_avail_sel <= link_rx_ready_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else + TX_CLK_AVAIL_OUT <= link_rx_ready_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else link_rx_ready_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else link_rx_ready_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else link_rx_ready_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else '1'; - TX_CLK_AVAIL_OUT <= tx_clk_avail_sel; - ------------------------------------------------- -- ------------------------------------------------- @@ -455,7 +440,6 @@ gen_control : for i in 0 to 3 generate RX_LOS_IN => rx_los_low(i), RX_CV_IN => rx_error(i), RX_LSM_IN => lsm_status(i), - TX_PLL_LOL_IN => TX_PLL_LOL_IN, WA_POSITION_IN => wa_position_i(i*4+3 downto i*4), WAP_REQUESTED_IN => wap_requested_i(i*4+3 downto i*4), WAP_REQ_OUT => wap_req_i(i), @@ -470,10 +454,11 @@ gen_control : for i in 0 to 3 generate -- ports for synchronous operation WORD_SYNC_IN => WORD_SYNC_IN, WORD_SYNC_OUT => word_sync_i(i), - GLOBAL_RESET_OUT => global_reset_i(i), LINK_TX_READY_IN => LINK_TX_READY_IN, LINK_RX_READY_OUT => link_rx_ready_i(i), LINK_ACTIVE_OUT => link_active_i(i), + LINK_RX_NULL_OUT => link_rx_null_i(i), + LINK_TX_NULL_IN => link_tx_null_i(i), -- komma operation TX_DLM_IN => TX_DLM_IN, TX_DLM_WORD_IN => TX_DLM_WORD_IN, diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd index 47d523b..4e39ed4 100644 --- a/media_interfaces/sync/main_rx_reset_RS.vhd +++ b/media_interfaces/sync/main_rx_reset_RS.vhd @@ -6,12 +6,10 @@ entity main_rx_reset_RS is port ( CLEAR : in std_logic; CLK_REF : in std_logic; - PLL_LOL_IN : in std_logic; CDR_LOL_IN : in std_logic; CV_IN : in std_logic; LSM_IN : in std_logic; LOS_IN : in std_logic; - SD_LOS_IN : in std_logic; WAP_ZERO_IN : in std_logic; -- outputs WAP_REQ_OUT : out std_logic; @@ -34,12 +32,10 @@ architecture main_rx_reset_RS_arch of main_rx_reset_RS is constant Tcdr_bit : integer := 22; constant Tviol_bit : integer := 22; - signal pll_lol_s : std_logic; signal cdr_lol_s : std_logic; signal cv_s : std_logic; signal lsm_s : std_logic; signal los_s : std_logic; - signal sd_los_s : std_logic; signal wap_zero_s : std_logic; signal cnt : unsigned(31 downto 0); @@ -55,19 +51,16 @@ architecture main_rx_reset_RS_arch of main_rx_reset_RS is begin -- Remark: on ECP3, rx_serdes_rst sets RX_CDR_LOL. Deadlocks on POWERUP. --- Remark: RX_LOS is not necessary, as SFP_LOS keeps us safely in reset. -- Remark: syncing is done here by one FF only. Might be dangerous. ------------------------------------------------------------------ RX_RESET_PROC : process( CLEAR, CLK_REF ) begin if( CLEAR = '1' ) then - pll_lol_s <= '1'; cdr_lol_s <= '1'; cv_s <= '1'; lsm_s <= '0'; los_s <= '1'; - sd_los_s <= '1'; wap_zero_s <= '0'; RX_SERDES_RST_OUT <= '1'; @@ -78,12 +71,10 @@ begin STATE_OUT <= x"f"; cnt <= (others => '0'); elsif( rising_edge(CLK_REF) ) then - pll_lol_s <= PLL_LOL_IN; cdr_lol_s <= CDR_LOL_IN; cv_s <= CV_IN; lsm_s <= LSM_IN; los_s <= LOS_IN; - sd_los_s <= SD_LOS_IN; wap_zero_s <= WAP_ZERO_IN; case rx_sm is @@ -92,8 +83,7 @@ begin RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; --- if( (pll_lol_s = '1') or (los_s = '1') or (sd_los_s = '1') ) then - if( (pll_lol_s = '1') or (sd_los_s = '1') ) then + if( (los_s = '1') ) then -- seems to work cnt <= (others => '0'); else if( cnt(Tplol_bit) = '1' ) then @@ -133,7 +123,10 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - if( cdr_lol_s = '1' ) then + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( cdr_lol_s = '1' ) then cnt <= (others => '0'); rx_sm <= APPLY_CDR_RST; else @@ -150,7 +143,10 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - if( cnt(Tshort_bit) = '1' ) then + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( cnt(Tshort_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= WAIT_RXPCS_LOCK; else @@ -162,7 +158,10 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; - if( cnt(Tviol_bit) = '1' ) then + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( cnt(Tviol_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= TEST_RXPCS; else @@ -174,7 +173,10 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; - if( (lsm_s = '0') or (cv_s = '1') ) then + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( (lsm_s = '0') or (cv_s = '1') ) then cnt <= (others => '0'); rx_sm <= APPLY_RXPCS_RST; else @@ -192,12 +194,14 @@ begin RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; cnt <= (others => '0'); - if( cnt(Tshort_bit) = '1' ) then + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( cnt(Tshort_bit) = '1' ) then cnt <= (others => '0'); if( wap_zero_s = '1' ) then rx_sm <= NORMAL_OP; else --- rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK rx_sm <= APPLY_CDR_RST; end if; else @@ -210,7 +214,10 @@ begin RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '1'; cnt <= (others => '0'); - if( (lsm_s = '0') or (cv_s = '1') ) then -- DANGEROUS + if ( los_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + elsif( (lsm_s = '0') or (cv_s = '1') ) then -- DANGEROUS rx_sm <= APPLY_RXPCS_RST; end if; @@ -224,17 +231,10 @@ begin cnt <= (others => '0'); end case; - ------------------------------------------------- - if( (pll_lol_s = '1') or (sd_los_s = '1') ) then - rx_sm <= POWERUP; - cnt <= (others => '0'); - end if; end if; end process rx_reset_proc; --- WAP_REQ_OUT <= '1' when ((rx_sm = WAIT_RXPCS_LOCK) or (rx_sm = TEST_RXPCS)) else '0'; WAP_REQ_OUT <= '1' when ((rx_sm = TEST_RXPCS)) else '0'; end architecture; diff --git a/media_interfaces/sync/main_tx_reset_RS.vhd b/media_interfaces/sync/main_tx_reset_RS.vhd index d782390..cda5e69 100644 --- a/media_interfaces/sync/main_tx_reset_RS.vhd +++ b/media_interfaces/sync/main_tx_reset_RS.vhd @@ -12,7 +12,6 @@ entity main_tx_reset_RS is TX_PLL_LOL_QD_B_IN : in std_logic; -- QUAD B TX_PLL_LOL_QD_C_IN : in std_logic; -- QUAD C TX_PLL_LOL_QD_D_IN : in std_logic; -- QUAD D - TX_PLL_LOL_OUT : out std_logic; -- wired'or for RX state machines TX_CLOCK_AVAIL_IN : in std_logic; -- recovered RX clock available (if needed) TX_PCS_RST_CH_C_OUT : out std_logic; -- PCS reset SYNC_TX_QUAD_OUT : out std_logic; -- sync all QUADs to TX bit 0 @@ -49,9 +48,6 @@ begin tx_pll_lol_all <= TX_PLL_LOL_QD_A_IN or TX_PLL_LOL_QD_B_IN or TX_PLL_LOL_QD_C_IN or TX_PLL_LOL_QD_D_IN; - - TX_PLL_LOL_OUT <= tx_pll_lol_all; - -- synchronize, just to be on the safe side SYNC_SFP_SIGS : entity work.signal_sync generic map( @@ -68,7 +64,6 @@ begin D_OUT(1) => tx_clock_avail_q ); - -- Timer THE_TIMER_PROC: process( CLK_REF ) begin @@ -85,7 +80,6 @@ begin timer <= counter(count_index); - -- State machine clocked process THE_FSM_PROC: process( CLK_REF, CLEAR ) begin @@ -125,7 +119,7 @@ begin when WAIT_FOR_TIMER => STATE_OUT <= x"2"; tx_pcs_rst_ch_c_int <= '1'; - if( timer = '1' ) then + if( (timer = '1') and (tx_pll_lol_all_q = '0') ) then NEXT_STATE <= SYNC_ALL; else NEXT_STATE <= WAIT_FOR_TIMER; diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index fb0d8b2..8a80644 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -29,7 +29,6 @@ entity med_sync_control_RS is RX_LOS_IN : in std_logic; -- SerDes RX input signal status RX_CV_IN : in std_logic; -- SerDes RX CodeViolation status RX_LSM_IN : in std_logic; -- SerDes TX LinkStateMachine status - TX_PLL_LOL_IN : in std_logic; -- wired'or from all QUADs WA_POSITION_IN : in std_logic_vector(3 downto 0); -- WordAlignment Position WAP_REQUESTED_IN : in std_logic_vector(3 downto 0); -- TESTTESTTEST WAP_REQ_OUT : out std_logic; @@ -44,10 +43,11 @@ entity med_sync_control_RS is -- ports for synchronous operation WORD_SYNC_IN : in std_logic; -- sync signal for Byte/Word Alignment WORD_SYNC_OUT : out std_logic; - GLOBAL_RESET_OUT : out std_logic; -- global reset from slave port LINK_TX_READY_IN : in std_logic; -- LINK_RX_READY_OUT : out std_logic; -- LINK_ACTIVE_OUT : out std_logic; -- + LINK_RX_NULL_OUT : out std_logic; + LINK_TX_NULL_IN : in std_logic; -- komma handling TX_DLM_IN : in std_logic; -- transmit one DLM komma TX_DLM_WORD_IN : in std_logic_vector(7 downto 0); @@ -103,6 +103,8 @@ architecture med_sync_control_arch of med_sync_control_RS is signal link_active_i : std_logic; signal link_active_qref : std_logic; signal link_active_qsys : std_logic; + signal link_rx_null_i : std_logic; + signal link_rx_null_qref : std_logic; -- attribute syn_keep : boolean; -- attribute syn_preserve : boolean; @@ -115,10 +117,6 @@ begin -- Reset signals ------------------------------------------------- --- we use uplink signal detection as global reset (slave port) --- doesn't make sense to start while no link partner is available - GLOBAL_RESET_OUT <= SFP_LOS_IN; - -- TX_CONTROL and RX_CONTROL reset reset_i <= RESET; @@ -132,12 +130,10 @@ begin port map( CLEAR => '0', CLK_REF => CLK_REF, - PLL_LOL_IN => TX_PLL_LOL_IN, CDR_LOL_IN => RX_CDR_LOL_IN, CV_IN => RX_CV_IN, LSM_IN => RX_LSM_IN, LOS_IN => RX_LOS_IN, - SD_LOS_IN => SFP_LOS_IN, WAP_ZERO_IN => is_wap_zero_i, -- outputs WAP_REQ_OUT => WAP_REQ_OUT, @@ -171,7 +167,7 @@ begin port map( CLK_RXI => CLK_RXI, CLK_SYS => CLK_SYS, - RESET => reset_i, + RESET => '0', --reset_i, -- RX_DATA_OUT => media_med2int_i.data, RX_PACKET_NUMBER_OUT => media_med2int_i.packet_num, @@ -191,6 +187,7 @@ begin LINK_RX_READY_IN => link_rx_ready_i, -- internally synced LINK_HALF_DONE_OUT => link_half_done_i, -- CLK_RXI based LINK_FULL_DONE_OUT => link_full_done_i, -- CLK_RXI based + LINK_RX_NULL_OUT => link_rx_null_i, -- CLK_RXI based -- DEBUG_OUT => debug_rx_control_i, STAT_REG_OUT => STAT_RX_CONTROL @@ -212,7 +209,7 @@ begin port map( CLK_TXI => CLK_TXI, CLK_SYS => CLK_SYS, - RESET => reset_i, + RESET => '0', --reset_i, -- Media Interface TX_DATA_IN => MEDIA_INT2MED.data, TX_PACKET_NUMBER_IN => MEDIA_INT2MED.packet_num, @@ -233,6 +230,7 @@ begin LINK_RX_READY_IN => link_rx_ready_i, -- internally synced LINK_HALF_DONE_IN => link_half_done_i, -- internally synced LINK_FULL_DONE_IN => link_full_done_i, -- internally synced + LINK_TX_NULL_IN => LINK_TX_NULL_IN, -- debug DEBUG_OUT => debug_tx_control_i, STAT_REG_OUT => STAT_TX_CONTROL @@ -317,7 +315,7 @@ begin SYNC_LA_SIGS : entity work.signal_sync generic map( - WIDTH => 1, + WIDTH => 2, DEPTH => 3 ) port map( @@ -325,11 +323,14 @@ begin CLK0 => CLK_REF, CLK1 => CLK_REF, D_IN(0) => link_active_i, - D_OUT(0) => link_active_qref + D_IN(1) => link_rx_null_i, + D_OUT(0) => link_active_qref, + D_OUT(1) => link_rx_null_qref ); - LINK_ACTIVE_OUT <= link_active_qref; - + LINK_ACTIVE_OUT <= link_active_qref; + LINK_RX_NULL_OUT <= link_rx_null_qref; + -- TEST_LINE signals -- DEBUG_OUT(31 downto 12) <= (others => '0'); -- DEBUG_OUT(11) <= link_full_done_qsys; diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd index d616d68..4ed1ccf 100644 --- a/media_interfaces/sync/med_sync_define_RS.vhd +++ b/media_interfaces/sync/med_sync_define_RS.vhd @@ -83,7 +83,6 @@ component main_tx_reset_RS is TX_PLL_LOL_QD_B_IN : in std_logic; -- QUAD B TX_PLL_LOL_QD_C_IN : in std_logic; -- QUAD C TX_PLL_LOL_QD_D_IN : in std_logic; -- QUAD D - TX_PLL_LOL_OUT : out std_logic; -- wired'or for RX state machines TX_CLOCK_AVAIL_IN : in std_logic; -- recovered RX clock available (if needed) TX_PCS_RST_CH_C_OUT : out std_logic; -- PCS reset SYNC_TX_QUAD_OUT : out std_logic; -- sync all QUADs to TX bit 0 @@ -114,6 +113,7 @@ component rx_control_RS is LINK_RX_READY_IN : in std_logic; LINK_HALF_DONE_OUT : out std_logic; LINK_FULL_DONE_OUT : out std_logic; + LINK_RX_NULL_OUT : out std_logic; -- debug DEBUG_OUT : out std_logic_vector(31 downto 0); STAT_REG_OUT : out std_logic_vector(31 downto 0) @@ -148,6 +148,7 @@ component tx_control_RS is LINK_RX_READY_IN : in std_logic; -- local ref clock LINK_HALF_DONE_IN : in std_logic; -- recovered RX clock LINK_FULL_DONE_IN : in std_logic; -- recovered RX clock + LINK_TX_NULL_IN : in std_logic; -- debug DEBUG_OUT : out std_logic_vector(31 downto 0); STAT_REG_OUT : out std_logic_vector(31 downto 0) diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index 3e192f5..7c0dd8d 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -29,6 +29,7 @@ entity rx_control_RS is LINK_RX_READY_IN : in std_logic; -- used for synchronous reset LINK_HALF_DONE_OUT : out std_logic; LINK_FULL_DONE_OUT : out std_logic; + LINK_RX_NULL_OUT : out std_logic; -- link received K_NULL -- debug DEBUG_OUT : out std_logic_vector(31 downto 0); STAT_REG_OUT : out std_logic_vector(31 downto 0) @@ -37,7 +38,7 @@ end entity; architecture rx_control_arch of rx_control_RS is - type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, GET_RST, + type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, GET_RST, GET_NULL, GET_UNKNOWN); signal rx_state : rx_state_t; @@ -88,16 +89,6 @@ architecture rx_control_arch of rx_control_RS is attribute syn_noprune : boolean; attribute syn_noprune of rx_dlm_i : signal is true; - -- attribute syn_keep : boolean; --- attribute syn_preserve : boolean; --- attribute syn_noprune : boolean; --- attribute syn_keep of idle0_detected : signal is true; --- attribute syn_preserve of idle0_detected : signal is true; --- attribute syn_noprune of idle0_detected : signal is true; --- attribute syn_keep of idle1_detected : signal is true; --- attribute syn_preserve of idle1_detected : signal is true; --- attribute syn_noprune of idle1_detected : signal is true; - begin -- Syncing things @@ -220,6 +211,8 @@ begin rx_state <= GET_DLM; when K_RST => rx_state <= GET_RST; + when K_NULL => + rx_state <= GET_NULL; when others => rx_state <= GET_UNKNOWN; end case; @@ -272,12 +265,20 @@ begin rx_rst_i <= '1'; rx_rst_word_i <= reg_rx_data_in; rx_state <= FIRST; - + + -- QUICK HACK + when GET_NULL => + rx_state_bits <= x"8"; + if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_NULL) ) then + rx_state <= SLEEP; + else + rx_state <= FIRST; + end if; + end case; -- BUG: master ports don't reset correctly if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then --- if( (RESET = '1') ) then rx_state <= SLEEP; rx_dlm_word_i <= x"00"; rx_rst_word_i <= x"00"; @@ -346,7 +347,8 @@ begin LINK_HALF_DONE_OUT <= idle0_detected; LINK_FULL_DONE_OUT <= idle1_detected; - + LINK_RX_NULL_OUT <= rst_link_state; + ---------------------------------------------------------------------- -- Debug and Status ---------------------------------------------------------------------- diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index 99d6032..61bfbb5 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -37,6 +37,7 @@ entity tx_control_RS is LINK_RX_READY_IN : in std_logic; -- local ref clock LINK_HALF_DONE_IN : in std_logic; -- recovered RX clock LINK_FULL_DONE_IN : in std_logic; -- recovered RX clock + LINK_TX_NULL_IN : in std_logic; -- debug DEBUG_OUT : out std_logic_vector(31 downto 0); STAT_REG_OUT : out std_logic_vector(31 downto 0) @@ -97,21 +98,17 @@ architecture arch of tx_control_RS is signal link_active_int : std_logic; signal link_active_qtx : std_logic; signal link_active_qsys : std_logic; + signal link_tx_null_qtx : std_logic; signal tx_k_i : std_logic; signal tx_data_i : std_logic_vector(7 downto 0); --- attribute syn_keep : boolean; --- attribute syn_preserve : boolean; --- attribute syn_keep of word_sync_i : signal is true; --- attribute syn_preserve of word_sync_i : signal is true; - begin -- Sync SYNC_STATUS_SIGS : entity work.signal_sync generic map( - WIDTH => 4, + WIDTH => 5, DEPTH => 3 ) port map( @@ -122,10 +119,12 @@ begin D_IN(1) => LINK_RX_READY_IN, D_IN(2) => LINK_HALF_DONE_IN, D_IN(3) => LINK_FULL_DONE_IN, + D_IN(4) => LINK_TX_NULL_IN, D_OUT(0) => link_tx_ready_qtx, D_OUT(1) => link_rx_ready_qtx, D_OUT(2) => link_half_done_qtx, - D_OUT(3) => link_full_done_qtx + D_OUT(3) => link_full_done_qtx, + D_OUT(4) => link_tx_null_qtx ); -- Payload is only allowed on fully active links @@ -279,8 +278,7 @@ begin when IDLE => tx_k_i <= '1'; tx_data_i <= K_NULL; --- word_sync_i <= '0'; - if( link_tx_ready_qtx = '1' ) then + if( (link_tx_ready_qtx = '1') and (link_tx_null_qtx = '0') ) then current_state <= SEND_IDLE_L; else current_state <= IDLE; @@ -339,10 +337,8 @@ begin if( (current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or (current_state = SEND_DLM_H) or (current_state = SEND_RST_H) ) then --- if ( link_active_qtx = '0' ) then --- current_state <= SEND_IDLE_L; - if ( link_tx_ready_qtx = '0' ) then - current_state <= IDLE; -- stay in reset until TX is possible + if ( (link_tx_ready_qtx = '0') or (link_tx_null_qtx = '1') ) then + current_state <= IDLE; elsif( send_dlm_i = '1' ) then current_state <= SEND_DLM_L; elsif( send_rst_i = '1' ) then @@ -378,27 +374,6 @@ begin send_dlm_i <= SEND_DLM_IN when rising_edge(CLK_TXI); send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI); ---Send DLM message --- THE_STORE_DLM_PROC: process( CLK_TXI, RESET ) --- begin --- if( RESET = '1' ) then --- send_dlm_i <= '0'; --- send_dlm_word_i <= (others => '0'); --- elsif( rising_edge(CLK_TXI) ) then --- if ( link_active_qtx = '0' ) then --- send_dlm_i <= '0'; --- send_dlm_word_i <= (others => '0'); --- elsif( SEND_DLM_IN = '1' ) then --- send_dlm_i <= '1'; --- send_dlm_word_i <= SEND_DLM_WORD_IN; --- elsif( current_state = SEND_DLM_L ) then --- send_dlm_i <= '0'; --- elsif( current_state = SEND_DLM_H ) then --- send_dlm_word_i <= (others => '0'); --- end if; --- end if; --- end process THE_STORE_DLM_PROC; - -- Send RST message -- UNTESTED THE_STORE_RST_PROC: process( CLK_TXI, RESET )