From: Michael Boehmer Date: Fri, 15 Jul 2022 21:29:37 +0000 (+0200) Subject: DHCP / SCTRL better now, internal SCTRL endpoint now on sniffer port X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c33e8b5576892b068a1ca62d0dab80177e48fbaa;p=trbnet.git DHCP / SCTRL better now, internal SCTRL endpoint now on sniffer port --- diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd index c56e6de..b864b20 100644 --- a/gbe_trb/base/gbe_logic_wrapper.vhd +++ b/gbe_trb/base/gbe_logic_wrapper.vhd @@ -30,25 +30,13 @@ entity gbe_logic_wrapper is MY_IP_OUT : out std_logic_vector(31 downto 0); MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0); ISSUE_REBOOT_OUT : out std_logic; - -- connection to MAC + -- connection to MAC (link handling) MAC_READY_CONF_IN : in std_logic; MAC_RECONF_OUT : out std_logic; MAC_AN_READY_IN : in std_logic; - MAC_FIFOAVAIL_OUT : out std_logic; - MAC_FIFOEOF_OUT : out std_logic; - MAC_FIFOEMPTY_OUT : out std_logic; - MAC_RX_FIFOFULL_OUT : out std_logic; --- MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0); --- MAC_TX_READ_IN : in std_logic; --- MAC_TX_DISCRFRM_IN : in std_logic; --- MAC_TX_STAT_EN_IN : in std_logic; --- MAC_TX_STATS_IN : in std_logic_vector(30 downto 0); --- MAC_TX_DONE_IN : in std_logic; --- MAC_RX_FIFO_ERR_IN : in std_logic; --- MAC_RX_STATS_IN : in std_logic_vector(31 downto 0); + -- TSMAC RX stuff MAC_RX_DATA_IN : in std_logic_vector(7 downto 0); MAC_RX_WRITE_IN : in std_logic; - MAC_RX_STAT_EN_IN : in std_logic; MAC_RX_EOF_IN : in std_logic; MAC_RX_ERROR_IN : in std_logic; -- FIFO TX stuff @@ -546,10 +534,6 @@ begin MAC_RX_ER_IN => MAC_RX_ERROR_IN, MAC_RXD_IN => MAC_RX_DATA_IN, MAC_RX_EN_IN => MAC_RX_WRITE_IN, - MAC_RX_FIFO_ERR_IN => '0', -- UNUSED - MAC_RX_FIFO_FULL_OUT => MAC_RX_FIFOFULL_OUT, - MAC_RX_STAT_EN_IN => MAC_RX_STAT_EN_IN, - MAC_RX_STAT_VEC_IN => (others => '0'), -- output signal to control logic FR_Q_OUT => fr_q, FR_RD_EN_IN => fr_rd_en, diff --git a/gbe_trb/base/gbe_wrapper_fifo.vhd b/gbe_trb/base/gbe_wrapper_fifo.vhd index 3c82b4d..13375d8 100644 --- a/gbe_trb/base/gbe_wrapper_fifo.vhd +++ b/gbe_trb/base/gbe_wrapper_fifo.vhd @@ -26,7 +26,7 @@ entity gbe_wrapper_fifo is RESET : in std_logic; GSR_N : in std_logic; -- we connect to FIFO interface directly - -- FIFO interface RX + -- FIFO interface TX (send frames) FIFO_DATA_OUT : out std_logic_vector(8 downto 0); FIFO_FULL_IN : in std_logic; FIFO_WR_OUT : out std_logic; @@ -34,11 +34,11 @@ entity gbe_wrapper_fifo is FRAME_ACK_OUT : out std_logic; FRAME_AVAIL_OUT : out std_logic; FRAME_START_OUT : out std_logic; - -- FIFO interface TX - FIFO_FULL_OUT : out std_logic; - FIFO_WR_IN : in std_logic; - FIFO_DATA_IN : in std_logic_vector(8 downto 0); - FRAME_START_IN : in std_logic; + -- FIFO interface RX (receive frames) + MAC_RX_DATA_IN : in std_logic_vector(7 downto 0); + MAC_RX_WRITE_IN : in std_logic; + MAC_RX_EOF_IN : in std_logic; + MAC_RX_ERROR_IN : in std_logic; -- PCS_AN_READY_IN : in std_logic; LINK_ACTIVE_IN : in std_logic; @@ -194,9 +194,6 @@ architecture RTL of gbe_wrapper_fifo is signal my_ip : std_logic_vector(127 downto 0); signal debug : std_logic_vector(127 downto 0); - signal frame_active : std_Logic; - signal frame_written : std_logic; - signal rx_fifo_wr : std_logic; signal frame_requested : std_logic; signal fifo_empty : std_logic; signal fifo_data : std_logic_vector(8 downto 0); @@ -213,28 +210,6 @@ architecture RTL of gbe_wrapper_fifo is begin - ------------------------------------------------------------------------------------------------- - -- HACK: adopt the RX part for internal GbE hub - - -- FrameActice signal - used to inhibit acceptance of runt frames - THE_FRAME_ACTIVE_PROC: process( CLK_125_IN ) - begin - if( rising_edge(CLK_125_IN) ) then - if ( RESET = '1' ) then - frame_active <= '0'; - elsif( FRAME_START_IN = '1' ) then - frame_active <= LINK_ACTIVE_IN; - elsif( frame_written = '1' ) then - frame_active <= '0'; - end if; - end if; - end process THE_FRAME_ACTIVE_PROC; - - -- one frame written to FIFO - frame_written <= '1' when (FIFO_DATA_IN(8) = '1') and (FIFO_WR_IN = '1') and (frame_active = '1') else '0'; - - rx_fifo_wr <= FIFO_WR_IN and frame_active; - ------------------------------------------------------------------------------------------------- -- HACK: replace the borken internal FIFO by a ring buffer THE_FRAME_TX: entity rx_rb @@ -295,26 +270,14 @@ begin MY_IP_OUT => my_ip(31 downto 0), MY_TRBNET_ADDRESS_IN => MY_TRBNET_ADDRESS_IN, ISSUE_REBOOT_OUT => issue_reboot, - MAC_READY_CONF_IN => LINK_ACTIVE_IN, -- NEEDED - MAC_RECONF_OUT => open, -- NEEDED - MAC_AN_READY_IN => PCS_AN_READY_IN, -- NEEDED - MAC_FIFOAVAIL_OUT => open, -- NEEDED - MAC_FIFOEOF_OUT => open, -- NEEDED - MAC_FIFOEMPTY_OUT => open, -- NEEDED - MAC_RX_FIFOFULL_OUT => FIFO_FULL_OUT, -- NEEDED -- BUG: check level --- MAC_TX_DATA_OUT => open, -- NEEDED --- MAC_TX_READ_IN => '0', -- NEEDED --- MAC_TX_DISCRFRM_IN => '0', -- NEEDED --- MAC_TX_STAT_EN_IN => '0', -- NEEDED --- MAC_TX_STATS_IN => (others => '0'), -- NEEDED --- MAC_TX_DONE_IN => '0', -- NEEDED --- MAC_RX_FIFO_ERR_IN => '0', -- NEEDED --- MAC_RX_STATS_IN => (others => '0'), -- done - MAC_RX_DATA_IN => FIFO_DATA_IN(7 downto 0), -- NEEDED - MAC_RX_WRITE_IN => rx_fifo_wr, -- NEEDED - MAC_RX_STAT_EN_IN => '0', -- NEEDED - MAC_RX_EOF_IN => FIFO_DATA_IN(8), -- NEEDED - MAC_RX_ERROR_IN => '0', -- NEEDED + MAC_READY_CONF_IN => LINK_ACTIVE_IN, + MAC_RECONF_OUT => open, + MAC_AN_READY_IN => PCS_AN_READY_IN, +---- + MAC_RX_DATA_IN => MAC_RX_DATA_IN, --FIFO_DATA_IN(7 downto 0), + MAC_RX_WRITE_IN => MAC_RX_WRITE_IN, --rx_fifo_wr, + MAC_RX_EOF_IN => MAC_RX_EOF_IN, --FIFO_DATA_IN(8), + MAC_RX_ERROR_IN => MAC_RX_ERROR_IN, --'0', ---- -- FIFO TX stuff FT_TX_DATA_OUT => ft_tx_data, diff --git a/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd b/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd index 697645b..97a5f82 100644 --- a/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd +++ b/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd @@ -35,10 +35,6 @@ port ( MAC_RX_ER_IN : in std_logic; -- only for statistics MAC_RXD_IN : in std_logic_vector(7 downto 0); -- RX data MAC_RX_EN_IN : in std_logic; -- write signal - MAC_RX_FIFO_ERR_IN : in std_logic; -- UNUSED - MAC_RX_FIFO_FULL_OUT : out std_logic; -- not really needed - MAC_RX_STAT_EN_IN : in std_logic; -- UNUSED - MAC_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); -- UNUSED -- output signal to control logic FR_Q_OUT : out std_logic_vector(8 downto 0); FR_RD_EN_IN : in std_logic; @@ -533,7 +529,6 @@ begin fifo_wr_en <= '0'; end if; - MAC_RX_FIFO_FULL_OUT <= rec_fifo_full; end if; end process THE_RX_FIFO_SYNC; diff --git a/gbe_trb/base/trb_net_gbe_components.vhd b/gbe_trb/base/trb_net_gbe_components.vhd index 1d214a7..db2d20f 100644 --- a/gbe_trb/base/trb_net_gbe_components.vhd +++ b/gbe_trb/base/trb_net_gbe_components.vhd @@ -597,10 +597,6 @@ port ( MAC_RX_ER_IN : in std_logic; MAC_RXD_IN : in std_logic_vector(7 downto 0); MAC_RX_EN_IN : in std_logic; - MAC_RX_FIFO_ERR_IN : in std_logic; - MAC_RX_FIFO_FULL_OUT : out std_logic; - MAC_RX_STAT_EN_IN : in std_logic; - MAC_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); -- output signal to control logic FR_Q_OUT : out std_logic_vector(8 downto 0); FR_RD_EN_IN : in std_logic; diff --git a/gbe_trb_ecp5/media/gbe_med_fifo_single.vhd b/gbe_trb_ecp5/media/gbe_med_fifo_single.vhd index f69acdf..3f611dc 100644 --- a/gbe_trb_ecp5/media/gbe_med_fifo_single.vhd +++ b/gbe_trb_ecp5/media/gbe_med_fifo_single.vhd @@ -33,6 +33,11 @@ entity gbe_med_fifo_single is SD_PRSNT_N_IN : in std_logic := '1'; SD_LOS_IN : in std_logic := '1'; SD_TXDIS_OUT : out std_logic; + -- internal sniffer port + MAC_RX_DATA_OUT : out std_logic_vector(7 downto 0); + MAC_RX_WRITE_OUT : out std_logic; + MAC_RX_EOF_OUT : out std_logic; + MAC_RX_ERROR_OUT : out std_logic; -- Status PCS_AN_READY_OUT : out std_logic; -- for internal SCTRL LINK_ACTIVE_OUT : out std_logic; -- for internal SCTRL @@ -483,6 +488,11 @@ begin rx_error => mac_rx_err ); + MAC_RX_DATA_OUT <= mac_rx_data; + MAC_RX_WRITE_OUT <= mac_rx_wr; + MAC_RX_EOF_OUT <= mac_rx_eof; + MAC_RX_ERROR_OUT <= mac_rx_err; + TSMAC_CONTROLLER : trb_net16_gbe_mac_control port map( CLK => CLK_125,