From: hadeshyp Date: Wed, 30 Jun 2010 13:41:22 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c3ec8c8eb0fe56de72475a8b8781df8f9b2555b4;p=daqdocu.git *** empty log message *** --- diff --git a/mdc.tex b/mdc.tex index ecc4479..6222764 100755 --- a/mdc.tex +++ b/mdc.tex @@ -11,11 +11,11 @@ The schematics of the MDC OEP v3 can be found in \cite{MDCOEP}. The schematics o \textbf{Bit} & \textbf{Debug Format} & \textbf{Compressed Format} & \textbf{Status Word} \\ \hline \hline -31 & 0 & 1 & 0\\ +31 & 0 & 1 & 0 \\ 30 & 0 & 0 & 1 \\ -29 & \multicolumn{3}{c|}{reserved}\\ -28 .. 25 & \multicolumn{2}{c|}{TDC number} & status data \\ -24 .. 22 & \multicolumn{2}{c|}{TDC channel} & status data \\ +29 & 0 & 0 & 0 \\ +28 .. 25 & TDC number & TDC number & status data \\ +24 .. 22 & TDC channel & TDC channel & status data \\ 21 .. 11 & Bit 21: Hit number, rest 0 & ADC data - Hit 1 & status data \\ 10 .. 0 & ADC data & ADC data - Hit 0 & status data \\ \hline @@ -51,6 +51,103 @@ E000 & TDC Readback Fifo & Fifo for readback values from TDC \\ \end{center} \end{table} +\subsubsection{Common Registers} +The bits of the common status and control registers used in the OEP are listed in tables \ref{MDCCommonCtrlReg0}, \ref{MDCCommonCtrlReg2} and \ref{MDCCommonStatReg0}. The MDC-specific control registers are shown in table \ref{MDCControlRegisters}. + +\begin{table} +\begin{center} +\begin{tabular}{|c|l|l|} +\hline +\textbf{Bits} & \textbf{Description} & \textbf{MDC} \\ +\hline\hline +31 -- 20 & temperature & temperature\\ +19 -- 13 & reserved & n/a\\ +12 & Last event on IPU is broken & n/a\\ +11 & Error in data buffer / IPU handler & see ipu handler\\ +10 & IPU event data missing & see ipu handler\\ +9 & IPU Event not found & see ipu handler\\ +8 & Timing trigger missing & see endpoint\\ +7 & Frontend error & token not back\\ +6 & Frontend not configured & MBO not configured\\ +5 & IPU channel counter mismatch & n/a\\ +4 & LVL1 trigger counter mismatch & see endpoint\\ +3 & note flag & n/a\\ +2 & warning flag & n/a \\ +1 & error flag & n/a\\ +0 & serious error flag & n/a\\ +\hline +\end{tabular} +\caption{Common Status Register 0 (CSR0) on MDC OEP} +\label{MDCCommonStatReg0} +\end{center} +\end{table} + + +\begin{table} +\begin{center} +\begin{tabular}{|c|l|l|} +\hline +\textbf{Bits} & \textbf{Description} & \textbf{MDC} \\ +\hline\hline +31 -- 24 & user defined & n/a \\ +23 & End Run trigger & n/a\\ +22 & Begin Run trigger & Initialize MBO / TDC\\ +21 -- 20 & reserved & n/a\\ +19 -- 16 & dummy timing triggers & 16: sim. timing trigger\\ +15 & reboot FPGA & reboot OEP\\ +14 -- 11 & reserved & n/a\\ +10 & reset sequence counter & reset seq. counter\\ +9 -- 4 & reserved & n/a\\ +3 & master reset & n/a\\ +2 & empty IPU chain / reset IPU logic & reset IPU\\ +1 & reset trigger logic & reset readout logic\\ +0 & reset frontends & reset MBO \\ +\hline +\end{tabular} +\caption{Common Control Register 0 (CCR0) on MDC OEP. All bits are strobe signals.} +\label{MDCCommonCtrlReg0} +\end{center} +\end{table} + + +\begin{table} +\begin{center} +\begin{tabular}{|c|l|l|} +\hline +\textbf{Bits} & \textbf{Description} & \textbf{MDC}\\ +\hline\hline +31 & enable trigger & enable common stop input\\ +30 & enable debug & enable sending debug data\\ +29 -- 24 & reserved & n/a\\ +23 -- 22 & data format & n.a.\\ +21 & data format & 0: normal, 1: dummy data \\ +20 & data format & 0: compressed, 1: long data format \\ +19 -- 16 & reserved & n.a.\\ +15 -- 0 & enable frontends & n.a.\\ +\hline +\end{tabular} +\caption{Common Control Register 2 (CCR2) on MDC OEP} +\label{MDCCommonCtrlReg2} +\end{center} +\end{table} + +\begin{table} +\begin{center} +\begin{tabular}{|c|l|l|} +\hline +\textbf{Reg.} & \textbf{Bit} & \textbf{Description}\\ +\hline\hline +C0 & 5 -- 4 & 1: short MBO, 2: long MBO\\ +C1 & 27 -- 16 & Number of dummy data words (if enabled)\\ +\hline +\end{tabular} +\caption{Control Registers on MDC OEP} +\label{MDCControlRegisters} +\end{center} +\end{table} + + + \subsubsection{MDC Optical Endpoint Voltage Monitoring} The ADC monitoring most voltages on each OEP can be accessed using register addresses 0x8000 to 0x803F. The memory map is given in table \ref{MDCOEPADCMemoryMap}, the voltages connected in table \ref{MDCOEPADCChannels}. @@ -97,15 +194,20 @@ The ADC monitoring most voltages on each OEP can be accessed using register addr \subsubsection{MDC OEP Status Register} \begin{description} - \item[0x9000: \filename{Control} status register] + \item[0x9000: \filename{Control} status register]~ \begin{description} \item[Bit 0] Token Back \item[Bit 1] Token Missing \item[Bit 2] CMS active \end{description} - \item[0x9001: \filename{Trigger\_Handler} status register] - \item[0x9002: \filename{Data\_Handler} status register] + + \item[0x9001: \filename{Trigger\_Handler} status register] ~ + \begin{description} + \item[Bit 3..0] State machine: 0: Idle, 1: Begrun, 2: timing trigger, 3: calibration trigger, 4: do readout + \end{description} + + \item[0x9002: \filename{Data\_Handler} status register]~ \begin{description} \item[Bit 3..0] State machine status \item[Bit 4] Start Readout @@ -118,7 +220,7 @@ The ADC monitoring most voltages on each OEP can be accessed using register addr \end{description} \item[0x9003: \filename{Tdc\_Readout} status register] The status register of the entity that reads data provided by the MBO. \begin{description} - \item[Bit 3..0] State machine status \\ 0: idle; 1: save\_L\_word, 2: send\_token, 3: wait\_1, 4: wait\_2, 5: save\_L\_word\_next. 6: wait\_for\_AOD\_low, 7: wait\_3, 8: wait\_4, 9: save\_H\_word\_state\_next + \item[Bit 3..0] State machine status \\ 0: idle; 1: save\_\-L\_\-word, 2: send\_\-token, 3: wait\_\-1, 4: wait\_\-2, 5: save\_\-L\_\-word\_\-next. 6: wait\_\-for\_\-AOD\_\-low, 7: wait\_\-3, 8: wait\_\-4, 9: save\_\-H\_\-word\_\-state\_\-next \item[Bit 4] Data valid out \item[Bit 5] Token back from MBO \item[Bit 6] \portname{A\_Dst\_In} @@ -126,7 +228,7 @@ The ADC monitoring most voltages on each OEP can be accessed using register addr \item[Bit 8] \portname{A\_Reserve\_In} \item[Bit 12..9] Lower four bits of trigger number - used to tag data in fifos \end{description} - \item[0x9004: \filename{Control\_Line\_Handler} status register] + \item[0x9004: \filename{Control\_Line\_Handler} status register]~ \begin{description} \item[Bit 3..0] State machine status \item[Bit 4] Finished Begrun Out diff --git a/slowcontrol.tex b/slowcontrol.tex index 19e22dc..f972614 100755 --- a/slowcontrol.tex +++ b/slowcontrol.tex @@ -366,7 +366,7 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}. 0 & reset frontends \\ \hline \end{tabular} -\caption{Common Control Register 0 (CCR1). All bits are strobe signals.} +\caption{Common Control Register 0 (CCR0). All bits are strobe signals.} \label{CommonCtrlReg0} \end{center} \end{table}