From: HADES DAQ Date: Thu, 30 Nov 2023 14:39:28 +0000 (+0100) Subject: added invert functionality for trigger output signals, mt X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c43c9b87c3ca8f5db68b8a70acfa9c0d937b7b20;p=dirich.git added invert functionality for trigger output signals, mt --- diff --git a/dirich5d1/code/wide_trigger_output.vhd b/dirich5d1/code/wide_trigger_output.vhd new file mode 100644 index 0000000..3d3a4fe --- /dev/null +++ b/dirich5d1/code/wide_trigger_output.vhd @@ -0,0 +1,76 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; +library work; + use work.trb_net_std.all; + use work.config.all; + + +entity wide_trigger_output is +generic( + INPUT_WIDTH : integer := NUM_TDC_CHANNELS - 1 +); +port( + CLK : in std_logic; + RESET : in std_logic; + + INPUT : in std_logic_vector(INPUT_WIDTH downto 1); + OUTPUT : out std_logic_vector(INPUT_WIDTH downto 1); + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX +); +end entity; + +architecture behaviour of wide_trigger_output is + signal input_or_stretched : std_logic; + signal input_inv : std_logic_vector(INPUT_WIDTH-1 downto 0); + signal invert : std_logic_vector(31 downto 0) := x"00000000"; + signal enable : std_logic_vector(31 downto 0) := x"00000000"; + signal stretch : std_logic_vector( 3 downto 0) := x"0"; + signal stretched_input : std_logic_vector(INPUT_WIDTH-1 downto 0) := (others => '0'); + +begin + + OUTPUT <= ((INPUT xor invert(INPUT_WIDTH downto 1)) and enable(INPUT_WIDTH downto 1)); + + proc_reg : process + variable stretch_check : std_logic_vector(3 downto 0) := x"0"; + begin + wait until rising_edge(CLK); + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.unknown <= '0'; + + if BUS_RX.write = '1' then + BUS_TX.ack <= '1'; + case BUS_RX.addr(1 downto 0) is + when "00" => + stretch <= BUS_RX.data(3 downto 0); + + when "01" => + invert <= BUS_RX.data; + when "10" => + enable <= BUS_RX.data; + + when others => + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + end case; + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + case BUS_RX.addr(1 downto 0) is + when "00" => BUS_TX.data(3 downto 0) <= stretch; + + when "01" => BUS_TX.data <= invert; + + when "10" => BUS_TX.data <= enable; + + when others => BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + end case; + end if; + end process; + +end architecture; + diff --git a/dirich5d1/dirich5d1.prj b/dirich5d1/dirich5d1.prj index 45065a5..28bad66 100644 --- a/dirich5d1/dirich5d1.prj +++ b/dirich5d1/dirich5d1.prj @@ -228,7 +228,7 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in200_out50/pll_in20 ### Triggering add_file -vhdl -lib work "./code/stretched_OR_trigger.vhd" add_file -vhdl -lib work "../dirich/code/input_signal_stretcher.vhd" - +add_file -vhdl -lib work "./code/wide_trigger_output.vhd" add_file -vhdl -lib work "./dirich5d1.vhd" diff --git a/dirich5d1/dirich5d1.vhd b/dirich5d1/dirich5d1.vhd index 506b80c..ad5ca51 100644 --- a/dirich5d1/dirich5d1.vhd +++ b/dirich5d1/dirich5d1.vhd @@ -57,7 +57,7 @@ entity dirich5d1 is SCLK_OUT : out std_logic_vector(1 downto 0); CS_OUT : out std_logic_vector(1 downto 0); - SIG_OUT : out std_logic_vector(32 downto 1) + SIG_OUT : out std_logic_vector(NUM_TDC_CHANNELS-1 downto 1) --Test Connectors @@ -96,8 +96,8 @@ architecture dirich5d1_arch of dirich5d1 is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); - signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in , busOrTrigger_tx : CTRLBUS_TX; - signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busOrTrigger_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in , busOrTrigger_tx, busWideTriggerOutput_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busOrTrigger_rx, busWideTriggerOutput_rx : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -283,9 +283,9 @@ THE_CAL_PLL : entity work.pll_in200_out50 THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 6, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", 5 => x"e000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, 5 => 2, others => 0), + PORT_NUMBER => 7, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", 5 => x"e000", 6 => x"e010", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, 5 => 2, 6 => 2, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -301,12 +301,14 @@ THE_CAL_PLL : entity work.pll_in200_out50 BUS_RX(3) => busthresh_rx, BUS_RX(4) => bustdc_rx, BUS_RX(5) => busOrTrigger_rx, + BUS_RX(6) => busWideTriggerOutput_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => busthresh_tx, BUS_TX(4) => bustdc_tx, BUS_TX(5) => busOrTrigger_tx, + BUS_TX(6) => busWideTriggerOutput_tx, STAT_DEBUG => open ); @@ -396,7 +398,21 @@ THE_CAL_PLL : entity work.pll_in200_out50 -- ); - SIG_OUT(8 downto 1) <= INPUT(8 downto 1); + + THE_WIDE_TRIGGER_OUTPUT: entity work.wide_trigger_output + port map ( + CLK => clk_sys, + RESET => reset_i, + + INPUT => INPUT(NUM_TDC_CHANNELS- 1 downto 1), + OUTPUT => SIG_OUT(NUM_TDC_CHANNELS-1 downto 1), + + BUS_RX => busWideTriggerOutput_rx, + BUS_TX => busWideTriggerOutput_tx + ); + + +-- SIG_OUT(8 downto 1) <= INPUT(8 downto 1); ---------------------------------------------------------------------------