From: Peter Lemmens <p.j.j.lemmens@rug.nl>
Date: Wed, 23 Oct 2013 14:06:12 +0000 (+0200)
Subject: status: trbnet working when no soda traffic (K_DLMs) interfering.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c50740a703977271515a1df4812f74405e568e28;p=soda.git

status: trbnet working when no soda traffic (K_DLMs) interfering.
Maybe tx-control or rx-control FSM not working properly.
When no K_DLMs: disconnect can lead to trb-connectionloss; "trbcmd reset" can solve this

Soda traffic arbiter added (soda_cmd_window_generator)
---

diff --git a/soda_client.ldf b/soda_client.ldf
index 4e9700b..91c2d36 100644
--- a/soda_client.ldf
+++ b/soda_client.ldf
@@ -4,7 +4,7 @@
         <Option name="HDL type" value="VHDL"/>
     </Options>
     <Implementation title="soda_client" dir="soda_client" description="soda_client" default_strategy="Strategy1">
-        <Options top="trb3_periph_sodaclient"/>
+        <Options def_top="trb3_periph_sodaclient" top="trb3_periph_sodaclient"/>
         <Source name="source/version.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
@@ -47,6 +47,9 @@
         <Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
+        <Source name="source/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
         <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
@@ -287,9 +290,6 @@
         <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../trbnet/media_interfaces/sync/tx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
         <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
diff --git a/soda_source.ldf b/soda_source.ldf
index 8455f12..fbf8ae4 100644
--- a/soda_source.ldf
+++ b/soda_source.ldf
@@ -314,6 +314,9 @@
         <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
+        <Source name="source/soda_cmd_window_generator.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
         <Source name="soda_source.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>
diff --git a/soda_source.lpf b/soda_source.lpf
index 8a14f16..ecba527 100644
--- a/soda_source.lpf
+++ b/soda_source.lpf
@@ -1,4 +1,4 @@
-rvl_alias "clk_raw_internal" "clk_raw_internal";
+rvl_alias "reveal_ist_222" "the_sync_link/the_serdes/rx_full_clk_ch0";
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
 BLOCK RD_DURING_WR_PATHS ;
diff --git a/source/med_ecp3_sfp_sync_down.vhd b/source/med_ecp3_sfp_sync_down.vhd
index 378b7c7..4875f2b 100644
--- a/source/med_ecp3_sfp_sync_down.vhd
+++ b/source/med_ecp3_sfp_sync_down.vhd
@@ -325,7 +325,7 @@ THE_TX : soda_tx_control
 		START_POSITION_IN			=> request_retr_position_i,    --TODO
 
 		TX_DLM_INIT					=>	TX_DLM_INIT,
-		SEND_DLM						=> TX_DLM,
+		SEND_DLM						=> '0',	--TX_DLM,
 		SEND_DLM_WORD				=> TX_DLM_WORD,
 
 		SEND_LINK_RESET_IN		=> CTRL_OP(15),
@@ -343,7 +343,7 @@ LINK_PHASE_OUT		<= link_phase_S;		--PL!
 -------------------------------------------------             
 THE_RX_CONTROL : rx_control
   port map(
-    CLK_200                        => clk_200_i,
+    CLK_200                        => clk_rx_full,	--clk_200_i, PL!
     CLK_100                        => SYSCLK,
     RESET_IN                       => rst,		--CLEAR, PL!
 
diff --git a/source/med_ecp3_sfp_sync_up.vhd b/source/med_ecp3_sfp_sync_up.vhd
index f0052aa..369cd54 100644
--- a/source/med_ecp3_sfp_sync_up.vhd
+++ b/source/med_ecp3_sfp_sync_up.vhd
@@ -9,61 +9,62 @@ library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.med_sync_define.all;
+use work.soda_components.all;
 
 entity med_ecp3_sfp_sync_up is
-  generic(
-    SERDES_NUM : integer range 0 to 3 := 0;
---     MASTER_CLOCK_SWITCH : integer := c_NO;   --just for debugging, should be NO
-    IS_SYNC_SLAVE   : integer := c_YES       --select slave mode
-    );
-  port(
-    CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
-    SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
-    RESET              : in  std_logic; -- synchronous reset
-    CLEAR              : in  std_logic; -- asynchronous reset
-    --Internal Connection TX
-    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
-    MED_DATAREADY_IN   : in  std_logic;
-    MED_READ_OUT       : out std_logic := '0';
-    --Internal Connection RX
-    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
-    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
-    MED_DATAREADY_OUT  : out std_logic := '0';
-    MED_READ_IN        : in  std_logic;
-    CLK_RX_HALF_OUT    : out std_logic := '0';  --received 100 MHz
-    CLK_RX_FULL_OUT    : out std_logic := '0';  --received 200 MHz
-    
-    --Sync operation
-    RX_DLM             : out std_logic := '0';
-    RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
-    TX_DLM             : in  std_logic := '0';
-    TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
-    
-    --SFP Connection
-    SD_RXD_P_IN        : in  std_logic;
-    SD_RXD_N_IN        : in  std_logic;
-    SD_TXD_P_OUT       : out std_logic;
-    SD_TXD_N_OUT       : out std_logic;
-    SD_REFCLK_P_IN     : in  std_logic;  --not used
-    SD_REFCLK_N_IN     : in  std_logic;  --not used
-    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-    SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
-    --Control Interface
-    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
-    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
-    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
-    SCI_READ           : in  std_logic := '0';
-    SCI_WRITE          : in  std_logic := '0';
-    SCI_ACK            : out std_logic := '0';
-    SCI_NACK           : out std_logic := '0';
-    -- Status and control port
-    STAT_OP            : out std_logic_vector (15 downto 0);
-    CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
-    STAT_DEBUG         : out std_logic_vector (63 downto 0);
-    CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
-   );
+	generic(	SERDES_NUM				: integer range 0 to 3 := 0;
+			--	MASTER_CLOCK_SWITCH	: integer := c_NO;   --just for debugging, should be NO
+				IS_SYNC_SLAVE			: integer := c_YES);       --select slave mode
+	port(
+		CLK                : in  std_logic; -- _internal_ 200 MHz reference clock
+		SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
+		RESET              : in  std_logic; -- synchronous reset
+		CLEAR              : in  std_logic; -- asynchronous reset
+		--Internal Connection TX
+		MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+		MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+		MED_DATAREADY_IN   : in  std_logic;
+		MED_READ_OUT       : out std_logic := '0';
+		--Internal Connection RX
+		MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+		MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+		MED_DATAREADY_OUT  : out std_logic := '0';
+		MED_READ_IN        : in  std_logic;
+		CLK_RX_HALF_OUT    : out std_logic := '0';  --received 100 MHz
+		CLK_RX_FULL_OUT    : out std_logic := '0';  --received 200 MHz
+
+		--Sync operation
+		RX_DLM             : out std_logic := '0';
+		RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
+		TX_DLM             : in  std_logic := '0';
+		TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
+		TX_DLM_INIT				: in std_logic := '0';	--PL!
+		LINK_PHASE_OUT			: out	std_logic := '0';	--PL!
+
+		--SFP Connection
+		SD_RXD_P_IN        : in  std_logic;
+		SD_RXD_N_IN        : in  std_logic;
+		SD_TXD_P_OUT       : out std_logic;
+		SD_TXD_N_OUT       : out std_logic;
+		SD_REFCLK_P_IN     : in  std_logic;  --not used
+		SD_REFCLK_N_IN     : in  std_logic;  --not used
+		SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+		SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+		SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
+		--Control Interface
+		SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+		SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+		SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+		SCI_READ           : in  std_logic := '0';
+		SCI_WRITE          : in  std_logic := '0';
+		SCI_ACK            : out std_logic := '0';
+		SCI_NACK           : out std_logic := '0';
+		-- Status and control port
+		STAT_OP            : out std_logic_vector (15 downto 0);
+		CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
+		STAT_DEBUG         : out std_logic_vector (63 downto 0);
+		CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
+	);
 end entity;
 
 
@@ -76,6 +77,7 @@ architecture med_ecp3_sfp_sync_up_arch of med_ecp3_sfp_sync_up is
   attribute syn_sharing : string;
   attribute syn_sharing of med_ecp3_sfp_sync_up_arch : architecture is "off";
 
+
 
 component DCS
 -- synthesis translate_off
@@ -93,7 +95,6 @@ DCSOUT :out std_logic) ;
 end component;
 
 
-
 signal clk_200_i         : std_logic;
 signal clk_200_internal  : std_logic;
 signal clk_rx_full       : std_logic;
@@ -108,12 +109,14 @@ signal rx_k              : std_logic;
 signal rx_error          : std_logic;
 
 signal rst_n             : std_logic;
+signal rst						: std_logic;		-- PL!
 signal rx_serdes_rst     : std_logic;
 signal tx_serdes_rst     : std_logic;
 signal tx_pcs_rst        : std_logic;
 signal rx_pcs_rst        : std_logic;
 signal rst_qd            : std_logic;
 signal serdes_rst_qd     : std_logic;
+signal sd_los_i          : std_logic;	--PL!
 
 signal rx_los_low        : std_logic;
 signal lsm_status        : std_logic;
@@ -137,6 +140,7 @@ signal tx_allow           : std_logic;
 signal rx_allow           : std_logic;
 signal tx_allow_q         : std_logic;
 signal rx_allow_q         : std_logic;
+signal link_phase_S			: std_logic;	--PL!
 signal request_retr_i     : std_logic;
 signal start_retr_i       : std_logic;
 signal request_retr_position_i  : std_logic_vector(7 downto 0);
@@ -170,7 +174,9 @@ CLK_RX_FULL_OUT <= clk_rx_full;
 SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
 
 
-rst_n <= not CLEAR;
+--rst_n <= not CLEAR;	PL!
+rst_n <= not (CLEAR or sd_los_i or internal_make_link_reset_out);
+rst   <=     (CLEAR or sd_los_i or internal_make_link_reset_out);
 
 
 gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
@@ -240,7 +246,7 @@ THE_SERDES : entity work.serdes_sync_upstream
 THE_RX_FSM : rx_reset_fsm
   port map(
     RST_N               => rst_n,
-    RX_REFCLK           => clk_200_internal,
+    RX_REFCLK           => clk_200_internal,		-- allways running PL!
     TX_PLL_LOL_QD_S     => tx_pll_lol,
     RX_SERDES_RST_CH_C  => rx_serdes_rst,
     RX_CDR_LOL_CH_S     => rx_cdr_lol,
@@ -253,7 +259,7 @@ THE_RX_FSM : rx_reset_fsm
 THE_TX_FSM : tx_reset_fsm
   port map(
     RST_N           => rst_n,
-    TX_REFCLK       => clk_200_internal,
+    TX_REFCLK       => clk_200_internal,			-- allways running PL!
     TX_PLL_LOL_QD_S => tx_pll_lol,
     RST_QD_C        => rst_qd,
     TX_PCS_RST_CH_C => tx_pcs_rst,
@@ -298,37 +304,40 @@ end process;
 -------------------------------------------------      
 -- TX Data
 -------------------------------------------------         
-THE_TX : tx_control
-  port map(
-    CLK_200                => clk_200_i,
-    CLK_100                => SYSCLK,
-    RESET_IN               => CLEAR,
+THE_TX : soda_tx_control
+	port map(
+		CLK_200						=> clk_200_i,
+		CLK_100						=> SYSCLK,
+		RESET_IN						=> rst,		--CLEAR, PL!
 
-    TX_DATA_IN             => MED_DATA_IN,
-    TX_PACKET_NUMBER_IN    => MED_PACKET_NUM_IN,
-    TX_WRITE_IN            => MED_DATAREADY_IN,
-    TX_READ_OUT            => MED_READ_OUT,
+		TX_DATA_IN					=> MED_DATA_IN,
+		TX_PACKET_NUMBER_IN		=> MED_PACKET_NUM_IN,
+		TX_WRITE_IN					=> MED_DATAREADY_IN,
+		TX_READ_OUT					=> MED_READ_OUT,
 
-    TX_DATA_OUT            => tx_data,
-    TX_K_OUT               => tx_k,
+		TX_DATA_OUT					=> tx_data,
+		TX_K_OUT						=> tx_k,
 
-    REQUEST_RETRANSMIT_IN  => request_retr_i,             --TODO
-    REQUEST_POSITION_IN    => request_retr_position_i,    --TODO
+		REQUEST_RETRANSMIT_IN	=> request_retr_i,             --TODO
+		REQUEST_POSITION_IN		=> request_retr_position_i,    --TODO
 
-    START_RETRANSMIT_IN    => start_retr_i,               --TODO
-    START_POSITION_IN      => request_retr_position_i,    --TODO
+		START_RETRANSMIT_IN		=> start_retr_i,               --TODO
+		START_POSITION_IN			=> request_retr_position_i,    --TODO
 
-    SEND_DLM               => TX_DLM,
-    SEND_DLM_WORD          => TX_DLM_WORD,
-    
-    SEND_LINK_RESET_IN     => CTRL_OP(15),
-    TX_ALLOW_IN            => tx_allow,
-    RX_ALLOW_IN            => rx_allow,
+		TX_DLM_INIT					=>	TX_DLM_INIT,
+		SEND_DLM						=> TX_DLM,
+		SEND_DLM_WORD				=> TX_DLM_WORD,
+
+		SEND_LINK_RESET_IN		=> CTRL_OP(15),
+		TX_ALLOW_IN					=> tx_allow,
+		RX_ALLOW_IN					=> rx_allow,
+		LINK_PHASE_OUT				=>	link_phase_S,		--PL!
 
-    DEBUG_OUT              => debug_tx_control_i,
-    STAT_REG_OUT           => stat_tx_control_i
-    );  
+		DEBUG_OUT					=> debug_tx_control_i,
+		STAT_REG_OUT				=> stat_tx_control_i
+);  
 
+LINK_PHASE_OUT		<= link_phase_S;		--PL!
 
 -------------------------------------------------      
 -- RX Data
@@ -337,7 +346,7 @@ THE_RX_CONTROL : rx_control
   port map(
     CLK_200                        => clk_200_i,
     CLK_100                        => SYSCLK,
-    RESET_IN                       => CLEAR,
+    RESET_IN                       => rst,		--CLEAR, PL!
 
     RX_DATA_OUT                    => MED_DATA_OUT,
     RX_PACKET_NUMBER_OUT           => MED_PACKET_NUM_OUT,
@@ -483,6 +492,7 @@ debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
 STAT_DEBUG <= debug_reg;
 
 internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
+sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK);	-- PL!
 
 
 STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
diff --git a/source/soda_SOB_faker.vhd b/source/soda_SOB_faker.vhd
index bd01282..e1e2427 100644
--- a/source/soda_SOB_faker.vhd
+++ b/source/soda_SOB_faker.vhd
@@ -12,8 +12,8 @@ use work.soda_components.all;
 
 entity soda_start_of_burst_faker is
 	generic(
-		cCLOCK_PERIOD	: natural range 1 to 20	:= 5;	-- clock-period in ns
-		cBURST_PERIOD	: natural := 2400					-- burst-period in ns
+		CLOCK_PERIOD			: natural range 1 to 20	:= cSODA_CLOCK_PERIOD;	-- clock-period in ns
+		BURST_PERIOD			: natural 					:= cBURST_PERIOD			-- burst-period in ns
 		);
 	port(
 		SYSCLK					: in	std_logic; -- fabric clock
@@ -24,7 +24,7 @@ end soda_start_of_burst_faker;
 
 architecture Behavioral of soda_start_of_burst_faker is
 
-	constant	cCLOCKS_PER_BURST			: std_logic_vector(15 downto 0)	:= conv_std_logic_vector((cBURST_PERIOD / cCLOCK_PERIOD) - 1, 16);
+	constant	cCLOCKS_PER_BURST			: std_logic_vector(15 downto 0)	:= conv_std_logic_vector((BURST_PERIOD / CLOCK_PERIOD) - 1, 16);
 
 	signal	burst_counter_S			: std_logic_vector(15 downto 0)	:= (others => '0');		-- from super-burst-nr-generator
 	
diff --git a/source/soda_cmd_window_generator.vhd b/source/soda_cmd_window_generator.vhd
new file mode 100644
index 0000000..fca0ea4
--- /dev/null
+++ b/source/soda_cmd_window_generator.vhd
@@ -0,0 +1,62 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all; 
+use work.soda_components.all;
+
+entity soda_cmd_window_generator is
+	generic(		CLOCK_PERIOD			: natural range 1 to 20	:= cSODA_CLOCK_PERIOD;				-- clock-period in ns
+					COMMAND_WINDOS_SIZE	: natural range 1 to 256 := cSODA_COMMAND_WINDOS_SIZE		-- command window size in ns 
+				);
+	port(
+		SODACLK						: in	std_logic; -- fabric clock
+		RESET							: in	std_logic; -- synchronous reset
+		START_OF_SUPERBURST_IN	: in	std_logic := '0';	-- 
+		SODA_CMD_WINDOW_OUT		: out	std_logic := '0'
+		);
+end soda_cmd_window_generator;
+
+architecture Behavioral of soda_cmd_window_generator is
+
+	constant	cWINDOW_delay				: std_logic_vector(7 downto 0)	:= conv_std_logic_vector(28, 8);													-- in clock-cycles
+	constant	cCLOCKS_PER_WINDOW		: std_logic_vector(15 downto 0)	:= conv_std_logic_vector((COMMAND_WINDOS_SIZE / CLOCK_PERIOD) - 1, 16);	-- in clock-cycles
+
+	signal	window_delay_counter_S	: std_logic_vector(7 downto 0)	:= (others => '0');		-- 
+	signal	window_size_counter_S	: std_logic_vector(15 downto 0)	:= (others => '0');		-- 
+	
+
+begin
+
+	
+	soda_cmd_window_proc : process(SODACLK)
+	begin
+		if rising_edge(SODACLK) then
+			if (RESET='1') then
+				window_delay_counter_S	<= (others => '0');
+				window_size_counter_S	<= (others => '0');
+				SODA_CMD_WINDOW_OUT		<= '0';
+			elsif (START_OF_SUPERBURST_IN = '1') then
+				window_delay_counter_S	<= cWINDOW_delay;
+			elsif (window_delay_counter_S > 0) then
+				window_delay_counter_S	<= window_delay_counter_S -1;
+			end if;
+			
+			if (window_delay_counter_S = 1) then
+				window_size_counter_S	<= cCLOCKS_PER_WINDOW;
+			elsif	(window_size_counter_S > 0) then
+				SODA_CMD_WINDOW_OUT		<= '1';
+				window_size_counter_S	<= window_size_counter_S - 1;
+			else
+				SODA_CMD_WINDOW_OUT	<= '0';
+			end if;
+
+		end if;
+	end process;
+
+end Behavioral;
diff --git a/source/soda_components.vhd b/source/soda_components.vhd
index 35decf0..fa081a8 100644
--- a/source/soda_components.vhd
+++ b/source/soda_components.vhd
@@ -9,9 +9,14 @@ use work.trb_net16_hub_func.all;
 
 package soda_components is
 
-	constant	c_NOT_IN_SYNC			: std_logic	:= '1';
-	constant	c_IN_SYNC				: std_logic	:= '0';
-	constant	c_HUB_CHILDREN			: natural range 1 to 4 := 2;
+	constant	c_NOT_IN_SYNC					: std_logic	:= '1';					-- byt2word allignment of soda
+	constant	c_IN_SYNC						: std_logic	:= '0';					-- byt2word allignment of soda
+	constant	c_HUB_CHILDREN					: natural range 1 to 4 := 2;		-- number of children per soda-hub
+	constant	cSODA_CLOCK_PERIOD			: natural range 1 to 20	:= 5;		-- soda clock-period in ns
+	constant	cBURST_PERIOD					: natural := 2400;						-- particle-beam burst-period in ns
+	constant	cSODA_COMMAND_WINDOS_SIZE	: natural range 1 to 65535 := 5000;   -- size of the window in which soda-cmds are allowed after a superburst-pulse in ns
+
+
 	type		t_HUB_DLM				is array(c_HUB_CHILDREN-1 downto 0) of std_logic;
 	type		t_HUB_DLM_WORD			is array(c_HUB_CHILDREN-1 downto 0) of std_logic_vector(7 downto 0);
 	type		t_PACKET_TYPE_SENT	is (c_NO_PACKET, c_CMD_PACKET, c_BST_PACKET);
@@ -241,8 +246,8 @@ package soda_components is
 
 	component soda_start_of_burst_faker
 		generic(
-			cCLOCK_PERIOD	: natural range 1 to 20		:= 5;		-- clock-period in ns
-			cBURST_PERIOD	: natural range 1	to 2400	:= 2400	-- burst-period in ns
+			CLOCK_PERIOD	: natural range 1 to 20		:= 5;		-- clock-period in ns
+			BURST_PERIOD	: natural range 1	to 2400	:= 2400	-- burst-period in ns
 			);
 		port(
 			SYSCLK					: in	std_logic; -- fabric clock
@@ -346,6 +351,8 @@ component med_ecp3_sfp_sync_up is
     RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
     TX_DLM             : in  std_logic := '0';
     TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
+		TX_DLM_INIT				: in std_logic := '0';	--PL!
+		LINK_PHASE_OUT			: out	std_logic := '0';	--PL!
 
     --SFP Connection
     SD_RXD_P_IN        : in  std_logic;
@@ -407,4 +414,16 @@ component soda_tx_control
     );
 end component;
 
+component soda_cmd_window_generator
+	generic(		CLOCK_PERIOD			: natural range 1 to 20	:= cSODA_CLOCK_PERIOD;				-- clock-period in ns
+					COMMAND_WINDOS_SIZE	: natural range 1 to 65335 := cSODA_COMMAND_WINDOS_SIZE		-- command window size in ns 
+				);
+	port(
+		SODACLK						: in	std_logic; -- fabric clock
+		RESET							: in	std_logic; -- synchronous reset
+		START_OF_SUPERBURST_IN	: in	std_logic := '0';	-- 
+		SODA_CMD_WINDOW_OUT		: out	std_logic := '0'
+		);
+end component;
+
 end package;
diff --git a/source/soda_packet_builder.vhd b/source/soda_packet_builder.vhd
index 81ff2fc..6e463d9 100644
--- a/source/soda_packet_builder.vhd
+++ b/source/soda_packet_builder.vhd
@@ -30,7 +30,8 @@ end soda_packet_builder;
 
 architecture Behavioral of soda_packet_builder is
 
-	signal	soda_cmd_strobe_S			: std_logic;
+	signal	soda_cmd_window_S			: std_logic;
+	signal	soda_cmd_strobe_S			: std_logic;
 	signal	super_burst_nr_S			: std_logic_vector(30 downto 0)	:= (others => '0');		-- from super-burst-nr-generator
 	signal	soda_cmd_word_S			: std_logic_vector(30 downto 0)	:= (others => '0');		-- from slowcontrol
 	signal	soda_pkt_word_S			: std_logic_vector(7 downto 0)	:= (others => '0');
@@ -308,5 +309,16 @@ begin
 			end case;		
 		end if;
 	end process;
-	
+
+cmd_window_gen : soda_cmd_window_generator
+	generic map(CLOCK_PERIOD			=> cSODA_CLOCK_PERIOD,				-- clock-period in ns
+					COMMAND_WINDOS_SIZE	=> cSODA_COMMAND_WINDOS_SIZE		-- command window size in ns 
+				)
+	port map(SODACLK						=>	SODACLK,
+				RESET							=>	RESET,
+				START_OF_SUPERBURST_IN	=>	START_OF_SUPERBURST,
+				SODA_CMD_WINDOW_OUT		=> soda_cmd_window_S
+				);
+
+
 end architecture;
\ No newline at end of file