From: Tobias Weber Date: Thu, 8 Aug 2013 13:47:53 +0000 (+0200) Subject: Removed Nxyter Constraints X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c58c7c84a418be794596b2a1a71797e5191ba104;p=trb3.git Removed Nxyter Constraints --- diff --git a/mupix/trb3_periph.prj b/mupix/trb3_periph.prj index 675fe06..65669a6 100644 --- a/mupix/trb3_periph.prj +++ b/mupix/trb3_periph.prj @@ -140,53 +140,4 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" -# nXyter Files - -#add_file -vhdl -lib "work" "cores/pll_125_hub.vhd" -add_file -vhdl -lib "work" "cores/pll_nx_clk256.vhd" -add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd" -add_file -vhdl -lib "work" "cores/pll_adc_clk32.vhd" -add_file -vhdl -lib "work" "cores/pll_adc_clk192.vhd" -add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd" -add_file -vhdl -lib "work" "cores/fifo_32_data.vhd" - -add_file -vhdl -lib "work" "trb3_periph.vhd" - -add_file -vhdl -lib "work" "source/nxyter_components.vhd" -add_file -vhdl -lib "work" "source/level_to_pulse.vhd" -add_file -vhdl -lib "work" "source/pulse_to_level.vhd" -add_file -vhdl -lib "work" "source/gray_decoder.vhd" -add_file -vhdl -lib "work" "source/gray_encoder.vhd" -add_file -vhdl -lib "work" "source/nx_timer.vhd" - -add_file -vhdl -lib "work" "source/nxyter_fee_board.vhd" -add_file -vhdl -lib "work" "source/nx_data_receiver.vhd" -add_file -vhdl -lib "work" "source/nx_data_validate.vhd" -add_file -vhdl -lib "work" "source/nx_trigger_validate.vhd" -add_file -vhdl -lib "work" "source/nx_event_buffer.vhd" - -add_file -vhdl -lib "work" "source/nxyter_registers.vhd" -add_file -vhdl -lib "work" "source/nx_setup.vhd" -add_file -vhdl -lib "work" "source/nx_histograms.vhd" - -add_file -vhdl -lib "work" "source/nx_i2c_master.vhd" -add_file -vhdl -lib "work" "source/nx_i2c_startstop.vhd" -add_file -vhdl -lib "work" "source/nx_i2c_sendbyte.vhd" -add_file -vhdl -lib "work" "source/nx_i2c_readbyte.vhd" - -add_file -vhdl -lib "work" "source/adc_spi_master.vhd" -add_file -vhdl -lib "work" "source/adc_spi_sendbyte.vhd" -add_file -vhdl -lib "work" "source/adc_spi_readbyte.vhd" - -add_file -vhdl -lib "work" "source/nx_fpga_timestamp.vhd" -add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd" -add_file -vhdl -lib "work" "source/nx_trigger_handler.vhd" -add_file -vhdl -lib "work" "source/nx_timestamp_sim.vhd" - -# Needed by ADC9222 Entity -add_file -vhdl -lib "work" "../base/cores/dqsinput.vhd" -add_file -vhdl -lib "work" "../base/cores/dqsinput1x4.vhd" -add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200.vhd" -add_file -vhdl -lib "work" "../base/cores/pll_adc12bit.vhd" -add_file -vhdl -lib "work" "../base/cores/fifo_32x512.vhd" -add_file -vhdl -lib "work" "../base/code/adc_ad9222.vhd" + diff --git a/mupix/trb3_periph_constraints.lpf b/mupix/trb3_periph_constraints.lpf index 0022ba1..f400b89 100644 --- a/mupix/trb3_periph_constraints.lpf +++ b/mupix/trb3_periph_constraints.lpf @@ -13,34 +13,7 @@ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; - FREQUENCY PORT NX1_CLK256A_OUT 256 MHz; - FREQUENCY PORT NX2_CLK256A_OUT 256 MHz; - -#Put the names of your nxyter inputs here: - FREQUENCY PORT NX1_CLK128_IN 128 MHz; - FREQUENCY PORT NX2_CLK128_IN 128 MHz; - FREQUENCY PORT NX1_ADC_DCLK_IN 192 MHz; - FREQUENCY PORT NX2_ADC_DCLK_IN 192 MHz; - -#Change the next two lines to the clk_fast signal of the ADC - USE PRIMARY2EDGE NET "THE_MAIN_PLL/PLLInst_0"; - USE PRIMARY NET "THE_MAIN_PLL/PLLInst_0"; - - - USE PRIMARY NET "CLK_PCLK_LEFT"; - USE PRIMARY NET "CLK_PCLK_LEFT_c"; - - USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT"; - USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT_c"; - - USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT"; - USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT_c"; - - USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk"; - USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk"; - #USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk"; - #USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk"; ################################################################# # Reset Nets @@ -65,29 +38,9 @@ MULTICYCLE TO CELL "THE_ADC/restart_i" 20 ns; ################################################################# -# Constraints for nxyter inputs +# Constraints for MuPix inputs ################################################################# # look at .par and .twr.setup file for clocks # and .mrp or errors -PROHIBIT PRIMARY NET "NX1_CLK128_IN_c"; -PROHIBIT SECONDARY NET "NX1_CLK128_IN_c"; - -PROHIBIT PRIMARY NET "NX2_CLK128_IN_c"; -PROHIBIT SECONDARY NET "NX2_CLK128_IN_c"; - -PROHIBIT PRIMARY NET "TEST_LINE_c_0"; -PROHIBIT SECONDARY NET "TEST_LINE_c_0"; - -DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*"; -INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" ; - -DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*"; -INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_CLK128_IN" ; - -MULTICYCLE FROM CLKNET "NX1_CLK256A_OUT_c" 50 ns; -MULTICYCLE FROM CLKNET "NX2_CLK256A_OUT_c" 50 ns; - -#PROHIBIT PRIMARY NET "NX1_ADC_DCLK_IN_c"; -#PROHIBIT SECONDARY NET "NX1_ADC_DCLK_IN_c";