From: Jan Michel <j.michel@gsi.de>
Date: Thu, 16 Aug 2018 11:25:04 +0000 (+0200)
Subject: add some registers to multiplicity logic
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c669cf5d35cee4b8d9282048b37c7cd7c031fb95;p=trb3.git

add some registers to multiplicity logic
---

diff --git a/base/code/input_to_trigger_logic_record.vhd b/base/code/input_to_trigger_logic_record.vhd
index 8ff21b5..6a2c0e9 100644
--- a/base/code/input_to_trigger_logic_record.vhd
+++ b/base/code/input_to_trigger_logic_record.vhd
@@ -42,12 +42,15 @@ signal inp_edge     : std_logic_vector(INPUTS-1 downto 0) := (others => '0');
 
 signal output_i     : std_logic_vector(OUTPUTS-1 downto 0) := (others => '0');
 signal out_reg      : std_logic_vector(OUTPUTS-1 downto 0) := (others => '0');
+signal got_any_stretch : std_logic_vector(OUTPUTS-1 downto 0) := (others => '0');
+signal got_any_edge : std_logic_vector(OUTPUTS-1 downto 0) := (others => '0');
 signal got_coincidence : std_logic;
 signal got_simplecoin  : std_logic;
 signal coin_enable  : std_logic  := '0';
 signal current_multiplicity, set_multiplicity : unsigned(7 downto 0);
 signal multiplicity_trigger : std_logic := '0';
 signal multiplicity_enable  : std_logic_vector(31 downto 0);
+signal mult_gated           : std_logic_vector(31 downto 0);
 
 signal set_output_coin, set_output_mult, set_output_simplecoin : std_logic_vector(7 downto 0);
 signal edge_enable  : std_logic_vector(7 downto 0) := (others => '0');
@@ -206,15 +209,19 @@ inp_edge          <= not inp_shift(1) and inp_shift(2) when rising_edge(CLK);
 --  Outputs
 ----------------------------
 gen_outs : for i in 0 to OUTPUTS-1 generate
-  output_i(i) <=     (or_all(inp_long and stretch_inp(INPUTS-1 downto 0) and enable(i)(INPUTS-1 downto 0)) and not edge_enable(i))
+  output_i(i) <=     (got_any_stretch(i) and not edge_enable(i))
                   or (or_all(inp_inv(INPUTS-1 downto 0) and not stretch_inp(INPUTS-1 downto 0) and enable(i)(INPUTS-1 downto 0)) and not edge_enable(i))
-                  or (or_all(inp_edge(INPUTS-1 downto 0) and enable(i)(INPUTS-1 downto 0)) and edge_enable(i))
+                  or (got_any_edge(i) and edge_enable(i))
                   or (got_simplecoin and set_output_simplecoin(i))
                   or (multiplicity_trigger and set_output_mult(i))
                   or (got_coincidence and set_output_coin(i))                   
                   ;
+got_any_edge(i) <= or_all(inp_edge(INPUTS-1 downto 0) and enable(i)(INPUTS-1 downto 0)) when rising_edge(CLK);
+got_any_stretch(i) <= or_all(inp_long and stretch_inp(INPUTS-1 downto 0) and enable(i)(INPUTS-1 downto 0))  when rising_edge(CLK);
+                  
 end generate;
 
+
 out_reg <= output_i when rising_edge(CLK);
 OUTPUT  <= output_i;
 
@@ -236,11 +243,16 @@ got_simplecoin    <= coin_in_1 and coin_in_2 and coin_enable when rising_edge(CL
 -- gen_mult : if OUTPUTS >= 2 generate
   PROC_MULT : process 
     variable m : integer range 0 to INPUTS-1;
+    variable numchan : integer range 0 to 31;
   begin
     wait until rising_edge(CLK);
+    numchan := minimum(INPUTS-1,31);
+    
+    mult_gated(numchan downto 0) <= inp_verylong(numchan downto 0) and multiplicity_enable(numchan downto 0);
+    
     m := 0;
-    for i in 0 to minimum(INPUTS-1,31) loop  --was INPUTS-1 @ 09.17
-      if inp_verylong(i) = '1' and multiplicity_enable(i) = '1' then
+    for i in 0 to numchan loop  --was INPUTS-1 @ 09.17
+      if mult_gated(i) = '1' then
         m := m + 1;
       end if;  
     end loop;
diff --git a/hub/config_compile.pl b/hub/config_compile.pl
deleted file mode 120000
index 67b86a0..0000000
--- a/hub/config_compile.pl
+++ /dev/null
@@ -1 +0,0 @@
-config_compile_gsi.pl
\ No newline at end of file