From: Jan Michel Date: Wed, 2 Oct 2013 22:57:28 +0000 (+0200) Subject: compiling version with ADC PLLs rearranged X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c7ce5554487812627df1dfe41a58521b22d643fd;p=trb3.git compiling version with ADC PLLs rearranged --- diff --git a/base/cores/dqsinput.ipx b/base/cores/dqsinput.ipx index ddcdf14..f9a6e2c 100644 --- a/base/cores/dqsinput.ipx +++ b/base/cores/dqsinput.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/base/cores/dqsinput.lpc b/base/cores/dqsinput.lpc index 326ccd1..16e4e23 100644 --- a/base/cores/dqsinput.lpc +++ b/base/cores/dqsinput.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=DDR_GENERIC -CoreRevision=5.3 +CoreRevision=5.4 ModuleName=dqsinput SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/27/2013 -Time=19:58:10 +Date=10/02/2013 +Time=23:39:53 [Parameters] Verilog=0 diff --git a/base/cores/dqsinput.vhd b/base/cores/dqsinput.vhd index 9be81a0..e207a19 100644 --- a/base/cores/dqsinput.vhd +++ b/base/cores/dqsinput.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) --- Module Version: 5.3 ---/d/jspc29/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n dqsinput -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 192 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e +-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99) +-- Module Version: 5.4 +--/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n dqsinput -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 192 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e --- Wed Mar 27 19:58:10 2013 +-- Wed Oct 2 23:39:53 2013 library IEEE; use IEEE.std_logic_1164.all; diff --git a/nxyter/compile_frankfurt.pl b/nxyter/compile_frankfurt.pl index 05a3bd8..63e4b75 100755 --- a/nxyter/compile_frankfurt.pl +++ b/nxyter/compile_frankfurt.pl @@ -9,7 +9,7 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/2.01'; +my $lattice_path = '/d/jspc29/lattice/diamond/2.1_x64'; my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; @@ -112,7 +112,8 @@ execute($c); system("rm $TOPNAME.ncd"); -$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); # IOR IO Timing Report diff --git a/nxyter/trb3_periph.p3t b/nxyter/trb3_periph.p3t new file mode 100644 index 0000000..2534469 --- /dev/null +++ b/nxyter/trb3_periph.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "trb3_gbe_trb3_gbe.log" +-o "trb3_gbe_trb3_gbe.csv" +-pr "trb3_gbe_trb3_gbe.prf" diff --git a/nxyter/trb3_periph.pt b/nxyter/trb3_periph.pt new file mode 100644 index 0000000..b5319a3 --- /dev/null +++ b/nxyter/trb3_periph.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 8 +-sphld m diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index 0c78926..ba13427 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -279,7 +279,8 @@ architecture trb3_periph_arch of trb3_periph is -- nXyter-FEB-Board Clocks signal nx_main_clk : std_logic; signal pll_nx_clk_lock : std_logic; - signal clk_adc_dat : std_logic; + signal clk_adc_dat_2 : std_logic; + signal clk_adc_dat_1 : std_logic; signal pll_adc_clk_lock : std_logic; -- nXyter 1 Regio Bus @@ -344,7 +345,7 @@ begin --------------------------------------------------------------------------- THE_MAIN_PLL : pll_in200_out100 port map( - CLK => CLK_GPLL_RIGHT, + CLK => CLK_PCLK_RIGHT, CLKOP => clk_100_i, CLKOK => clk_200_i, LOCK => pll_lock @@ -692,7 +693,7 @@ begin CLK_IN => clk_100_i, RESET_IN => reset_i, CLK_NX_IN => nx_main_clk, - CLK_ADC_IN => clk_adc_dat, + CLK_ADC_IN => clk_adc_dat_1, TRIGGER_OUT => fee1_trigger, I2C_SDA_INOUT => NX1_I2C_SDA_INOUT, @@ -770,7 +771,7 @@ begin CLK_IN => clk_100_i, RESET_IN => reset_i, CLK_NX_IN => nx_main_clk, - CLK_ADC_IN => clk_adc_dat, + CLK_ADC_IN => clk_adc_dat_2, TRIGGER_OUT => fee2_trigger, I2C_SDA_INOUT => NX2_I2C_SDA_INOUT, @@ -856,8 +857,14 @@ begin -- ClockSource as nXyter Main Clock) pll_adc_clk_1: pll_adc_clk port map ( - CLK => clk_200_i, - CLKOP => clk_adc_dat, + CLK => CLK_PCLK_RIGHT, + CLKOP => clk_adc_dat_1, + LOCK => pll_adc_clk_lock + ); + pll_adc_clk_2: pll_adc_clk + port map ( + CLK => CLK_PCLK_RIGHT, + CLKOP => clk_adc_dat_2, LOCK => pll_adc_clk_lock ); diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index 6758f2d..5af8655 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -31,28 +31,25 @@ # Not used in current design #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; - #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; - FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; - #USE PRIMARY NET CLK_GPLL_RIGHT; - #USE PRIMARY NET CLK_GPLL_RIGHT_c; - - #FREQUENCY PORT nx_main_clk 250 MHz; - USE PRIMARY NET "nx_main_clk"; - #USE PRIMARY NET CLK_GPLL_RIGHT_c; - - LOCATE COMP THE_MAIN_PLL/PLLInst_0 SITE PLL_R79C5; - - -# Put the names of your nxyter inputs here: FREQUENCY PORT NX1_CLK128_IN 125 MHz; FREQUENCY PORT NX2_CLK128_IN 125 MHz; - #FREQUENCY PORT NX1_ADC_DCLK_IN 93.75 MHz; - #FREQUENCY PORT NX2_ADC_DCLK_IN 93.75 MHz; - FREQUENCY PORT NX1_ADC_SAMPLE_CLK_OUT 31.25 MHz; FREQUENCY PORT NX2_ADC_SAMPLE_CLK_OUT 31.25 MHz; + + USE PRIMARY NET "nx_main_clk"; + USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT"; + USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT"; + USE PRIMARY NET "clk_200_i"; + USE PRIMARY NET "clk_100_i_c"; + USE PRIMARY NET "CLK_PCLK_RIGHT_c"; + + #LOCATE COMP THE_MAIN_PLL/PLLInst_0 SITE PLL_R79C178; + + +# Put the names of your nxyter inputs here: # ------ ADC Stuff --------------------------- @@ -62,9 +59,6 @@ #FREQUENCY PORT clk_adc_dat 93.75 MHz; #USE PRIMARY NET "clk_adc_dat"; - USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT"; - USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT"; - #PROHIBIT PRIMARY NET "NX1_ADC_FCLK_IN"; #PROHIBIT PRIMARY NET "NX1B_ADC_FCLK_IN"; #PROHIBIT SECONDARY NET "NX1_ADC_FCLK_IN";