From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Fri, 29 Jul 2022 09:00:26 +0000 (+0200)
Subject: relaxed timing for muxing data
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c84566421565fb79aec6760279baeb91c7b19141;p=trbnet.git

relaxed timing for muxing data
---

diff --git a/gbe_trb/base/rx_rb.vhd b/gbe_trb/base/rx_rb.vhd
index 0c57f46..31f3f5e 100644
--- a/gbe_trb/base/rx_rb.vhd
+++ b/gbe_trb/base/rx_rb.vhd
@@ -50,25 +50,26 @@ architecture rx_rb_arch of rx_rb is
   signal STATE, NEXT_STATE    : state_t;
 
 -- Signals
-  signal rd_ptr          : unsigned(11 downto 0);
-  signal wr_ptr          : unsigned(11 downto 0);
-  signal last_wr_ptr     : std_logic_vector(11 downto 0);
-  signal rb_used         : unsigned(11 downto 0);
-  signal rb_full         : std_logic;
-  signal rb_empty        : std_logic;
-  signal ce_wr_ptr       : std_logic;
-  signal ld_wr_ptr       : std_logic;
-  signal ce_rd_ptr       : std_logic;
-  signal wr_ram          : std_logic;
-  signal rd_ram          : std_logic;
-  signal ram_q           : std_logic_vector(8 downto 0);
-  signal frame_active    : std_logic;
-  signal frame_requested : std_logic;
-  signal fifo_wr_int     : std_logic;
-  signal empty_read_ack  : std_logic;
-  signal normal_read_ack : std_logic;
-  signal sof_int         : std_logic;
-  signal frames_avail    : unsigned(7 downto 0);
+  signal rd_ptr             : unsigned(11 downto 0);
+  signal wr_ptr             : unsigned(11 downto 0);
+  signal last_wr_ptr        : std_logic_vector(11 downto 0);
+  signal rb_used            : unsigned(11 downto 0);
+  signal rb_full            : std_logic;
+  signal rb_empty           : std_logic;
+  signal ce_wr_ptr          : std_logic;
+  signal ld_wr_ptr          : std_logic;
+  signal ce_rd_ptr          : std_logic;
+  signal wr_ram             : std_logic;
+  signal rd_ram             : std_logic;
+  signal ram_q              : std_logic_vector(8 downto 0);
+  signal frame_active       : std_logic;
+  signal frame_requested    : std_logic;
+  signal frame_acknowledged : std_logic;
+  signal fifo_wr_int        : std_logic;
+  signal empty_read_ack     : std_logic;
+  signal normal_read_ack    : std_logic;
+  signal sof_int            : std_logic;
+  signal frames_avail       : unsigned(7 downto 0);
 
 
 begin
@@ -180,6 +181,7 @@ begin
   empty_read_ack <= FRAME_REQ_IN and rb_empty when rising_edge(CLK);
   
   -- NormalReadAck signal
+--  normal_read_ack <= ram_q(8) and fifo_wr_int when rising_edge(CLK); -- ADDED 2nd step
   normal_read_ack <= ram_q(8) and fifo_wr_int;
   
   -- read signal
@@ -188,15 +190,15 @@ begin
   
   sof_int <= FRAME_REQ_IN and not frame_requested when rising_edge(CLK);
   
-  FRAME_ACK_OUT <= normal_read_ack or empty_read_ack;
+  FRAME_ACK_OUT <= normal_read_ack or empty_read_ack when rising_edge(CLK); -- ADDED
   
-  FRAME_START_OUT <= sof_int;
+  FRAME_START_OUT <= sof_int when rising_edge(CLK); -- ADDED
   
-  FIFO_Q_OUT <= ram_q;
+  FIFO_Q_OUT <= ram_q when rising_edge(CLK); -- ADDED
   
   fifo_wr_int <= rd_ram when rising_edge(CLK);
    
-  FIFO_WR_OUT <= fifo_wr_int;
+  FIFO_WR_OUT <= fifo_wr_int when rising_edge(CLK); -- ADDED
   
   -- FramesAvailable counter
   THE_FRAMES_AVAIL_PROC: process( CLK )