From: Cahit Date: Fri, 8 May 2015 12:16:06 +0000 (+0200) Subject: brought 32 PinAddOn project up-to-date X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c853a35e80115a5466bea1e39da9d1d0706b1417;p=trb3.git brought 32 PinAddOn project up-to-date --- diff --git a/32PinAddOn/compile_constraints.pl b/32PinAddOn/compile_constraints.pl index f23f766..c5c47dd 100755 --- a/32PinAddOn/compile_constraints.pl +++ b/32PinAddOn/compile_constraints.pl @@ -6,8 +6,15 @@ use strict; my $TOPNAME = "trb3_periph_32PinAddOn"; #Name of top-level entity #create full lpf file -system("cp ../base/$TOPNAME.lpf diamond/trb3_periph.lpf"); -system("cat currentRelease/trbnet_constraints.lpf >> diamond/trb3_periph.lpf"); -system("cat currentRelease/tdc_constraints_64.lpf >> diamond/trb3_periph.lpf"); -system("cat currentRelease/unimportant_lines_constraints.lpf >> diamond/trb3_periph.lpf"); -system("cat unimportant_lines_constraints.lpf >> diamond/trb3_periph.lpf"); +#system("cp ../base/$TOPNAME.lpf diamond/$TOPNAME.lpf"); +#system("cat tdc_release/trbnet_constraints.lpf >> diamond/$TOPNAME.lpf"); +#system("cat tdc_release/tdc_constraints_64.lpf >> diamond/$TOPNAME.lpf"); +#system("cat tdc_release/unimportant_lines_constraints.lpf >> diamond/$TOPNAME.lpf"); +#system("cat unimportant_lines_constraints.lpf >> diamond/$TOPNAME.lpf"); + +system("cp ../base/$TOPNAME.lpf workdir/diamond/$TOPNAME.lpf"); +system("cat tdc_release/trbnet_constraints.lpf >> workdir/diamond/$TOPNAME.lpf"); +system("cat tdc_release/tdc_constraints_64.lpf >> workdir/diamond/$TOPNAME.lpf"); +system("cat tdc_release/unimportant_lines_constraints.lpf >> workdir/diamond/$TOPNAME.lpf"); +system("cat unimportant_lines_constraints.lpf >> workdir/diamond/$TOPNAME.lpf"); + diff --git a/32PinAddOn/config.vhd b/32PinAddOn/config.vhd index 7f6b579..79253d0 100644 --- a/32PinAddOn/config.vhd +++ b/32PinAddOn/config.vhd @@ -11,9 +11,9 @@ package config is --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons - constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 2; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, -- 2: alternating channels, @@ -28,7 +28,7 @@ package config is constant INCLUDE_SPI : integer := c_YES; --Add logic to generate configurable trigger signal from input signals. - constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; constant INCLUDE_STATISTICS : integer := c_YES; --Do histos of all inputs constant PHYSICAL_INPUTS : integer := 32; --number of inputs connected constant USE_SINGLE_FIFO : integer := c_YES; -- single fifo for statistics diff --git a/32PinAddOn/currentRelease b/32PinAddOn/currentRelease deleted file mode 120000 index 02a0ff9..0000000 --- a/32PinAddOn/currentRelease +++ /dev/null @@ -1 +0,0 @@ -../tdc_releases/tdc_v2.1.1 \ No newline at end of file diff --git a/32PinAddOn/tdc_release b/32PinAddOn/tdc_release new file mode 120000 index 0000000..b10de14 --- /dev/null +++ b/32PinAddOn/tdc_release @@ -0,0 +1 @@ +../../tdc/releases/tdc_v2.1.2 \ No newline at end of file diff --git a/32PinAddOn/trb3_periph_32PinAddOn.prj b/32PinAddOn/trb3_periph_32PinAddOn.prj index 54f77cd..bee9bca 100644 --- a/32PinAddOn/trb3_periph_32PinAddOn.prj +++ b/32PinAddOn/trb3_periph_32PinAddOn.prj @@ -18,16 +18,16 @@ set_option -resource_sharing true # map options set_option -frequency 200 set_option -fanout_limit 100 + +# Lattice XP set_option -disable_io_insertion 0 set_option -retiming 0 set_option -pipe 0 -#set_option -force_gsr set_option -force_gsr false set_option -fixgatedclocks false #3 set_option -fixgeneratedclocks false #3 set_option -compiler_compatible true - # simulation options set_option -write_verilog 0 set_option -write_vhdl 1 @@ -40,24 +40,23 @@ project -result_format "edif" project -result_file "workdir/trb3_periph_32PinAddOn.edf" #implementation attributes - set_option -vlog_std v2001 set_option -project_relative_includes 1 + +# design plan options impl -active "workdir" #################### - -#add_file options - +#project files add_file -vhdl -lib work "version.vhd" -add_file -vhdl -lib work "currentRelease/tdc_version.vhd" +add_file -vhdl -lib work "tdc_release/tdc_version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" add_file -vhdl -lib work "../base/trb3_components.vhd" -add_file -vhdl -lib work "currentRelease/tdc_components.vhd" +add_file -vhdl -lib work "tdc_release/tdc_components.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" @@ -106,6 +105,8 @@ add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" @@ -150,25 +151,34 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" ############### #Change path to tdc release also in compile script! ############### -#add_file -vhdl -lib "work" "currentRelease/Adder_304.vhd" -add_file -vhdl -lib "work" "currentRelease/bit_sync.vhd" -add_file -vhdl -lib "work" "currentRelease/BusHandler.vhd" -add_file -vhdl -lib "work" "currentRelease/Channel.vhd" -add_file -vhdl -lib "work" "currentRelease/Channel_200.vhd" -add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd" -add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd" -add_file -vhdl -lib "work" "currentRelease/Readout.vhd" -add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd" -add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd" -add_file -vhdl -lib "work" "currentRelease/TDC.vhd" -add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd" -add_file -vhdl -lib "work" "currentRelease/up_counter.vhd" -add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd" -add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd" -add_file -vhdl -lib "work" "currentRelease/hit_mux.vhd" -add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd" -add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd" -add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "tdc_release/BusHandler.vhd" +add_file -vhdl -lib work "tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "tdc_release/Channel.vhd" +add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd" +add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "tdc_release/Readout.vhd" +add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd" +add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "tdc_release/TDC.vhd" +add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "tdc_release/up_counter.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out333.vhd" + add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd" add_file -vhdl -lib "work" "../base/code/input_statistics.vhd" add_file -vhdl -lib "work" "../base/code/sedcheck.vhd" diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd b/32PinAddOn/trb3_periph_32PinAddOn.vhd index 7358892..a8babbe 120000 --- a/32PinAddOn/trb3_periph_32PinAddOn.vhd +++ b/32PinAddOn/trb3_periph_32PinAddOn.vhd @@ -1 +1 @@ -currentRelease/trb3_periph_32PinAddOn.vhd \ No newline at end of file +tdc_release/trb3_periph_32PinAddOn.vhd \ No newline at end of file