From: hadaq Date: Fri, 4 Nov 2011 11:00:34 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c8ae1abf67f25bf492184852ccf72320bdfa8006;p=trb3.git *** empty log message *** --- diff --git a/base/compile_periph_frankfurt.pl b/base/compile_periph_frankfurt.pl index 6f55fc1..3c64fc9 100755 --- a/base/compile_periph_frankfurt.pl +++ b/base/compile_periph_frankfurt.pl @@ -85,11 +85,11 @@ foreach (@a) { if(/\@E:/) { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); print "\n\n"; - exit 129; + exit 129; } } diff --git a/base/compile_periph_gsi.pl b/base/compile_periph_gsi.pl index 30d6868..ce197d3 100755 --- a/base/compile_periph_gsi.pl +++ b/base/compile_periph_gsi.pl @@ -85,11 +85,11 @@ foreach (@a) { if(/\@E:/) { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); print "\n\n"; - exit 129; + exit 129; } } diff --git a/base/compile_periph_synonly.pl b/base/compile_periph_synonly.pl new file mode 100755 index 0000000..99c0314 --- /dev/null +++ b/base/compile_periph_synonly.pl @@ -0,0 +1,155 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + + + + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph"; #Name of top-level entity +my $BasePath = "../base/"; #path to "base" directory +my $lattice_path = '/opt/lattice/diamond/1.3'; +my $synplify_path = '/opt/synplicity/fpga_e201103'; +my $lm_license_file_for_synplify = "27000\@localhost"; +my $lm_license_file_for_par = "1710\@cronos.e12.physik.tu-muenchen.de"; +################################################################################### + + + + + + + + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + + +#create full lpf file +system("cp $BasePath/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); + + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; + +my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + + + +foreach (@a) +{ + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } +} + + +#$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +#$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +#execute($c); + +#my $tpmap = $TOPNAME . "_map" ; + +#$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +#execute($c); + + +#system("rm $TOPNAME.ncd"); + +#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +#execute($c); + +## IOR IO Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +## TWR Timing Report +#$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +#execute($c); + +#$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +#execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/base/tdc_source_files/TDC.vhd b/base/tdc_source_files/TDC.vhd index 50bd380..f1e0ac6 100644 --- a/base/tdc_source_files/TDC.vhd +++ b/base/tdc_source_files/TDC.vhd @@ -13,19 +13,20 @@ use ecp2m.components.all; entity TDC is generic ( - CHANNEL_NUMBER : integer range 0 to 64 := 8); + CHANNEL_NUMBER : integer range 0 to 64 := 8); port ( - RESET : in std_logic; - CLK_CHANNEL : in std_logic; - CLK_READOUT : in std_logic; - HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); - TRIGGER_IN : in std_logic; - TRIGGER_WIN : in std_logic_vector(31 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - TRB_WR_CLK_OUT : out std_logic; - DATA_VALID : out std_logic; - DATA_READY : out std_logic; - TDC_DEBUG_00 : out std_logic_vector(31 downto 0) + RESET : in std_logic; + CLK_TDC : in std_logic; + CLK_READOUT : in std_logic; + HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + TRIGGER_IN : in std_logic; + TRIGGER_WIN_IN : in std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + TRB_WR_CLK_OUT : out std_logic; + DATA_VALID_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic; + READY_OUT : out std_logic; + TDC_DEBUG_00 : out std_logic_vector(31 downto 0) ); end TDC; @@ -37,7 +38,7 @@ architecture TDC of TDC is component Channel generic ( - CHANNEL_ID : integer range 0 to 15); + CHANNEL_ID : integer range 0 to 15); port ( RESET : in std_logic; CLK : in std_logic; @@ -52,64 +53,64 @@ architecture TDC of TDC is -- component ROM_FIFO port ( - Address : in std_logic_vector(7 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(3 downto 0)); + Address : in std_logic_vector(7 downto 0); + OutClock : in std_logic; + OutClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(3 downto 0)); end component; -- component up_counter generic ( - NUMBER_OF_BITS : positive); + NUMBER_OF_BITS : positive); port ( - CLK : in std_logic; - RESET : in std_logic; - COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); - UP_IN : in std_logic); + CLK : in std_logic; + RESET : in std_logic; + COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0); + UP_IN : in std_logic); end component; -- component edge_to_pulse_fast port ( - RESET : in std_logic; - CLK : in std_logic; - SIGNAL_IN : in std_logic; - PULSE_OUT : out std_logic); + RESET : in std_logic; + CLK : in std_logic; + SIGNAL_IN : in std_logic; + PULSE_OUT : out std_logic); end component; -- component bit_sync generic ( - DEPTH : integer); + DEPTH : integer); port ( - RESET : in std_logic; - CLK0 : in std_logic; - CLK1 : in std_logic; - D_IN : in std_logic; - D_OUT : out std_logic); + RESET : in std_logic; + CLK0 : in std_logic; + CLK1 : in std_logic; + D_IN : in std_logic; + D_OUT : out std_logic); end component; -- component ddr_off port ( - Clk : in std_logic; - Data : in std_logic_vector(1 downto 0); - Q : out std_logic_vector(0 downto 0)); + Clk : in std_logic; + Data : in std_logic_vector(1 downto 0); + Q : out std_logic_vector(0 downto 0)); end component; ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- -- Input Output signals - signal clk_i : std_logic; - signal clk_100_i : std_logic; - signal lock_100_i : std_logic; - signal reset_i : std_logic; - signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal trigger_in_i : std_logic; - signal trig_pulse_i : std_logic; - signal trig_sync_i : std_logic; - signal data_out_i : std_logic_vector(31 downto 0); - signal data_valid_i : std_logic; - signal data_ready_i : std_logic; + signal clk_i : std_logic; + signal clk_100_i : std_logic; + signal lock_100_i : std_logic; + signal reset_i : std_logic; + signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal trigger_in_i : std_logic; + signal trig_pulse_i : std_logic; + signal trig_sync_i : std_logic; + signal data_out_i : std_logic_vector(31 downto 0); + signal data_valid_i : std_logic; + signal data_finished_i : std_logic; -- Other signals type FSM is (IDLE, WR_HEADER, WR_ERROR, WR_TRAILOR, WAIT_FOR_FIFO_NR, @@ -121,8 +122,8 @@ architecture TDC of TDC is signal start_rdout_i : std_logic; signal rdout_busy_fsm : std_logic; signal rdout_busy_i : std_logic; - signal send_ready_fsm : std_logic; - signal send_ready_i : std_logic; + signal send_finished_fsm : std_logic; + signal send_finished_i : std_logic; signal wr_header_fsm : std_logic; signal wr_header_i : std_logic; signal wr_ch_data_fsm : std_logic; @@ -153,7 +154,7 @@ architecture TDC of TDC is signal ctwe_reset_i : std_logic; signal trig_win_end_i : std_logic; -- - type Std_Logic_8_array is array (0 to 1) of std_logic_vector(3 downto 0); + type Std_Logic_8_array is array (0 to 1) of std_logic_vector(3 downto 0); signal fifo_nr_hex : Std_Logic_8_array; -- signal coarse_counter_i : std_logic_vector(15 downto 0); @@ -168,7 +169,7 @@ architecture TDC of TDC is signal LE_cntr_up : std_logic; signal LE_cntr_i : std_logic_vector(15 downto 0); -- - type channel_data_array is array (0 to CHANNEL_NUMBER) of std_logic_vector(31 downto 0); + type channel_data_array is array (0 to CHANNEL_NUMBER) of std_logic_vector(31 downto 0); signal channel_data_i : channel_data_array; signal channel_data_reg : channel_data_array; signal channel_data_2reg : channel_data_array; @@ -186,21 +187,21 @@ architecture TDC of TDC is begin reset_i <= RESET; - clk_i <= CLK_CHANNEL; + clk_i <= CLK_TDC; clk_100_i <= CLK_READOUT; trigger_in_i <= TRIGGER_IN; hit_in_i <= HIT_IN; - trig_win_pre <= TRIGGER_WIN(15 downto 0); - trig_win_post <= TRIGGER_WIN(31 downto 16); + trig_win_pre <= TRIGGER_WIN_IN(15 downto 0); + trig_win_post <= TRIGGER_WIN_IN(31 downto 16); ------------------------------------------------------------------------------- -- COMPONENT INSTANTINIATIONS ------------------------------------------------------------------------------- -- Channels GEN_Channels : for i in 0 to CHANNEL_NUMBER - 1 generate - Channels : Channel + Channels : Channel generic map ( - CHANNEL_ID => i) + CHANNEL_ID => i) port map ( RESET => reset_i, CLK => clk_i, @@ -219,10 +220,10 @@ begin generic map ( NUMBER_OF_BITS => 16) port map ( - CLK => clk_i, - RESET => reset_i, - COUNT_OUT => coarse_counter_i, - UP_IN => '1'); + CLK => clk_i, + RESET => reset_i, + COUNT_OUT => coarse_counter_i, + UP_IN => '1'); ------------------------------------------------------------------------------- -- CLOCK SETTINGS @@ -279,10 +280,10 @@ begin generic map ( NUMBER_OF_BITS => 16) port map ( - CLK => clk_100_i, - RESET => reset_i, - COUNT_OUT => LE_cntr_i, - UP_IN => LE_cntr_up); + CLK => clk_100_i, + RESET => reset_i, + COUNT_OUT => LE_cntr_i, + UP_IN => LE_cntr_up); LE_cntr_up <= start_rdout_i; -- purpose: Defines the trigger time with respect to the coarse counter @@ -328,10 +329,10 @@ begin generic map ( NUMBER_OF_BITS => 16) port map ( - CLK => clk_100_i, - RESET => ctwe_reset_i, - COUNT_OUT => ctwe_cntr_i, - UP_IN => ctwe_up_i); + CLK => clk_100_i, + RESET => ctwe_reset_i, + COUNT_OUT => ctwe_cntr_i, + UP_IN => ctwe_up_i); --purpose: Calculates the position of the trigger window edges Trig_Win_Calculation : process (clk_100_i, reset_i) @@ -370,11 +371,11 @@ begin begin if rising_edge(clk_100_i) then if reset_i = '1' then - trig_win_r <= '0'; + trig_win_r <= '0'; elsif channel_hit_time <= TW_post then - trig_win_r <= '1'; + trig_win_r <= '1'; else - trig_win_r <= '0'; + trig_win_r <= '0'; end if; end if; end process Check_Trig_Win_Right; @@ -386,13 +387,13 @@ begin begin if rising_edge(clk_100_i) then if reset_i = '1' then - mask_i <= (others => '1'); + mask_i <= (others => '1'); elsif trig_win_end_i = '1' then - mask_i <= channel_empty_i; + mask_i <= channel_empty_i; elsif updt_mask_i = '1' then mask_i(fifo_nr) <= '1'; else - mask_i <= mask_i; + mask_i <= mask_i; end if; end if; end process CREAT_MASK; @@ -442,19 +443,19 @@ begin end if; end process UPDATE_INDEX_NR; ------------------------------------------------------------------------------- --- Data Out, Data Valid and Data Ready assigning according to the control +-- Data Out, Data Valid and Data Finished assigning according to the control -- signals from the readout final-state-machine. Data_Out_MUX : process (clk_100_i, reset_i) begin if rising_edge(clk_100_i) then if reset_i = '1' then - data_out_i <= (others => '1'); - data_valid_i <= '0'; + data_out_i <= (others => '1'); + data_valid_i <= '0'; else if wr_header_i = '1' then - data_out_i <= x"aa00" & LE_cntr_i; - data_valid_i <= '1'; + data_out_i <= x"aa00" & LE_cntr_i; + data_valid_i <= '1'; elsif wr_ch_data_i = '1' then if (TW_pre(15) = '1' and trig_time_i(15) = '0') or (TW_post(15) = '0' and trig_time_i(15) = '1') then if (trig_win_l = '0' and trig_win_r = '1') or (trig_win_l = '1' and trig_win_r = '0') then @@ -476,36 +477,37 @@ begin end if; end if; elsif wr_error_i = '1' then - data_out_i <= x"ee000000"; - data_valid_i <= '1'; + data_out_i <= x"ee000000"; + data_valid_i <= '1'; elsif wr_trailor_i = '1' then - data_out_i <= x"bb00" & LE_cntr_i; - data_valid_i <= '1'; + data_out_i <= x"bb00" & LE_cntr_i; + data_valid_i <= '1'; else - data_out_i <= (others => '1'); - data_valid_i <= '0'; + data_out_i <= (others => '1'); + data_valid_i <= '0'; end if; end if; end if; end process Data_Out_MUX; - DATA_OUT <= data_out_i; - DATA_VALID <= data_valid_i; + DATA_OUT <= data_out_i; + DATA_VALID_OUT <= data_valid_i; - Send_Ready : process (clk_100_i, reset_i) + Send_Finished : process (clk_100_i, reset_i) begin if rising_edge(clk_100_i) then if reset_i = '1' then - data_ready_i <= '0'; - elsif send_ready_i = '1' then - data_ready_i <= '1'; + data_finished_i <= '0'; + elsif send_finished_i = '1' then + data_finished_i <= '1'; else - data_ready_i <= '0'; + data_finished_i <= '0'; end if; end if; - end process Send_Ready; + end process Send_Finished; - DATA_READY <= data_ready_i; + DATA_FINISHED_OUT <= data_finished_i; + READY_OUT <= data_finished_i; ----------------------------------------------------------------------------- -- Data delay @@ -542,29 +544,29 @@ begin begin if rising_edge(clk_100_i) then if reset_i = '1' then - FSM_CURRENT <= IDLE; - rdout_busy_i <= '0'; - updt_index_i <= '0'; - updt_mask_i <= '0'; - wr_header_i <= '0'; - wr_ch_data_i <= '0'; - wr_error_i <= '0'; - wr_trailor_i <= '0'; - rd_en_i <= (others => '0'); - send_ready_i <= '0'; - fsm_debug_i <= x"0"; + FSM_CURRENT <= IDLE; + rdout_busy_i <= '0'; + updt_index_i <= '0'; + updt_mask_i <= '0'; + wr_header_i <= '0'; + wr_ch_data_i <= '0'; + wr_error_i <= '0'; + wr_trailor_i <= '0'; + rd_en_i <= (others => '0'); + send_finished_i <= '0'; + fsm_debug_i <= x"0"; else - FSM_CURRENT <= FSM_NEXT; - rdout_busy_i <= rdout_busy_fsm; - updt_index_i <= updt_index_fsm; - updt_mask_i <= updt_mask_fsm; - wr_header_i <= wr_header_fsm; - wr_ch_data_i <= wr_ch_data_fsm; - wr_error_i <= wr_error_fsm; - wr_trailor_i <= wr_trailor_fsm; - rd_en_i <= rd_en_fsm; - send_ready_i <= send_ready_fsm; - fsm_debug_i <= fsm_debug_fsm; + FSM_CURRENT <= FSM_NEXT; + rdout_busy_i <= rdout_busy_fsm; + updt_index_i <= updt_index_fsm; + updt_mask_i <= updt_mask_fsm; + wr_header_i <= wr_header_fsm; + wr_ch_data_i <= wr_ch_data_fsm; + wr_error_i <= wr_error_fsm; + wr_trailor_i <= wr_trailor_fsm; + rd_en_i <= rd_en_fsm; + send_finished_i <= send_finished_fsm; + fsm_debug_i <= fsm_debug_fsm; end if; end if; end process FSM_CLK; @@ -573,107 +575,107 @@ begin channel_empty_4reg) begin - rdout_busy_fsm <= '1'; - updt_index_fsm <= '0'; - updt_mask_fsm <= '0'; - wr_header_fsm <= '0'; - wr_ch_data_fsm <= '0'; - wr_error_fsm <= '0'; - wr_trailor_fsm <= '0'; - rd_en_fsm <= (others => '0'); - send_ready_fsm <= '0'; + rdout_busy_fsm <= '1'; + updt_index_fsm <= '0'; + updt_mask_fsm <= '0'; + wr_header_fsm <= '0'; + wr_ch_data_fsm <= '0'; + wr_error_fsm <= '0'; + wr_trailor_fsm <= '0'; + rd_en_fsm <= (others => '0'); + send_finished_fsm <= '0'; case (FSM_CURRENT) is - when IDLE => + when IDLE => if trig_win_end_i = '1' then - rdout_busy_fsm <= '1'; - FSM_NEXT <= WR_HEADER; - fsm_debug_fsm <= x"1"; + rdout_busy_fsm <= '1'; + FSM_NEXT <= WR_HEADER; + fsm_debug_fsm <= x"1"; else - rdout_busy_fsm <= '0'; - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"2"; + rdout_busy_fsm <= '0'; + FSM_NEXT <= IDLE; + fsm_debug_fsm <= x"2"; end if; -- - when WR_HEADER => - FSM_NEXT <= WAIT_FOR_FIFO_NR; - wr_header_fsm <= '1'; - fsm_debug_fsm <= x"3"; + when WR_HEADER => + FSM_NEXT <= WAIT_FOR_FIFO_NR; + wr_header_fsm <= '1'; + fsm_debug_fsm <= x"3"; -- when WAIT_FOR_FIFO_NR => - FSM_NEXT <= APPLY_MASK; - updt_index_fsm <= '1'; - fsm_debug_fsm <= x"4"; + FSM_NEXT <= APPLY_MASK; + updt_index_fsm <= '1'; + fsm_debug_fsm <= x"4"; -- - when APPLY_MASK => + when APPLY_MASK => if fifo_nr_int = 8 then - FSM_NEXT <= WR_ERROR; - fsm_debug_fsm <= x"5"; + FSM_NEXT <= WR_ERROR; + fsm_debug_fsm <= x"5"; else FSM_NEXT <= RD_CHANNEL_1; rd_en_fsm(fifo_nr_int) <= '1'; fsm_debug_fsm <= x"6"; end if; -- - when RD_CHANNEL_1 => - FSM_NEXT <= RD_CHANNEL_2; - rd_en_fsm(fifo_nr_int) <= '1'; - updt_mask_fsm <= '1'; - fsm_debug_fsm <= x"7"; + when RD_CHANNEL_1 => + FSM_NEXT <= RD_CHANNEL_2; + rd_en_fsm(fifo_nr_int) <= '1'; + updt_mask_fsm <= '1'; + fsm_debug_fsm <= x"7"; -- - when RD_CHANNEL_2 => - FSM_NEXT <= RD_CHANNEL_3; - rd_en_fsm(fifo_nr_int) <= '1'; - fsm_debug_fsm <= x"7"; + when RD_CHANNEL_2 => + FSM_NEXT <= RD_CHANNEL_3; + rd_en_fsm(fifo_nr_int) <= '1'; + fsm_debug_fsm <= x"7"; -- - when RD_CHANNEL_3 => - FSM_NEXT <= RD_CHANNEL_4; - rd_en_fsm(fifo_nr_int) <= '1'; - fsm_debug_fsm <= x"7"; + when RD_CHANNEL_3 => + FSM_NEXT <= RD_CHANNEL_4; + rd_en_fsm(fifo_nr_int) <= '1'; + fsm_debug_fsm <= x"7"; -- - when RD_CHANNEL_4 => - FSM_NEXT <= RD_CHANNEL_5; - rd_en_fsm(fifo_nr_int) <= '1'; - fsm_debug_fsm <= x"7"; + when RD_CHANNEL_4 => + FSM_NEXT <= RD_CHANNEL_5; + rd_en_fsm(fifo_nr_int) <= '1'; + fsm_debug_fsm <= x"7"; -- - when RD_CHANNEL_5 => - FSM_NEXT <= RD_CHANNEL; - rd_en_fsm(fifo_nr) <= '1'; - fsm_debug_fsm <= x"7"; + when RD_CHANNEL_5 => + FSM_NEXT <= RD_CHANNEL; + rd_en_fsm(fifo_nr) <= '1'; + fsm_debug_fsm <= x"7"; -- - when RD_CHANNEL => + when RD_CHANNEL => -- if channel_empty_3reg(fifo_nr) = '1' then if channel_empty_4reg(fifo_nr) = '1' then - wr_ch_data_fsm <= '0'; - updt_index_fsm <= '1'; - FSM_NEXT <= APPLY_MASK; - fsm_debug_fsm <= x"8"; + wr_ch_data_fsm <= '0'; + updt_index_fsm <= '1'; + FSM_NEXT <= APPLY_MASK; + fsm_debug_fsm <= x"8"; else - wr_ch_data_fsm <= '1'; - rd_en_fsm(fifo_nr) <= '1'; - FSM_NEXT <= RD_CHANNEL; - fsm_debug_fsm <= x"9"; + wr_ch_data_fsm <= '1'; + rd_en_fsm(fifo_nr) <= '1'; + FSM_NEXT <= RD_CHANNEL; + fsm_debug_fsm <= x"9"; end if; -- - when WR_ERROR => - wr_error_fsm <= '1'; - FSM_NEXT <= WR_TRAILOR; - fsm_debug_fsm <= x"A"; + when WR_ERROR => + wr_error_fsm <= '1'; + FSM_NEXT <= WR_TRAILOR; + fsm_debug_fsm <= x"A"; -- - when WR_TRAILOR => - wr_trailor_fsm <= '1'; - FSM_NEXT <= FINISH; - fsm_debug_fsm <= x"B"; + when WR_TRAILOR => + wr_trailor_fsm <= '1'; + FSM_NEXT <= FINISH; + fsm_debug_fsm <= x"B"; -- - when FINISH => - send_ready_fsm <= '1'; - rdout_busy_fsm <= '0'; - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"C"; + when FINISH => + send_finished_fsm <= '1'; + rdout_busy_fsm <= '0'; + FSM_NEXT <= IDLE; + fsm_debug_fsm <= x"C"; -- - when others => - FSM_NEXT <= IDLE; - fsm_debug_fsm <= x"D"; + when others => + FSM_NEXT <= IDLE; + fsm_debug_fsm <= x"D"; end case; end process FSM_PROC; @@ -696,7 +698,7 @@ begin -- tdc_debug_out_i(4 downto 1) <= fsm_debug_i; -- tdc_debug_out_i(5) <= buf1_start_i; -- tdc_debug_out_i(9 downto 6) <= buf1_fsm_debug_i; --- tdc_debug_out_i(11 downto 10) <= data_ready_i; --2 +-- tdc_debug_out_i(11 downto 10) <= data_finished_i; --2 -- tdc_debug_out_i(15 downto 12) <= data_len_0_i(5 downto 2); --12 -- tdc_debug_out_i(19 downto 16) <= data_len_1_i(5 downto 2); --12 -- tdc_debug_out_i(25 downto 24) <= clear_in_i; @@ -716,6 +718,6 @@ begin end if; end if; end process REG_OUTPUTS; - TDC_DEBUG_00 <= tdc_debug_i; + TDC_DEBUG_00 <= tdc_debug_i; end TDC; diff --git a/base/trb3_periph.prj b/base/trb3_periph.prj index c475fce..e911f58 100644 --- a/base/trb3_periph.prj +++ b/base/trb3_periph.prj @@ -146,8 +146,6 @@ add_file -vhdl -lib "work" "../base/tdc_source_files/FIFO_32x512_Oreg.vhd" add_file -vhdl -lib "work" "../base/tdc_source_files/ROM_FIFO.vhd" add_file -vhdl -lib "work" "../base/cores/bit_sync.vhd" add_file -vhdl -lib "work" "../base/cores/edge_to_pulse_fast.vhd" -add_file -vhdl -lib "work" "../base/cores/f_divider.vhd" -add_file -vhdl -lib "work" "../base/cores/signal_sync.vhd" add_file -vhdl -lib "work" "../base/cores/up_counter.vhd" diff --git a/base/trb3_periph.vhd b/base/trb3_periph.vhd index bf35bd1..c41d6c2 100644 --- a/base/trb3_periph.vhd +++ b/base/trb3_periph.vhd @@ -13,85 +13,85 @@ use work.version.all; entity trb3_periph is port( --Clocks - CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz - CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA - CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! - CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz + CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! --Trigger - TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out - TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out - + TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out + TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out + --Serdes - CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible - CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems - SERDES_INT_TX : out std_logic_vector(3 downto 0); - SERDES_INT_RX : in std_logic_vector(3 downto 0); - SERDES_ADDON_TX : out std_logic_vector(11 downto 0); - SERDES_ADDON_RX : in std_logic_vector(11 downto 0); - + CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible + CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems + SERDES_INT_TX : out std_logic_vector(3 downto 0); + SERDES_INT_RX : in std_logic_vector(3 downto 0); + SERDES_ADDON_TX : out std_logic_vector(11 downto 0); + SERDES_ADDON_RX : in std_logic_vector(11 downto 0); + --Inter-FPGA Communication - FPGA5_COMM : inout std_logic_vector(11 downto 0); - --Bit 0/1 input, serial link RX active - --Bit 2/3 output, serial link TX active - --others yet undefined + FPGA5_COMM : inout std_logic_vector(11 downto 0); + --Bit 0/1 input, serial link RX active + --Bit 2/3 output, serial link TX active + --others yet undefined --Connection to AddOn - SPARE_LINE : inout std_logic_vector(5 downto 0); --inputs only - DQUL : inout std_logic_vector(45 downto 0); - DQLL : inout std_logic_vector(47 downto 0); - DQUR : inout std_logic_vector(33 downto 0); - DQLR : inout std_logic_vector(35 downto 0); - --All DQ groups from one bank are grouped. - --All DQS are inserted in the DQ lines at position 6 and 7, DQ 6-9 are shifted to 8-11 - --Order per bank is kept, i.e. adjacent numbers have adjacent pins - --all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 is 6+2+2=10. - --even numbers are positive LVDS line, odd numbers are negative LVDS line - --DQUL can be switched to 1.8V + SPARE_LINE : inout std_logic_vector(5 downto 0); --inputs only + DQUL : inout std_logic_vector(45 downto 0); + DQLL : inout std_logic_vector(47 downto 0); + DQUR : inout std_logic_vector(33 downto 0); + DQLR : inout std_logic_vector(35 downto 0); + --All DQ groups from one bank are grouped. + --All DQS are inserted in the DQ lines at position 6 and 7, DQ 6-9 are shifted to 8-11 + --Order per bank is kept, i.e. adjacent numbers have adjacent pins + --all DQ blocks are 6+2+4=12 Pins wide, only DQUL3 is 6+2+2=10. + --even numbers are positive LVDS line, odd numbers are negative LVDS line + --DQUL can be switched to 1.8V --Flash ROM & Reboot - FLASH_CLK : out std_logic; - FLASH_CS : out std_logic; - FLASH_DIN : out std_logic; - FLASH_DOUT : in std_logic; - PROGRAMN : out std_logic; --reboot FPGA - + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_DIN : out std_logic; + FLASH_DOUT : in std_logic; + PROGRAMN : out std_logic; --reboot FPGA + --Misc - TEMPSENS : inout std_logic; --Temperature Sensor - CODE_LINE : in std_logic_vector(1 downto 0); - LED_GREEN : out std_logic; - LED_ORANGE : out std_logic; - LED_RED : out std_logic; - LED_YELLOW : out std_logic; - SUPPL : in std_logic; --terminated diff pair, PCLK, Pads + TEMPSENS : inout std_logic; --Temperature Sensor + CODE_LINE : in std_logic_vector(1 downto 0); + LED_GREEN : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_YELLOW : out std_logic; + SUPPL : in std_logic; --terminated diff pair, PCLK, Pads --Test Connectors - TEST_LINE : out std_logic_vector(15 downto 0) + TEST_LINE : out std_logic_vector(15 downto 0) ); - attribute syn_useioff : boolean; - --no IO-FF for LEDs relaxes timing constraints - attribute syn_useioff of LED_GREEN : signal is false; - attribute syn_useioff of LED_ORANGE : signal is false; - attribute syn_useioff of LED_RED : signal is false; - attribute syn_useioff of LED_YELLOW : signal is false; - attribute syn_useioff of TEMPSENS : signal is false; - attribute syn_useioff of PROGRAMN : signal is false; - attribute syn_useioff of CODE_LINE : signal is false; - attribute syn_useioff of TRIGGER_LEFT : signal is false; - attribute syn_useioff of TRIGGER_RIGHT : signal is false; - - --important signals _with_ IO-FF - attribute syn_useioff of FLASH_CLK : signal is true; - attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_DIN : signal is true; - attribute syn_useioff of FLASH_DOUT : signal is true; - attribute syn_useioff of FPGA5_COMM : signal is true; - attribute syn_useioff of TEST_LINE : signal is true; - attribute syn_useioff of DQLL : signal is true; - attribute syn_useioff of DQUL : signal is true; - attribute syn_useioff of DQLR : signal is true; - attribute syn_useioff of DQUR : signal is true; - attribute syn_useioff of SPARE_LINE : signal is true; + attribute syn_useioff : boolean; + --no IO-FF for LEDs relaxes timing constraints + attribute syn_useioff of LED_GREEN : signal is false; + attribute syn_useioff of LED_ORANGE : signal is false; + attribute syn_useioff of LED_RED : signal is false; + attribute syn_useioff of LED_YELLOW : signal is false; + attribute syn_useioff of TEMPSENS : signal is false; + attribute syn_useioff of PROGRAMN : signal is false; + attribute syn_useioff of CODE_LINE : signal is false; + attribute syn_useioff of TRIGGER_LEFT : signal is false; + attribute syn_useioff of TRIGGER_RIGHT : signal is false; + + --important signals _with_ IO-FF + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; + attribute syn_useioff of FLASH_DOUT : signal is true; + attribute syn_useioff of FPGA5_COMM : signal is true; + attribute syn_useioff of TEST_LINE : signal is true; + attribute syn_useioff of DQLL : signal is true; + attribute syn_useioff of DQUL : signal is true; + attribute syn_useioff of DQLR : signal is true; + attribute syn_useioff of DQUR : signal is true; + attribute syn_useioff of SPARE_LINE : signal is true; end entity; @@ -101,288 +101,307 @@ architecture trb3_periph_arch of trb3_periph is constant REGIO_NUM_STAT_REGS : integer := 2; constant REGIO_NUM_CTRL_REGS : integer := 2; - attribute syn_keep : boolean; + attribute syn_keep : boolean; attribute syn_preserve : boolean; --Clock / Reset - signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL - signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. - signal clear_i : std_logic; - signal reset_i : std_logic; - signal GSR_N : std_logic; - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; - + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + --Media Interface - signal med_stat_op : std_logic_vector (1*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); - signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0); - signal med_data_out : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); - signal med_dataready_out : std_logic; - signal med_read_out : std_logic; - signal med_data_in : std_logic_vector (1*16-1 downto 0); - signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); - signal med_dataready_in : std_logic; - signal med_read_in : std_logic; + signal med_stat_op : std_logic_vector (1*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (1*16-1 downto 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0); + signal med_data_out : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (1*3-1 downto 0); + signal med_dataready_out : std_logic; + signal med_read_out : std_logic; + signal med_data_in : std_logic_vector (1*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (1*3-1 downto 0); + signal med_dataready_in : std_logic; + signal med_read_in : std_logic; --LVL1 channel - signal timing_trg_received_i : std_logic; - signal trg_data_valid_i : std_logic; - signal trg_timing_valid_i : std_logic; - signal trg_notiming_valid_i : std_logic; - signal trg_invalid_i : std_logic; - signal trg_type_i : std_logic_vector(3 downto 0); - signal trg_number_i : std_logic_vector(15 downto 0); - signal trg_code_i : std_logic_vector(7 downto 0); - signal trg_information_i : std_logic_vector(23 downto 0); - signal trg_int_number_i : std_logic_vector(15 downto 0); + signal timing_trg_received_i : std_logic; + signal trg_data_valid_i : std_logic; + signal trg_timing_valid_i : std_logic; + signal trg_notiming_valid_i : std_logic; + signal trg_invalid_i : std_logic; + signal trg_type_i : std_logic_vector(3 downto 0); + signal trg_number_i : std_logic_vector(15 downto 0); + signal trg_code_i : std_logic_vector(7 downto 0); + signal trg_information_i : std_logic_vector(23 downto 0); + signal trg_int_number_i : std_logic_vector(15 downto 0); --Data channel - signal fee_trg_release_i : std_logic; - signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); - signal fee_data_i : std_logic_vector(31 downto 0); - signal fee_data_write_i : std_logic; - signal fee_data_finished_i : std_logic; - signal fee_almost_full_i : std_logic; + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + signal fee_data_i : std_logic_vector(31 downto 0); + signal fee_data_write_i : std_logic; + signal fee_data_finished_i : std_logic; + signal fee_almost_full_i : std_logic; --Slow Control channel - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); - signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); - signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); - signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); - + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + --RegIO - signal my_address : std_logic_vector (15 downto 0); - signal regio_addr_out : std_logic_vector (15 downto 0); - signal regio_read_enable_out : std_logic; - signal regio_write_enable_out : std_logic; - signal regio_data_out : std_logic_vector (31 downto 0); - signal regio_data_in : std_logic_vector (31 downto 0); - signal regio_dataready_in : std_logic; - signal regio_no_more_data_in : std_logic; - signal regio_write_ack_in : std_logic; - signal regio_unknown_addr_in : std_logic; - signal regio_timeout_out : std_logic; + signal my_address : std_logic_vector (15 downto 0); + signal regio_addr_out : std_logic_vector (15 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (31 downto 0); + signal regio_data_in : std_logic_vector (31 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; --Timer - signal global_time : std_logic_vector(31 downto 0); - signal local_time : std_logic_vector(7 downto 0); - signal time_since_last_trg : std_logic_vector(31 downto 0); - signal timer_ticks : std_logic_vector(1 downto 0); - + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + --Flash - signal spictrl_read_en : std_logic; - signal spictrl_write_en : std_logic; - signal spictrl_data_in : std_logic_vector(31 downto 0); - signal spictrl_addr : std_logic; - signal spictrl_data_out : std_logic_vector(31 downto 0); - signal spictrl_ack : std_logic; - signal spictrl_busy : std_logic; - signal spimem_read_en : std_logic; - signal spimem_write_en : std_logic; - signal spimem_data_in : std_logic_vector(31 downto 0); - signal spimem_addr : std_logic_vector(5 downto 0); - signal spimem_data_out : std_logic_vector(31 downto 0); - signal spimem_ack : std_logic; - - signal spi_bram_addr : std_logic_vector(7 downto 0); - signal spi_bram_wr_d : std_logic_vector(7 downto 0); - signal spi_bram_rd_d : std_logic_vector(7 downto 0); - signal spi_bram_we : std_logic; + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + - --FPGA Test signal time_counter : unsigned(31 downto 0); + + --TDC component + component TDC + generic ( + CHANNEL_NUMBER : integer range 0 to 64); + port ( + RESET : in std_logic; + CLK_TDC : in std_logic; + CLK_READOUT : in std_logic; + HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + TRIGGER_IN : in std_logic; + TRIGGER_WIN_IN : in std_logic_vector(31 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + TRB_WR_CLK_OUT : out std_logic; + DATA_VALID_OUT : out std_logic; + DATA_FINISHED_OUT : out std_logic; + READY_OUT : out std_logic; + TDC_DEBUG_00 : out std_logic_vector(31 downto 0)); + end component; begin --------------------------------------------------------------------------- -- Reset Generation --------------------------------------------------------------------------- -GSR_N <= pll_lock; - -THE_RESET_HANDLER : trb_net_reset_handler - generic map( - RESET_DELAY => x"FEEE" - ) - port map( - CLEAR_IN => '0', -- reset input (high active, async) - CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock - PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) - RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) - CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! - RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) - DEBUG_OUT => open - ); + GSR_N <= pll_lock; + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"FEEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); --------------------------------------------------------------------------- -- Clock Handling --------------------------------------------------------------------------- -THE_MAIN_PLL : pll_in125_out125 - port map( - CLK => CLK_GPLL_LEFT, --CLK_GPLL_RIGHT - CLKOP => clk_100_i, - CLKOK => clk_200_i, - LOCK => pll_lock - ); + THE_MAIN_PLL : pll_in125_out125 + port map( + CLK => CLK_GPLL_LEFT, --CLK_GPLL_RIGHT + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) --------------------------------------------------------------------------- -THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp - generic map( - SERDES_NUM => 1, --number of serdes in quad - EXT_CLOCK => c_NO, --use internal clock - USE_200_MHZ => c_YES --run on 200 MHz clock - ) - port map( - CLK => clk_200_i, - SYSCLK => clk_100_i, - RESET => reset_i, - CLEAR => clear_i, - CLK_EN => '1', - --Internal Connection - MED_DATA_IN => med_data_out, - MED_PACKET_NUM_IN => med_packet_num_out, - MED_DATAREADY_IN => med_dataready_out, - MED_READ_OUT => med_read_in, - MED_DATA_OUT => med_data_in, - MED_PACKET_NUM_OUT => med_packet_num_in, - MED_DATAREADY_OUT => med_dataready_in, - MED_READ_IN => med_read_out, - REFCLK2CORE_OUT => open, - --SFP Connection - SD_RXD_P_IN => SERDES_INT_RX(2), - SD_RXD_N_IN => SERDES_INT_RX(3), - SD_TXD_P_OUT => SERDES_INT_TX(2), - SD_TXD_N_OUT => SERDES_INT_TX(3), - SD_REFCLK_P_IN => open, - SD_REFCLK_N_IN => open, - SD_PRSNT_N_IN => FPGA5_COMM(0), - SD_LOS_IN => FPGA5_COMM(0), - SD_TXDIS_OUT => FPGA5_COMM(2), - -- Status and control port - STAT_OP => med_stat_op, - CTRL_OP => med_ctrl_op, - STAT_DEBUG => med_stat_debug, - CTRL_DEBUG => (others => '0') - ); + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp + generic map( + SERDES_NUM => 1, --number of serdes in quad + EXT_CLOCK => c_NO, --use internal clock + USE_200_MHZ => c_YES --run on 200 MHz clock + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SERDES_INT_RX(2), + SD_RXD_N_IN => SERDES_INT_RX(3), + SD_TXD_P_OUT => SERDES_INT_TX(2), + SD_TXD_N_OUT => SERDES_INT_TX(3), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => FPGA5_COMM(0), + SD_LOS_IN => FPGA5_COMM(0), + SD_TXDIS_OUT => FPGA5_COMM(2), + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') + ); --------------------------------------------------------------------------- -- Endpoint --------------------------------------------------------------------------- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler generic map( - REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS,--4, --16 stat reg - REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,--3, --8 cotrol reg - ADDRESS_MASK => x"FFFF", - BROADCAST_BITMASK => x"FF", - BROADCAST_SPECIAL_ADDR => x"45", - REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), - REGIO_HARDWARE_VERSION => x"91000001", - REGIO_INIT_ADDRESS => x"f300", - REGIO_USE_VAR_ENDPOINT_ID => c_YES, - CLOCK_FREQUENCY => 125, - TIMING_TRIGGER_RAW => c_YES, + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + BROADCAST_SPECIAL_ADDR => x"45", + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), + REGIO_HARDWARE_VERSION => x"91000001", + REGIO_INIT_ADDRESS => x"f300", + REGIO_USE_VAR_ENDPOINT_ID => c_YES, + CLOCK_FREQUENCY => 125, + TIMING_TRIGGER_RAW => c_YES, --Configure data handler - DATA_INTERFACE_NUMBER => 1, - DATA_BUFFER_DEPTH => 13, --13 - DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024 - TRG_RELEASE_AFTER_DATA => c_YES, - HEADER_BUFFER_DEPTH => 9, - HEADER_BUFFER_FULL_THRESH => 2**9-16 + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 13, --13 + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024 + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 ) port map( - CLK => clk_100_i, - RESET => reset_i, - CLK_EN => '1', - MED_DATAREADY_OUT => med_dataready_out, -- open, -- - MED_DATA_OUT => med_data_out, -- open, -- - MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- - MED_READ_IN => med_read_in, - MED_DATAREADY_IN => med_dataready_in, - MED_DATA_IN => med_data_in, - MED_PACKET_NUM_IN => med_packet_num_in, - MED_READ_OUT => med_read_out, -- open, -- - MED_STAT_OP_IN => med_stat_op, - MED_CTRL_OP_OUT => med_ctrl_op, + CLK => clk_100_i, + RESET => reset_i, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, -- open, -- + MED_DATA_OUT => med_data_out, -- open, -- + MED_PACKET_NUM_OUT => med_packet_num_out, -- open, -- + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, -- open, -- + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, --Timing trigger in - TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, --LVL1 trigger to FEE - LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, - LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, - LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, - LVL1_INVALID_TRG_OUT => trg_invalid_i, + LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, + LVL1_INVALID_TRG_OUT => trg_invalid_i, - LVL1_TRG_TYPE_OUT => trg_type_i, - LVL1_TRG_NUMBER_OUT => trg_number_i, - LVL1_TRG_CODE_OUT => trg_code_i, - LVL1_TRG_INFORMATION_OUT => trg_information_i, - LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, + LVL1_TRG_TYPE_OUT => trg_type_i, + LVL1_TRG_NUMBER_OUT => trg_number_i, + LVL1_TRG_CODE_OUT => trg_code_i, + LVL1_TRG_INFORMATION_OUT => trg_information_i, + LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, --Response from FEE - FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, - FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, - FEE_DATA_IN => fee_data_i, - FEE_DATA_WRITE_IN(0) => fee_data_write_i, - FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, - FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, + FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, + FEE_DATA_IN => fee_data_i, + FEE_DATA_WRITE_IN(0) => fee_data_write_i, + FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, + FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 - REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, - REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, - REGIO_STAT_REG_IN => stat_reg, --start 0x80 - REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 - REGIO_STAT_STROBE_OUT => stat_reg_strobe, - REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, - REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, - REGIO_VAR_ENDPOINT_ID(15 downto 2)=> (others => '0'), - - BUS_ADDR_OUT => regio_addr_out, - BUS_READ_ENABLE_OUT => regio_read_enable_out, - BUS_WRITE_ENABLE_OUT => regio_write_enable_out, - BUS_DATA_OUT => regio_data_out, - BUS_DATA_IN => regio_data_in, - BUS_DATAREADY_IN => regio_dataready_in, - BUS_NO_MORE_DATA_IN => regio_no_more_data_in, - BUS_WRITE_ACK_IN => regio_write_ack_in, - BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, - BUS_TIMEOUT_OUT => regio_timeout_out, - ONEWIRE_INOUT => TEMPSENS, - ONEWIRE_MONITOR_OUT => open, - - TIME_GLOBAL_OUT => global_time, - TIME_LOCAL_OUT => local_time, - TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, - TIME_TICKS_OUT => timer_ticks, - - STAT_DEBUG_IPU => open, - STAT_DEBUG_1 => open, - STAT_DEBUG_2 => open, - STAT_DEBUG_DATA_HANDLER_OUT=> open, - STAT_DEBUG_IPU_HANDLER_OUT => open, - STAT_TRIGGER_OUT => open, - CTRL_MPLEX => (others => '0'), - IOBUF_CTRL_GEN => (others => '0'), - STAT_ONEWIRE => open, - STAT_ADDR_DEBUG => open, - DEBUG_LVL1_HANDLER_OUT => open + REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00 + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => stat_reg, --start 0x80 + REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0 + REGIO_STAT_STROBE_OUT => stat_reg_strobe, + REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE, + REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'), + + BUS_ADDR_OUT => regio_addr_out, + BUS_READ_ENABLE_OUT => regio_read_enable_out, + BUS_WRITE_ENABLE_OUT => regio_write_enable_out, + BUS_DATA_OUT => regio_data_out, + BUS_DATA_IN => regio_data_in, + BUS_DATAREADY_IN => regio_dataready_in, + BUS_NO_MORE_DATA_IN => regio_no_more_data_in, + BUS_WRITE_ACK_IN => regio_write_ack_in, + BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + BUS_TIMEOUT_OUT => regio_timeout_out, + ONEWIRE_INOUT => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks, + + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT => open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + STAT_TRIGGER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open, + DEBUG_LVL1_HANDLER_OUT => open ); --------------------------------------------------------------------------- @@ -396,145 +415,168 @@ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- -THE_BUS_HANDLER : trb_net16_regio_bus_handler - generic map( - PORT_NUMBER => 2, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0) - ) - port map( - CLK => clk_100_i, - RESET => reset_i, - - DAT_ADDR_IN => regio_addr_out, - DAT_DATA_IN => regio_data_out, - DAT_DATA_OUT => regio_data_in, - DAT_READ_ENABLE_IN => regio_read_enable_out, - DAT_WRITE_ENABLE_IN => regio_write_enable_out, - DAT_TIMEOUT_IN => regio_timeout_out, - DAT_DATAREADY_OUT => regio_dataready_in, - DAT_WRITE_ACK_OUT => regio_write_ack_in, - DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, - DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, - - --Bus Handler (SPI CTRL) - BUS_READ_ENABLE_OUT(0) => spictrl_read_en, - BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, - BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, - BUS_ADDR_OUT(0*16) => spictrl_addr, - BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, - BUS_DATAREADY_IN(0) => spictrl_ack, - BUS_WRITE_ACK_IN(0) => spictrl_ack, - BUS_NO_MORE_DATA_IN(0) => spictrl_busy, - BUS_UNKNOWN_ADDR_IN(0) => '0', - --Bus Handler (SPI Memory) - BUS_READ_ENABLE_OUT(1) => spimem_read_en, - BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, - BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, - BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, - BUS_DATAREADY_IN(1) => spimem_ack, - BUS_WRITE_ACK_IN(1) => spimem_ack, - BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(1) => '0', - - STAT_DEBUG => open - ); + THE_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 2, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0) + ) + port map( + CLK => clk_100_i, + RESET => reset_i, + + DAT_ADDR_IN => regio_addr_out, + DAT_DATA_IN => regio_data_out, + DAT_DATA_OUT => regio_data_in, + DAT_READ_ENABLE_IN => regio_read_enable_out, + DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_TIMEOUT_IN => regio_timeout_out, + DAT_DATAREADY_OUT => regio_dataready_in, + DAT_WRITE_ACK_OUT => regio_write_ack_in, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in, + + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + + STAT_DEBUG => open + ); --------------------------------------------------------------------------- -- SPI / Flash --------------------------------------------------------------------------- -THE_SPI_MASTER: spi_master - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_READ_IN => spictrl_read_en, - BUS_WRITE_IN => spictrl_write_en, - BUS_BUSY_OUT => spictrl_busy, - BUS_ACK_OUT => spictrl_ack, - BUS_ADDR_IN(0) => spictrl_addr, - BUS_DATA_IN => spictrl_data_in, - BUS_DATA_OUT => spictrl_data_out, - -- SPI connections - SPI_CS_OUT => FLASH_CS, - SPI_SDI_IN => FLASH_DOUT, - SPI_SDO_OUT => FLASH_DIN, - SPI_SCK_OUT => FLASH_CLK, - -- BRAM for read/write data - BRAM_A_OUT => spi_bram_addr, - BRAM_WR_D_IN => spi_bram_wr_d, - BRAM_RD_D_OUT => spi_bram_rd_d, - BRAM_WE_OUT => spi_bram_we, - -- Status lines - STAT => open - ); + THE_SPI_MASTER : spi_master + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => FLASH_CS, + SPI_SDI_IN => FLASH_DOUT, + SPI_SDO_OUT => FLASH_DIN, + SPI_SCK_OUT => FLASH_CLK, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); -- data memory for SPI accesses -THE_SPI_MEMORY: spi_databus_memory - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_ADDR_IN => spimem_addr, - BUS_READ_IN => spimem_read_en, - BUS_WRITE_IN => spimem_write_en, - BUS_ACK_OUT => spimem_ack, - BUS_DATA_IN => spimem_data_in, - BUS_DATA_OUT => spimem_data_out, - -- state machine connections - BRAM_ADDR_IN => spi_bram_addr, - BRAM_WR_D_OUT => spi_bram_wr_d, - BRAM_RD_D_IN => spi_bram_rd_d, - BRAM_WE_IN => spi_bram_we, - -- Status lines - STAT => open - ); - + THE_SPI_MEMORY : spi_databus_memory + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + --------------------------------------------------------------------------- -- Reboot FPGA --------------------------------------------------------------------------- -THE_FPGA_REBOOT : fpga_reboot - port map( - CLK => clk_100_i, - RESET => reset_i, - DO_REBOOT => common_ctrl_reg(15), - PROGRAMN => PROGRAMN - ); + THE_FPGA_REBOOT : fpga_reboot + port map( + CLK => clk_100_i, + RESET => reset_i, + DO_REBOOT => common_ctrl_reg(15), + PROGRAMN => PROGRAMN + ); + - --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- - LED_GREEN <= not med_stat_op(9); - LED_ORANGE <= not med_stat_op(10); - LED_RED <= not time_counter(26); - LED_YELLOW <= not med_stat_op(11); + LED_GREEN <= not med_stat_op(9); + LED_ORANGE <= not med_stat_op(10); + LED_RED <= not time_counter(26); + LED_YELLOW <= not med_stat_op(11); --------------------------------------------------------------------------- -- Test Connector --------------------------------------------------------------------------- - TEST_LINE( 7 downto 0) <= med_data_in(7 downto 0); - TEST_LINE( 8) <= med_dataready_in; - TEST_LINE( 9) <= med_dataready_out; - TEST_LINE(10) <= stat_reg_strobe(0); - TEST_LINE(15 downto 11) <= (others => '0'); + TEST_LINE(7 downto 0) <= med_data_in(7 downto 0); + TEST_LINE(8) <= med_dataready_in; + TEST_LINE(9) <= med_dataready_out; + TEST_LINE(10) <= stat_reg_strobe(0); + TEST_LINE(15 downto 11) <= (others => '0'); --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- process - begin - wait until rising_edge(clk_100_i); - time_counter <= time_counter + 1; - end process; - -end architecture; \ No newline at end of file + begin + wait until rising_edge(clk_100_i); + time_counter <= time_counter + 1; + end process; + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + + THE_TDC : TDC + generic map ( + CHANNEL_NUMBER => 8) -- Number of TDC channels + port map ( + RESET => reset_i, + CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement + CLK_READOUT => clk_100_i, -- Clock for the readout + HIT_IN => DQUL(7 downto 0), -- Channel start signals + TRIGGER_IN => trg_timing_valid_i, -- Readout trigger + TRIGGER_WIN_IN => x"00640000", -- Trigger window register relative to + -- the trigger (post edge & pre edge) + DATA_OUT => fee_data_i, -- Data to readout + TRB_WR_CLK_OUT => open, -- Readout clk (maybe not necessary + -- in trb3) + DATA_VALID_OUT => fee_data_write_i, -- Data valid signal + DATA_FINISHED_OUT => fee_data_finished_i, -- Readout finished signal + READY_OUT => fee_trg_release_i, -- Ready for the next trigger + TDC_DEBUG_00 => open); -- Debug + +end architecture;