From: Benedikt Gutsche Date: Fri, 30 Aug 2024 09:03:25 +0000 (+0200) Subject: better vldb core X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c8bc52eac5feda30d947ebe4284c662d77d4b830;p=trb5sc.git better vldb core --- diff --git a/vldb/code/gbt_core.vhd b/vldb/code/gbt_core.vhd index 85f268a..46cffb4 100644 --- a/vldb/code/gbt_core.vhd +++ b/vldb/code/gbt_core.vhd @@ -27,42 +27,45 @@ end entity; architecture arch of gbt_core is -- Clock & reset - signal gbtsc_tx_clk_en : std_logic := '0'; --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled - signal gbtsc_rx_clk_en : std_logic := '0'; --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled + signal gbtsc_tx_clk_en : std_logic := '0'; + signal gbtsc_rx_clk_en : std_logic := '0'; -- SCA control - signal gbtsc_sca_enable_i : std_logic := '1'; --! Enable flag to select SCAs - signal gbtsc_start_reset_cmd_i : std_logic := '0'; --! Send a reset command to the enabled SCAs - signal gbtsc_start_connect_cmd_i : std_logic := '0'; --! Send a connect command to the enabled SCAs - signal gbtsc_start_command_i : std_logic := '0'; --! Send the command set in input to the enabled SCAs + signal gbtsc_sca_enable_i : std_logic := '1'; --! Enable flag to select SCAs + signal gbtsc_start_reset_cmd_i : std_logic := '0'; --! Send a reset command to the enabled SCAs + signal gbtsc_start_connect_cmd_i : std_logic := '0'; --! Send a connect command to the enabled SCAs + signal gbtsc_start_command_i : std_logic := '0'; --! Send the command in input to the enabled SCAs signal gbtsc_start_reset_cmd_raw :std_logic := '0'; signal gbtsc_start_connect_cmd_raw :std_logic := '0'; signal gbtsc_start_command_raw :std_logic := '0'; signal gbtsc_reset_go : std_logic := '0'; signal gbtsc_connect_go : std_logic := '0'; signal gbtsc_go : std_logic := '0'; + -- SCA command - signal gbtsc_tx_address_i : std_logic_vector(7 downto 0) := x"00"; --! Command: address field (According to the SCA manual) - signal gbtsc_tx_transID_i : std_logic_vector(7 downto 0) := x"01"; --! Command: transaction ID field (According to the SCA manual) - signal gbtsc_tx_channel_i : std_logic_vector(7 downto 0) := x"00"; --! Command: channel field (According to the SCA manual) - signal gbtsc_tx_command_i : std_logic_vector(7 downto 0) := x"02"; --! Command: command field (According to the SCA manual) - signal gbtsc_tx_data_i : std_logic_vector(31 downto 0) := x"0000FF00"; --! Command: data field (According to the SCA manual) - - signal gbtsc_rx_received_o : std_logic := '0'; --! Reply received flag (pulse) - signal gbtsc_rx_address_o : std_logic_vector(7 downto 0); --! Reply: address field (According to the SCA manual) - signal gbtsc_rx_control_o : std_logic_vector(7 downto 0); --! Reply: control field (According to the SCA manual) - signal gbtsc_rx_transID_o : std_logic_vector(7 downto 0); --! Reply: transaction ID field (According to the SCA manual) - signal gbtsc_rx_channel_o : std_logic_vector(7 downto 0); --! Reply: channel field (According to the SCA manual) - signal gbtsc_rx_len_o : std_logic_vector(7 downto 0); --! Reply: len field (According to the SCA manual) - signal gbtsc_rx_error_o : std_logic_vector(7 downto 0); --! Reply: error field (According to the SCA manual) - signal gbtsc_rx_data_o : std_logic_vector(31 downto 0); --! Reply: data field (According to the SCA manual) - signal sync_reg : std_logic_vector(79 downto 0); -- register for syncing + signal gbtsc_tx_address_i : std_logic_vector(7 downto 0) := x"00"; + signal gbtsc_tx_transID_i : std_logic_vector(7 downto 0) := x"01"; + signal gbtsc_tx_channel_i : std_logic_vector(7 downto 0) := x"00"; + signal gbtsc_tx_command_i : std_logic_vector(7 downto 0) := x"02"; + signal gbtsc_tx_data_i : std_logic_vector(31 downto 0) := x"0000FF00"; + + signal gbtsc_rx_received_o : std_logic := '0'; + signal gbtsc_rx_address_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_control_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_transID_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_channel_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_len_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_error_o : std_logic_vector(7 downto 0); + signal gbtsc_rx_data_o : std_logic_vector(31 downto 0); + signal sync_reg : std_logic_vector(79 downto 0); signal sync_reg_done_100 : std_logic := '0'; signal sync_reg_done_40 : std_logic := '0'; -- EC line - signal hdlc_from_gbtsc : std_logic_vector(1 downto 0) := "11"; --! (TX) Array of bits to be mapped to the TX GBT-Frame - signal hdlc_to_gbtsc : std_logic_vector(1 downto 0) := "11"; --! (RX) Array of bits to be mapped to the RX GBT-Frame + signal hdlc_from_gbtsc : std_logic_vector(1 downto 0) := "11"; + signal hdlc_to_gbtsc : std_logic_vector(1 downto 0) := "11"; + + signal hdlc_des : std_logic_vector(3 downto 0); signal test_out : std_logic_vector(7 downto 0) := (others => '0'); signal counter : unsigned(23 downto 0); @@ -74,44 +77,41 @@ begin THE_GBTSC_TOP : entity work.gbtsc_top generic map( - -- IC configuration - g_IC_FIFO_DEPTH => 20, --! Defines the depth of the FIFO used to handle the Internal control (Max. number of words/bytes can be read/write from/to a GBTx) - - -- EC configuration - g_SCA_COUNT => 1 --! Defines the maximum number of SCA that can be connected to this module + g_IC_FIFO_DEPTH => 20, + g_SCA_COUNT => 1 ) port map( -- Clock & reset - tx_clk_i => CLK, -- gbtsc_tx_clk_i, --! Tx clock (Tx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency - tx_clk_en => gbtsc_tx_clk_en, --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled - tx_reset_i => RESET, -- gbtsc_tx_reset_i, --! Reset TX datapath + tx_clk_i => CLK, + tx_clk_en => gbtsc_tx_clk_en, + tx_reset_i => RESET, - rx_clk_i => CLK, -- gbtsc_rx_clk_i, --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency - rx_clk_en => gbtsc_rx_clk_en, --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled - rx_reset_i => RESET, -- gbtsc_rx_reset_i, --! Reset RX datapath + rx_clk_i => CLK, + rx_clk_en => gbtsc_rx_clk_en, + rx_reset_i => RESET, -- IC control - tx_start_write_i => '0', -- gbtsc_tx_start_write_i, --! Request a write config. to the GBTx (IC) - tx_start_read_i => '0', -- gbtsc_tx_start_read_i, --! Request a read config. to the GBTx (IC) + tx_start_write_i => '0', + tx_start_read_i => '0', -- IC configuration - tx_GBTx_address_i => (others => '0'), -- gbtsc_tx_GBTx_address_i, --! I2C address of the GBTx - tx_register_addr_i => (others => '0'), -- gbtsc_tx_register_addr_i, --! Address of the first register to be accessed - tx_nb_to_be_read_i => (others => '0'), -- gbtsc_tx_nb_to_be_read_i, --! Number of words/bytes to be read (only for read transactions) + tx_GBTx_address_i => (others => '0'), + tx_register_addr_i => (others => '0'), + tx_nb_to_be_read_i => (others => '0'), -- IC FIFO control - wr_clk_i => CLK, --! Fifo's writing clock - tx_wr_i => '0', -- gbtsc_tx_wr_i, --! Request a write operation into the internal FIFO (Data to GBTx) - tx_data_to_gbtx_i => (others => '0'), -- gbtsc_tx_data_to_gbtx_i, --! Data to be written into the internal FIFO + wr_clk_i => CLK, + tx_wr_i => '0', + tx_data_to_gbtx_i => (others => '0'), rd_clk_i => CLK, - rx_rd_i => '0', -- gbtsc_rx_rd_i, --! Request a read operation of the internal FIFO (GBTx reply) - rx_data_from_gbtx_o => open, -- gbtsc_rx_data_from_gbtx_o, --! Data from the FIFO + rx_rd_i => '0', + rx_data_from_gbtx_o => open, -- IC Status - tx_ready_o => open, -- gbtsc_tx_ready_o, --! IC core ready for a transaction - rx_empty_o => open, -- gbtsc_rx_empty_o, --! Rx FIFO is empty (no reply from GBTx) + tx_ready_o => open, + rx_empty_o => open, -- SCA control sca_enable_i(0) => gbtsc_sca_enable_i, --! Enable flag to select SCAs @@ -121,28 +121,28 @@ begin inject_crc_error => '0', --! Emulate a CRC error -- SCA command - tx_address_i => gbtsc_tx_address_i, --! Command: address field (According to the SCA manual) - tx_transID_i => gbtsc_tx_transID_i, --! Command: transaction ID field (According to the SCA manual) - tx_channel_i => gbtsc_tx_channel_i, --! Command: channel field (According to the SCA manual) - tx_command_i => gbtsc_tx_command_i, --! Command: command field (According to the SCA manual) - tx_data_i => gbtsc_tx_data_i, --! Command: data field (According to the SCA manual) - - rx_received_o(0) => gbtsc_rx_received_o, --! Reply: received flag (pulse) - rx_address_o(0) => gbtsc_rx_address_o, --! Reply: address field (According to the SCA manual) - rx_control_o(0) => gbtsc_rx_control_o, --! Reply: control field (According to the SCA manual) - rx_transID_o(0) => gbtsc_rx_transID_o, --! Reply: transaction ID field (According to the SCA manual) - rx_channel_o(0) => gbtsc_rx_channel_o, --! Reply: channel field (According to the SCA manual) - rx_len_o(0) => gbtsc_rx_len_o, --! Reply: len field (According to the SCA manual) - rx_error_o(0) => gbtsc_rx_error_o, --! Reply: error field (According to the SCA manual) - rx_data_o(0) => gbtsc_rx_data_o, --! Reply: data field (According to the SCA manual) + tx_address_i => gbtsc_tx_address_i, --! Address field (According to the SCA manual) + tx_transID_i => gbtsc_tx_transID_i, --! Transaction ID field (According to the SCA manual) + tx_channel_i => gbtsc_tx_channel_i, --! Channel field (According to the SCA manual) + tx_command_i => gbtsc_tx_command_i, --! Command field (According to the SCA manual) + tx_data_i => gbtsc_tx_data_i, --! Data field (According to the SCA manual) + + rx_received_o(0) => gbtsc_rx_received_o, --! Received flag (pulse) + rx_address_o(0) => gbtsc_rx_address_o, --! Address field (According to the SCA manual) + rx_control_o(0) => gbtsc_rx_control_o, --! Control field (According to the SCA manual) + rx_transID_o(0) => gbtsc_rx_transID_o, --! Transaction ID field (According to the SCA manual) + rx_channel_o(0) => gbtsc_rx_channel_o, --! Channel field (According to the SCA manual) + rx_len_o(0) => gbtsc_rx_len_o, --! Len field (According to the SCA manual) + rx_error_o(0) => gbtsc_rx_error_o, --! Error field (According to the SCA manual) + rx_data_o(0) => gbtsc_rx_data_o, --! Data field (According to the SCA manual) -- EC line - ec_data_o(0) => hdlc_from_gbtsc, --! (TX) Array of bits to be mapped to the TX GBT-Frame - ec_data_i(0) => hdlc_to_gbtsc, --! (RX) Array of bits to be mapped to the RX GBT-Frame + ec_data_o(0) => hdlc_from_gbtsc, + ec_data_i(0) => hdlc_to_gbtsc, -- IC lines - ic_data_o => open, --! (TX) Array of bits to be mapped to the TX GBT-Frame (bits 83/84) - ic_data_i => "00" --! (RX) Array of bits to be mapped to the RX GBT-Frame (bits 83/84) + ic_data_o => open, + ic_data_i => "00" ); @@ -188,28 +188,27 @@ begin -- HDLC serializer hdlcser_proc: process(CLK_80) + variable bitflip : std_logic := '0'; begin if rising_edge(CLK_80) then - if CLK = '1' then + if bitflip = '1' then ELINK_TX <= hdlc_from_gbtsc(1); else ELINK_TX <= hdlc_from_gbtsc(0); end if; + bitflip := not bitflip; + hdlc_des <= hdlc_des(2 downto 0) & ELINK_RX; end if; end process; - -- HDLC deserializer - hdlcdes_proc: process(CLK_80) - variable hdlc_des: std_logic_vector(1 downto 0); + + elink_input_proc: process(CLK) begin - if rising_edge(CLK_80) then - hdlc_des := hdlc_des(0) & ELINK_RX; - if CLK = '1' then - hdlc_to_gbtsc <= hdlc_des; - end if; + if rising_edge(CLK) then + hdlc_to_gbtsc <= hdlc_des(3) & hdlc_des(2); end if; end process; - + PROC_GBTSCA_REG_CMDS : process begin @@ -228,17 +227,17 @@ begin BUS_TX.ack <= '1'; if BUS_RX.addr(3 downto 0) = x"0" then - gbtsc_tx_address_i <= BUS_RX.data(7 downto 0); -- hdlc Address + gbtsc_tx_address_i <= BUS_RX.data(7 downto 0); elsif BUS_RX.addr(3 downto 0) = x"1" then - gbtsc_reset_go <= BUS_RX.data(0); -- gbtsca RESET - gbtsc_connect_go <= BUS_RX.data(1); -- gbtsca CONNECT - gbtsc_go <= BUS_RX.data(2); -- gbtsca Start Command + gbtsc_reset_go <= BUS_RX.data(0); + gbtsc_connect_go <= BUS_RX.data(1); + gbtsc_go <= BUS_RX.data(2); elsif BUS_RX.addr(3 downto 0) = x"2" then - gbtsc_tx_transID_i <= BUS_RX.data(7 downto 0); -- gbtsca TransID - gbtsc_tx_channel_i <= BUS_RX.data(15 downto 8); -- gbtsca Channel - gbtsc_tx_command_i <= BUS_RX.data(23 downto 16); -- gbtsca Command + gbtsc_tx_transID_i <= BUS_RX.data(7 downto 0); + gbtsc_tx_channel_i <= BUS_RX.data(15 downto 8); + gbtsc_tx_command_i <= BUS_RX.data(23 downto 16); elsif BUS_RX.addr(3 downto 0) = x"3" then - gbtsc_tx_data_i <= BUS_RX.data(31 downto 0); -- gbtsca Data + gbtsc_tx_data_i <= BUS_RX.data(31 downto 0); else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; @@ -248,15 +247,15 @@ begin BUS_TX.ack <= '1'; if BUS_RX.addr(3 downto 0) = x"a" then - BUS_TX.data(7 downto 0) <= sync_reg(79 downto 72); -- hdlc Address - BUS_TX.data(15 downto 8) <= sync_reg(71 downto 64); -- hdlc Control + BUS_TX.data(7 downto 0) <= sync_reg(79 downto 72); + BUS_TX.data(15 downto 8) <= sync_reg(71 downto 64); elsif BUS_RX.addr(3 downto 0) = x"b" then - BUS_TX.data( 7 downto 0 ) <= sync_reg(63 downto 56); -- gbtsca TransID - BUS_TX.data(15 downto 8 ) <= sync_reg(55 downto 48); -- gbtsca Channel - BUS_TX.data(23 downto 16) <= sync_reg(47 downto 40); -- gbtsca Error - BUS_TX.data(31 downto 24) <= sync_reg(39 downto 32); -- gbtsca Length + BUS_TX.data( 7 downto 0 ) <= sync_reg(63 downto 56); + BUS_TX.data(15 downto 8 ) <= sync_reg(55 downto 48); + BUS_TX.data(23 downto 16) <= sync_reg(47 downto 40); + BUS_TX.data(31 downto 24) <= sync_reg(39 downto 32); elsif BUS_RX.addr(3 downto 0) = x"c" then - BUS_TX.data(31 downto 0) <= sync_reg(31 downto 0); -- gbtsca Data + BUS_TX.data(31 downto 0) <= sync_reg(31 downto 0); sync_reg_done_100 <= '1'; else BUS_TX.ack <= '0'; @@ -307,5 +306,4 @@ begin PULSE_B_OUT => sync_reg_done_40 ); - end architecture; diff --git a/vldb/par.p2t b/vldb/par.p2t index 90538cf..9c0aff1 100644 --- a/vldb/par.p2t +++ b/vldb/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 48 +-t 25 -c 2 -e 2 -i 10 diff --git a/vldb/trb5sc_mimosis.vhd b/vldb/trb5sc_mimosis.vhd index 0c45747..8cba1dc 100644 --- a/vldb/trb5sc_mimosis.vhd +++ b/vldb/trb5sc_mimosis.vhd @@ -10,6 +10,7 @@ use work.trb_net_components.all; use work.trb3_components.all; use work.med_sync_define.all; + entity trb5sc_mimosis is port( CLK_200 : in std_logic; @@ -148,9 +149,9 @@ architecture arch of trb5sc_mimosis is signal i2c_reg_2 : std_logic_vector(31 downto 0); signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); signal mimosis_scl_drv, mimosis_sda_drv : std_logic; - signal i2c_go_100, i2c_go : std_logic; - signal i2c_reg_5_40 : std_logic_vector(31 downto 0); - signal counter : unsigned(23 downto 0); + signal i2c_go_100, i2c_go : std_logic; + signal i2c_reg_5_40 : std_logic_vector(31 downto 0); + signal counter : unsigned(23 downto 0); --signal fwd_dst_mac : std_logic_vector(47 downto 0); --signal fwd_dst_ip : std_logic_vector(31 downto 0); @@ -212,7 +213,7 @@ begin THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync generic map( SERDES_NUM => SERDES_NUM, - USE_NEW_ECP5_RESET => 0, + USE_NEW_ECP5_RESET => 1, IS_SYNC_SLAVE => c_YES ) port map( @@ -551,6 +552,7 @@ begin LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4)); LED_ADDON_SFP_ORANGE(1) <= '0'; + ----------------------------------------------------------------------------- ---- GbE ----------------------------------------------------------------------------- @@ -687,43 +689,6 @@ begin --end process; ---------------------------------------------------------------------------- --- Output stage ---------------------------------------------------------------------------- - THE_OUT : entity work.testout - port map( - clkout => open, - refclk => clk_160, - reset => reset_i, - data => out_data, - data_cflag => open, - data_direction => (others => '0'), - data_loadn => (others => '1'), - data_move => (others => '0'), - dout => out_i - ); - - PROC_OUT : process - variable cnt : integer range 0 to 7; - begin - wait until rising_edge(clk_160); - cnt := cnt + 1; - case cnt is - when 0 => out_data <= x"ffff"; - when 1 => out_data <= x"ffff"; - when 2 => out_data <= x"ffff"; - when 3 => out_data <= x"0000"; - when 4 => out_data <= x"5555"; - when 5 => out_data <= x"5555"; - when 6 => out_data <= x"5555"; - when 7 => out_data <= x"5555"; - end case; - end process; - - -- H3(3 downto 0) <= out_i(3 downto 0); - -- H4(3 downto 0) <= out_i(7 downto 4); - - --------------------------------------------------------------------------- -- GBT Core --------------------------------------------------------------------------- @@ -739,6 +704,7 @@ begin TESTOUT => LED, + -- ELINK_RX => H3(2), ELINK_RX => H3_2, ELINK_TX => H3(0) );