From: palka Date: Thu, 29 May 2008 13:29:04 +0000 (+0000) Subject: med_packet out was wrong X-Git-Tag: oldGBE~558 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c8f67749bbb823c799bcfc110d22f17e5e6c0f25;p=trbnet.git med_packet out was wrong --- diff --git a/optical_link/compile_hub.pl b/optical_link/compile_hub.pl index a190b52..9baf39f 100755 --- a/optical_link/compile_hub.pl +++ b/optical_link/compile_hub.pl @@ -24,7 +24,8 @@ $TOPNAME="hub"; #set -o errexit system("env| grep LM_"); -$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; +$c="/opt/Synplicity/fpga_901/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; +#$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; #$c=("( netcat -w2 -l -u -p 6001 < data_for_synbatch_6001.raw >/dev/null 2>&1)& /opt/Synplicity/fpga_89/bin/synplify_pro -batch $TOPNAME"."_syn.prj"); $r=execute($c, "do_not_exit" ); diff --git a/optical_link/flexi_PCS_channel_synch.vhd b/optical_link/flexi_PCS_channel_synch.vhd index e9827d3..32dc1b1 100644 --- a/optical_link/flexi_PCS_channel_synch.vhd +++ b/optical_link/flexi_PCS_channel_synch.vhd @@ -262,7 +262,7 @@ begin end if; end process READING_THE_FIFO; DATA_VALID_OUT <= data_valid_out_i; - fifo_rd_en <= fifo_rd_en_hub or fifo_rd_pulse; + fifo_rd_en <= (fifo_rd_en_hub and (not fifo_empty)) or fifo_rd_pulse; RXD_SYNCH <= fifo_data_out(15 downto 0); -- DATA_VALID_OUT <= fifo_data_out(16) and (not fifo_empty); VALID_DATA_SEND_TO_API: process (RX_CLK, RESET) diff --git a/optical_link/hub.lpf b/optical_link/hub.lpf index 99a8988..011b5ae 100644 --- a/optical_link/hub.lpf +++ b/optical_link/hub.lpf @@ -179,7 +179,9 @@ IOBUF PORT "DWAIT" IO_TYPE=LVTTL33 ; #LOCATE COMP "FS_PE_8" SITE "AL15" ; #LOCATE COMP "FS_PE_9" SITE "AM14" ; #LOCATE COMP "FS_PE_10" SITE "AC16" ; -#LOCATE COMP "FS_PE_11" SITE "AH16" ; + +LOCATE COMP "FS_PE_11" SITE "AH16" ; +IOBUF PORT "FS_PE_11" IO_TYPE=LVTTL33 ; #LOCATE COMP "FS_PE_12" SITE "AK15" ; #LOCATE COMP "FS_PE_13" SITE "AH14" ; #LOCATE COMP "FS_PE_14" SITE "AM13" ; diff --git a/optical_link/hub.vhd b/optical_link/hub.vhd index e7c006e..d402f74 100644 --- a/optical_link/hub.vhd +++ b/optical_link/hub.vhd @@ -349,6 +349,17 @@ architecture hub of hub is signal_in : in std_logic; pulse : out std_logic); end component; + component DCS +-- synthesis translate_off + generic ( + DCSMODE : string := "LOW_LOW"); +-- synthesis translate_on + port ( + CLK0 : in std_logic; + CLK1 : in std_logic; + SEL : in std_logic; + DCSOUT : out std_logic); + end component; ----------------------------------------------------------------------------- -- FLEXI_PCS ----------------------------------------------------------------------------- @@ -425,12 +436,21 @@ architecture hub of hub is signal word_counter_for_api_00 : std_logic_vector(1 downto 0); signal word_counter_for_api_01 : std_logic_vector(1 downto 0); signal global_reset_i : std_logic; - signal global_reset_cnt : std_logic_vector(3 downto 0); + signal global_reset_cnt : std_logic_vector(3 downto 0):=x"0"; signal registered_signals : std_logic_vector(7 downto 0); signal hub_register_0a_i_synch : std_logic_vector(7 downto 0); signal hub_register_0e_and_0d_synch : std_logic_vector(15 downto 0); signal test_signal : std_logic_vector(1 downto 0); signal pulse_test : std_logic; + signal saved_ready : std_logic_vector(HOW_MANY_CHANNELS-2 downto 0); + signal all_ready : std_logic; + signal flexi_pcs_ref_clk : std_logic; + signal lok_i : std_logic_vector(16 downto 1); + signal not_used_lok : std_logic_vector(15 downto 0); + signal used_channels_locked : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + signal channels_locked : std_logic_vector(16 downto 1); + signal switch_rx_clk : std_logic; + signal lock_pattern : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); begin GLOBAL_RESET: process(LVDS_CLK_200P,global_reset_cnt) begin @@ -461,13 +481,41 @@ begin pulse => pulse_test); test_signal(1) <= pulse_test; test_signal(0) <= pulse_test; + REF_CLK_SELECT: DCS + -- synthesis translate_off + generic map ( + DCSMODE => DCSMODE) + -- synthesis translate_on + port map ( + CLK0 => LVDS_CLK_200P, + CLK1 => '0', + SEL => switch_rx_clk,--hub_register_0a_i(0),--'0',--switch_rx_clk, + DCSOUT => flexi_pcs_ref_clk); + SWITCH_CLOCK: process (LVDS_CLK_200P, global_reset_i) + begin -- process SWITCH_CLOCK + if rising_edge(LVDS_CLK_200P) then + if global_reset_i = '1' or lock_pattern /= used_channels_locked then -- asynchronous reset (active low) + switch_rx_clk <= '0'; + lock_pattern <= (others => '1'); + elsif lock_pattern = used_channels_locked then + switch_rx_clk <= '1'; + lock_pattern <= (others => '1'); + end if; + end if; + end process SWITCH_CLOCK; + LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate + begin + used_channels_locked(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16); + end generate LOK_STATUS_DIOD_EN; + + --lock_pattern(15 downto HOW_MANY_CHANNELS) <= lok_i(16 downto HOW_MANY_CHANNELS +1); QUAD_GENERATE : for bit_index in 0 to ((HOW_MANY_CHANNELS+3)/4-1) generate begin QUAD : serdes_fpga_ref_clk port map ( -- refclkp => SERDES_200P, -- refclkn => SERDES_200N, - rxrefclk => LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P, + rxrefclk => flexi_pcs_ref_clk,--LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P, refclk => LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P, hdinp_0 => SFP_INP_P(bit_index*4+0), hdinn_0 => SFP_INP_N(bit_index*4+0), @@ -611,6 +659,8 @@ begin MED_STAT_OP => med_stat_op_i, MED_CTRL_OP => med_ctrl_op_i ); + ADO_TTL(34 downto 19) <= med_read_in_i(0) & flexi_pcs_synch_status_i(2 downto 1) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0); + ADO_TTL(15 downto 0) <= med_read_out_i(0) & flexi_pcs_synch_status_i(7 downto 6) & med_packet_num_in_i(1 downto 0) & tx_k_i(1 downto 0) & txd_synch_i(3 downto 0) & med_dataready_in_i(0) & med_data_in_i(3 downto 0); -- med_data_in_i(15 downto 0) <= hub_register_0e_and_0d; -- med_read_in_i <= (others => '1'); --test @@ -673,6 +723,7 @@ begin end if; end process; process (rx_clk_i(0), global_reset_i, rx_k_i(0)) + begin if rising_edge(rx_clk_i(0)) then if global_reset_i = '1' then -- asynchronous reset (active low) @@ -697,40 +748,42 @@ begin end if; end process; registered_signals(4 downto 3) <= rx_k_i(1) & rx_k_i(0); - TRB_HUB_INT : trb_hub_interface - port map ( - CLK => ref_pclk(0), - RESET => global_reset_i, - STROBE => ADO_TTL(9), - internal_data_in => ADO_TTL(18 downto 11), - internal_data_out => ADO_TTL(42 downto 35), - internal_address => ADO_TTL(34 downto 19), - internal_mode => ADO_TTL(10), - VALID_DATA_SENT => ADO_TTL(8), - HUB_REGISTER_00 => hub_register_00_i, - HUB_REGISTER_01 => hub_register_01_i, - HUB_REGISTER_02 => hub_register_02_i, - HUB_REGISTER_03 => hub_register_03_i, - HUB_REGISTER_04 => hub_register_04_i, - HUB_REGISTER_05 => hub_register_05_i, - HUB_REGISTER_06 => hub_register_06_i, - HUB_REGISTER_07 => hub_register_07_i, - HUB_REGISTER_08 => hub_register_08_i, - HUB_REGISTER_09 => hub_register_09_i, - HUB_REGISTER_0a => hub_register_0a_i, - HUB_REGISTER_0b => hub_register_0b_i, - HUB_REGISTER_0c => hub_register_0c_i, - HUB_REGISTER_0d => hub_register_0d_i, - HUB_REGISTER_0e => hub_register_0e_i, - HUB_REGISTER_0f => hub_register_0f_i, - HUB_REGISTER_10 => hub_register_10_i, - HUB_REGISTER_11 => hub_register_11_i, - HUB_REGISTER_12 => hub_register_12_i, - HUB_REGISTER_13 => hub_register_13_i, - HUB_REGISTER_14 => hub_register_14_i, - HUB_REGISTER_15 => hub_register_15_i, - HUB_REGISTER_16 => hub_register_16_i - ); +-- TRB_HUB_INT : trb_hub_interface +-- port map ( +-- CLK => ref_pclk(0), +-- RESET => global_reset_i, +-- STROBE => ADO_TTL(9), +-- internal_data_in => ADO_TTL(18 downto 11), +-- internal_data_out => ADO_TTL(42 downto 35), +-- internal_address => ADO_TTL(34 downto 19), +-- internal_mode => ADO_TTL(10), +-- VALID_DATA_SENT => ADO_TTL(8), +-- HUB_REGISTER_00 => hub_register_00_i, +-- HUB_REGISTER_01 => hub_register_01_i, +-- HUB_REGISTER_02 => hub_register_02_i, +-- HUB_REGISTER_03 => hub_register_03_i, +-- HUB_REGISTER_04 => hub_register_04_i, +-- HUB_REGISTER_05 => hub_register_05_i, +-- HUB_REGISTER_06 => hub_register_06_i, +-- HUB_REGISTER_07 => hub_register_07_i, +-- HUB_REGISTER_08 => hub_register_08_i, +-- HUB_REGISTER_09 => hub_register_09_i, +-- HUB_REGISTER_0a => hub_register_0a_i, +-- HUB_REGISTER_0b => hub_register_0b_i, +-- HUB_REGISTER_0c => hub_register_0c_i, +-- HUB_REGISTER_0d => hub_register_0d_i, +-- HUB_REGISTER_0e => hub_register_0e_i, +-- HUB_REGISTER_0f => hub_register_0f_i, +-- HUB_REGISTER_10 => hub_register_10_i, +-- HUB_REGISTER_11 => hub_register_11_i, +-- HUB_REGISTER_12 => hub_register_12_i, +-- HUB_REGISTER_13 => hub_register_13_i, +-- HUB_REGISTER_14 => hub_register_14_i, +-- HUB_REGISTER_15 => hub_register_15_i, +-- HUB_REGISTER_16 => hub_register_16_i +-- ); +-- ADO_TTL(34 downto 9) <= (others => 'Z'); + SYNCH_DATA: process (ref_pclk(0), global_reset_i) begin -- process SYNCH_DATA if falling_edge(ref_pclk(0)) then @@ -743,7 +796,7 @@ begin end if; end if; end process SYNCH_DATA; - ADO_TTL(34 downto 9) <= (others => 'Z'); + hub_register_00_i <= flexi_pcs_synch_status_i(7 downto 0); hub_register_01_i <= hub_stat_gen_i(15 downto 8); hub_register_02_i <= rxd_i(7 downto 0); --; --rxd_1_a(15 downto 8); @@ -816,16 +869,16 @@ begin --------------------------------------------------------------------------- LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate begin - LOK(synch_fsm_state+1) <= not flexi_pcs_synch_status_i(2+synch_fsm_state*16); + lok_i(synch_fsm_state+1) <= not flexi_pcs_synch_status_i(2+synch_fsm_state*16); end generate LOK_STATUS_DIOD_EN; LOK_STATUS_DIOD_DIS : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate begin WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate - LOK(16-not_connected) <= '1'; + lok_i(16-not_connected) <= '1'; end generate WHEN_NOT_ALL_EN; end generate LOK_STATUS_DIOD_DIS; - + LOK <= lok_i; IPLL <= '0'; OPLL <= '0'; DBAD <= ADO_TTL(11); @@ -854,9 +907,9 @@ begin end if; end process CV_COUNTERaab; RT(16 downto 8) <= cv_counter(31 downto 23); - RT(2) <= cv_counter(0); + RT(2) <= flexi_pcs_ref_clk;--cv_counter(0); - RT(1) <= ref_pclk(0); + RT(1) <= not switch_rx_clk;--ref_pclk(0); RT(3) <= LVDS_CLK_200P; diff --git a/optical_link/hub_syn.prj b/optical_link/hub_syn.prj index f60dd8e..6b9cd0c 100644 --- a/optical_link/hub_syn.prj +++ b/optical_link/hub_syn.prj @@ -5,6 +5,13 @@ #add_file options +add_file -vhdl -lib work "~/trbnet/trb_net_rom_16x8.vhd" +add_file -vhdl -lib work "~/trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "~/trbnet/trb_net_ram_dp.vhd" +add_file -vhdl -lib work "~/trbnet/trb_net_ram.vhd" +add_file -vhdl -lib work "~/trbnet/trb_net_ram_16x8_dp.vhd" +add_file -vhdl -lib work "~/trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "~/trbnet/trb_net16_hub_func.vhd" add_file -vhdl -lib work "~/trbnet/lattice/scm/lattice_scm_fifo_18x1k.vhd" add_file -vhdl -lib work "~/trbnet/lattice/scm/lattice_scm_fifo_18x16.vhd" add_file -vhdl -lib work "~/trbnet/lattice/scm/lattice_scm_fifo_18x32.vhd" @@ -31,7 +38,6 @@ add_file -vhdl -lib work "flexi_PCS_fifo_EBR.vhd" add_file -vhdl -lib work "serdes_fpga_ref_clk.vhd" add_file -vhdl -lib work "pll_ref.vhd" #add_file -vhdl -lib work "~/trbnet/xilinx/trb_net_fifo_arch.vhd" -add_file -vhdl -lib work "~/trbnet/trb_net16_base_api.vhd" add_file -vhdl -lib work "~/trbnet/trb_net_std.vhd" add_file -vhdl -lib work "~/trbnet/trb_net_fifo.vhd" add_file -vhdl -lib work "~/trbnet/trb_net16_fifo.vhd" @@ -40,15 +46,11 @@ add_file -vhdl -lib work "~/trbnet/trb_net16_iobuf.vhd" #add_file -vhdl -lib work "~/trbnet/trb_net_passive_api.vhd" add_file -vhdl -lib work "~/trbnet/xilinx/shift_lut_x16.vhd" add_file -vhdl -lib work "~/trbnet/trb_net_dummy_fifo.vhd" -add_file -vhdl -lib work "~/trbnet/trb_net_ibuf.vhd" -add_file -vhdl -lib work "~/trbnet/trb_net_io_multiplexer.vhd" -add_file -vhdl -lib work "~/trbnet/trb_net_obuf.vhd" add_file -vhdl -lib work "~/trbnet/trb_net_pattern_gen.vhd" add_file -vhdl -lib work "~/trbnet/trb_net_priority_arbiter.vhd" add_file -vhdl -lib work "~/trbnet/trb_net_priority_encoder.vhd" add_file -vhdl -lib work "~/trbnet/trb_net_sbuf.vhd" add_file -vhdl -lib work "~/trbnet/trb_net16_sbuf.vhd" -add_file -vhdl -lib work "~/trbnet/trb_net_term_ibuf.vhd" add_file -vhdl -lib work "~/trbnet/trb_net16_hub_base.vhd" add_file -vhdl -lib work "~/trbnet/trb_net16_hub_logic.vhd" add_file -vhdl -lib work "~/trbnet/trb_net16_hub_func.vhd" diff --git a/optical_link/hub_tb.vhd b/optical_link/hub_tb.vhd index 5ddb01c..1b35d87 100644 --- a/optical_link/hub_tb.vhd +++ b/optical_link/hub_tb.vhd @@ -56,9 +56,9 @@ signal SFP_OUT_P_i : std_logic_vector(15 downto 0); component hub port ( LVDS_CLK_200P : in std_logic; - LVDS_CLK_200N : in std_logic; - SERDES_200N : in std_logic; - SERDES_200P : in std_logic; +-- LVDS_CLK_200N : in std_logic; +-- SERDES_200N : in std_logic; +-- SERDES_200P : in std_logic; ADO_TTL : inout std_logic_vector(46 downto 0); DBAD : out std_logic; DGOOD : out std_logic; @@ -72,7 +72,18 @@ component hub SFP_INP_N : in std_logic_vector(15 downto 0); SFP_INP_P : in std_logic_vector(15 downto 0); SFP_OUT_N : out std_logic_vector(15 downto 0); - SFP_OUT_P : out std_logic_vector(15 downto 0)); + SFP_OUT_P : out std_logic_vector(15 downto 0); + FS_PE_11 : inout std_logic; + --------------------------------------------------------------------------- + -- sim + --------------------------------------------------------------------------- + OPT_DATA_IN : in std_logic_vector(16*HOW_MANY_CHANNELS-1 downto 0); + OPT_DATA_OUT : out std_logic_vector(16*HOW_MANY_CHANNELS-1 downto 0); + OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0) + + + ); end component; @@ -80,9 +91,6 @@ begin -- of hub_tb HUB_SIM: hub port map ( LVDS_CLK_200P => LVDS_CLK_200P_i, - LVDS_CLK_200N => LVDS_CLK_200N_i, - SERDES_200N => SERDES_200N_i, - SERDES_200P => SERDES_200P_i, ADO_TTL => ADO_TTL_i, DBAD => DBAD_i, DGOOD => DGOOD_i, @@ -96,7 +104,12 @@ begin -- of hub_tb SFP_INP_N => SFP_INP_N_i, SFP_INP_P => SFP_INP_P_i, SFP_OUT_N => SFP_OUT_N_i, - SFP_OUT_P => SFP_OUT_P_i); + SFP_OUT_P => SFP_OUT_P_i + FS_PE_11 => + OPT_DATA_IN => + OPT_DATA_OUT => + OPT_DATA_VALID_IN => + OPT_DATA_VALID_OUT => clock_gclk : process begin diff --git a/optical_link/serdes_fpga_ref_clk.txt b/optical_link/serdes_fpga_ref_clk.txt index b798524..c664b6f 100644 --- a/optical_link/serdes_fpga_ref_clk.txt +++ b/optical_link/serdes_fpga_ref_clk.txt @@ -19,18 +19,29 @@ ch3 13 03 # Powerup Channel ch3 00 00 quad 00 00 quad 01 E4 -quad 28 50 # Reference clock multiplier +quad 28 40 # Reference clock multiplier quad 29 11 # FPGA sourced refclk quad 02 00 # ref_pclk source is ch0 quad 04 00 # MCA enable 4 channels quad 18 10 # 8b10b Mode - quad 14 FF # Word Alignment Mask - quad 15 7c # +ve K - quad 16 b6 # -ve K +quad 14 FF # Word Alignment Mask +quad 15 7c # +ve K +quad 16 b6 # -ve K quad 17 36 quad 19 8C # Enable word_align_en port, FPGA bus width is 16-bit/20-bit + +#quad 1e 01 #SOP EOP only 1 word 24.04.2008 +#quad 1f ff +#quad 20 7c +#quad 21 7c +#quad 22 5 +#quad 23 7c +#quad 24 7c +#quad 25 5 + + ch0 14 90 # 16% pre-emphasis ch0 15 10 # +6dB equalization ch1 14 90 # 16% pre-emphasis diff --git a/optical_link/trb_hub_interface.vhd b/optical_link/trb_hub_interface.vhd index cf0e059..7f1d1b7 100644 --- a/optical_link/trb_hub_interface.vhd +++ b/optical_link/trb_hub_interface.vhd @@ -120,7 +120,7 @@ begin when x"000c" => saved_data_out <= hub_register_0c_i; when x"000d" => saved_data_out <= hub_register_0d_i; when x"000e" => saved_data_out <= hub_register_0e_i; - when x"000f" => saved_data_out <= HUB_REGISTER_0f; + when x"000f" => saved_data_out <= hub_register_0f_i; when x"0010" => saved_data_out <= HUB_REGISTER_10; when x"0011" => saved_data_out <= HUB_REGISTER_11; when x"0012" => saved_data_out <= HUB_REGISTER_12; @@ -137,7 +137,8 @@ begin when x"000b" => hub_register_0b_i <= saved_data_in; when x"000c" => hub_register_0c_i <= saved_data_in; when x"000d" => hub_register_0d_i <= saved_data_in; - when x"000e" => hub_register_0e_i <= saved_data_in; + when x"000e" => hub_register_0e_i <= saved_data_in; + when x"000f" => hub_register_0f_i <= saved_data_in; when others => null; end case; end if; @@ -149,6 +150,7 @@ begin HUB_REGISTER_0c <= hub_register_0c_i; HUB_REGISTER_0d <= hub_register_0d_i; HUB_REGISTER_0e <= hub_register_0e_i; + HUB_REGISTER_0f <= hub_register_0f_i; INTERNAL_DATA_OUT <= saved_data_out; data_ready <= '1'; VALID_CLOCKED : process (CLK, RESET)