From: a.weber Date: Tue, 7 Aug 2018 19:06:10 +0000 (+0200) Subject: working fifo; missing HubAddress in Data -AW X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c9027a4a3283ae3c57e55ba8f546b3058921be34;p=dirich.git working fifo; missing HubAddress in Data -AW --- diff --git a/combiner_calib/combiner.lpf b/combiner_calib/combiner.lpf index 921a7a0..6d5a39d 100644 --- a/combiner_calib/combiner.lpf +++ b/combiner_calib/combiner.lpf @@ -19,10 +19,10 @@ LOCATE COMP "THE_MEDIA_4_DOWN_A/THE_SERDES/PCSD_INST" SITE "PCSA" ; LOCATE COMP "THE_MEDIA_4_DOWN_B/THE_SERDES/PCSD_INST" SITE "PCSB" ; LOCATE COMP "THE_MEDIA_4_DOWN_D/THE_SERDES/PCSD_INST" SITE "PCSD" ; -REGION "MEDIA_A" "R87C91D" 28 36; -REGION "MEDIA_B" "R87C55D" 28 36; -REGION "MEDIA_C" "R87C127D" 28 36; -REGION "MEDIA_D" "R87C19D" 28 36; +REGION "MEDIA_A" "R80C91D" 35 36; +REGION "MEDIA_B" "R80C55D" 35 36; +REGION "MEDIA_C" "R80C127D" 35 36; +REGION "MEDIA_D" "R80C19D" 35 36; #REGION "MEDIA_DOWN1" "R93C10D" 22 160; diff --git a/combiner_calib/combiner.vhd b/combiner_calib/combiner.vhd index 8f2b68c..315e32d 100644 --- a/combiner_calib/combiner.vhd +++ b/combiner_calib/combiner.vhd @@ -112,8 +112,8 @@ architecture arch of combiner is signal int2med : int2med_array_t(0 to INTERFACE_NUM-1); signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX; - signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx , busdebug_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx : CTRLBUS_TX; signal bussci_tx : ctrlbus_tx_array_t(0 to 3); signal bussci_rx : ctrlbus_rx_array_t(0 to 3); @@ -197,6 +197,19 @@ architecture arch of combiner is signal fifo_rdEn_r, fifo_rdEn_2r, fifo_rdEn_3r : std_logic; signal fifo_data_out : std_logic_vector(35 downto 0); + signal FSM_state_RX : std_logic_vector(31 downto 0); + signal FSM_state_TX : std_logic_vector(31 downto 0); + signal WCNT_i : std_logic_vector(15 downto 0); + + signal DEBUG_fifo_rdEn : unsigned(31 downto 0); + signal DEBUG_cts_read : unsigned(31 downto 0); + signal DEBUG_enable_fifo_rdEn : std_logic; + signal DEBUG_cts_dataready : std_logic := '0'; + signal DEBUG_EvtLength : unsigned(15 downto 0); + + signal already_asked : std_logic := '0'; + signal rd_enabled : std_logic := '0'; + component FIFO_36x64 is port ( Data: in std_logic_vector(35 downto 0); @@ -611,127 +624,141 @@ back_slave_ready_i <= BACK_SLAVE_READY; wait until rising_edge(clk_sys); pckr_Data_ready <= '0'; + fee_read <= '1'; if reset_i = '1' then pckr_RX_state <= IDLE; else case pckr_RX_state is - when IDLE => - if cts_start_readout = '1' then - pckr_RX_state <= WAITING; - EvInf_data <= (others => '0'); - end if; - - when WAITING => - if fee_busy = '1' then - pckr_RX_state <= EVINF_H; - end if; - - when EVINF_H => - if (fee_dataready and fee_read) = '1' then - EvInf_data(31 downto 16) <= fee_data; --not necessry - pckr_Data(31 downto 16) <= fee_data; - pckr_RX_state <= EVINF_L; - end if; - - when EVINF_L => - if (fee_dataready and fee_read) = '1' then - EvInf_data(15 downto 0) <= fee_data; --not necessry - pckr_Data(15 downto 0) <= fee_data; - pckr_Data_type <= x"1"; - pckr_Data_ready <= '1'; - pckr_RX_state <= LENGTH; - end if; - - when LENGTH => - if (fee_dataready and fee_read) = '1' then - pckr_Data(31 downto 16) <= fee_data; - pckr_Data_Length_Ev <= fee_data; --for CTS - pckr_Data_Length_Ev_cntr := unsigned(fee_data); - pckr_RX_state <= SOURCE; - end if; - - when SOURCE => - if (fee_dataready and fee_read) = '1' then - pckr_Data_Source <= fee_data; --not necessary - pckr_Data(15 downto 0) <= fee_data; - pckr_Data_type <= x"2"; - pckr_Data_ready <= '1'; - pckr_RX_state <= SSE_LENGTH; - end if; - - when SSE_LENGTH => - if (fee_dataready and fee_read) = '1' then - pckr_Data(31 downto 16) <= fee_data; - --see_length <= fee_data; - sse_length_cntr := unsigned(fee_data); - pckr_RX_state <= SSE_FEE_ID; - end if; - - when SSE_FEE_ID => --Analysing Data - if (fee_dataready and fee_read) = '1' then - pckr_Data(15 downto 0) <= fee_data; - pckr_Data_type <= x"3"; --SSE_HDR - pckr_Data_ready <= '1'; - sse_fee_addr <= fee_data; - pckr_RX_state <= SSE_DATA_H; - - pckr_Data_Length_Ev_cntr := pckr_Data_Length_Ev_cntr - 1; - if sse_length_cntr = x"0000" then - pckr_RX_state <= SSE_LENGTH; - end if; - end if; - - when SSE_DATA_H => - if (fee_dataready and fee_read) = '1' then - pckr_Data(31 downto 16) <= fee_data; - pckr_RX_state <= SSE_DATA_L; - end if; - - when SSE_DATA_L => --Analysing Data - if (fee_dataready and fee_read) = '1' then - pckr_Data(15 downto 0) <= fee_data; - pckr_Data_type <= x"4"; --SSE_DATA - pckr_Data_ready <= '1'; - sse_length_cntr := sse_length_cntr - 1; - pckr_Data_Length_Ev_cntr := pckr_Data_Length_Ev_cntr - 1; - - -- data handling - if sse_length_cntr = x"0000" then - if pckr_Data_Length_Ev_cntr = x"0000" then - pckr_RX_state <= STAT_BITS; - else - pckr_RX_state <= SSE_LENGTH; - end if; - else - --if pckr_Data_Length_Ev_cntr = x"0000" then - -- Problem ?!? - --else - pckr_RX_state <= SSE_DATA_H; - --end if; - end if; - end if; - - when STAT_BITS => --Analysing Data - if (fee_busy) = '0' then - EvStatBits <= fee_status_bits; - pckr_RX_state <= IDLE; - end if; - - when others => - null; + when IDLE => + if cts_start_readout = '1' then + pckr_RX_state <= WAITING; + EvInf_data <= (others => '0'); + end if; + FSM_state_RX <= x"00000001"; + + when WAITING => + if fee_busy = '1' then + pckr_RX_state <= EVINF_H; + end if; + FSM_state_RX <= x"00000002"; + + when EVINF_H => + if (fee_dataready and fee_read) = '1' then + EvInf_data(31 downto 16) <= fee_data; --not necessry + pckr_Data(31 downto 16) <= fee_data; + pckr_RX_state <= EVINF_L; + end if; + FSM_state_RX <= x"00000003"; + + when EVINF_L => --triggerNMBR + if (fee_dataready and fee_read) = '1' then + EvInf_data(15 downto 0) <= fee_data; --not necessry + pckr_Data(15 downto 0) <= fee_data; + pckr_Data_type <= x"1"; + pckr_Data_ready <= '1'; + pckr_RX_state <= LENGTH; + end if; + FSM_state_RX <= x"00000004"; + + when LENGTH => + if (fee_dataready and fee_read) = '1' then + pckr_Data(31 downto 16) <= fee_data; + pckr_Data_Length_Ev <= fee_data; --for CTS + pckr_Data_Length_Ev_cntr := unsigned(fee_data); + pckr_RX_state <= SOURCE; + end if; + FSM_state_RX <= x"00000005"; + + when SOURCE => + if (fee_dataready and fee_read) = '1' then + pckr_Data_Source <= fee_data; --not necessary + pckr_Data(15 downto 0) <= fee_data; + pckr_Data_type <= x"2"; + pckr_Data_ready <= '1'; + pckr_RX_state <= SSE_DATA_H;--SSE_LENGTH; CHANGED FOR PACKING MODE + end if; + FSM_state_RX <= x"00000006"; + + when SSE_LENGTH => + if (fee_dataready and fee_read) = '1' then + pckr_Data(31 downto 16) <= fee_data; + --see_length <= fee_data; + sse_length_cntr := unsigned(fee_data); + pckr_RX_state <= SSE_FEE_ID; + end if; + FSM_state_RX <= x"00000007"; + + when SSE_FEE_ID => --Analysing Data + if (fee_dataready and fee_read) = '1' then + pckr_Data(15 downto 0) <= fee_data; + pckr_Data_type <= x"3"; --SSE_HDR + pckr_Data_ready <= '1'; + sse_fee_addr <= fee_data; + pckr_RX_state <= SSE_DATA_H; + + pckr_Data_Length_Ev_cntr := pckr_Data_Length_Ev_cntr - 1; + -- if sse_length_cntr = x"0000" then + -- pckr_RX_state <= SSE_LENGTH; + -- end if; + end if; + FSM_state_RX <= x"00000008"; + + when SSE_DATA_H => + if (fee_dataready and fee_read) = '1' then + pckr_Data(31 downto 16) <= fee_data; + pckr_RX_state <= SSE_DATA_L; + end if; + FSM_state_RX <= x"00000009"; + + when SSE_DATA_L => --Analysing Data + if (fee_dataready and fee_read) = '1' then + pckr_Data(15 downto 0) <= fee_data; + pckr_Data_type <= x"4"; --SSE_DATA + pckr_Data_ready <= '1'; + --sse_length_cntr := sse_length_cntr - 1; + pckr_Data_Length_Ev_cntr := pckr_Data_Length_Ev_cntr - 1; + + -- data handling + --------------------------- NON PACKING -------------- + -- if sse_length_cntr = x"0000" then + -- if pckr_Data_Length_Ev_cntr = x"0000" then + -- pckr_RX_state <= STAT_BITS; + -- else + -- pckr_RX_state <= SSE_LENGTH; + -- end if; + -- else + -- pckr_RX_state <= SSE_DATA_H; + -- end if; + + + if pckr_Data_Length_Ev_cntr = x"0000" then + pckr_RX_state <= STAT_BITS; + else + pckr_RX_state <= SSE_DATA_H; + end if; + + end if; + FSM_state_RX <= x"0000000A"; + + when STAT_BITS => --Analysing Data + if (fee_busy) = '0' then + EvStatBits <= fee_status_bits; + pckr_RX_state <= IDLE; + end if; + FSM_state_RX <= x"0000000B"; + + when others => + FSM_state_RX <= x"00000000"; + end case; end if; end process; - - --pckr_TX_data <= pckr_Data when rising_edge(clk_sys); - --pckr_TX_data_ready <= pckr_Data_ready_r when rising_edge(clk_sys); - -- pckr_TX_data_type <= pckr_Data_type when rising_edge(clk_sys); - --fifo_rdEn_r <= fifo_rdEn when rising_edge(clk_sys); - THE_DATAPACKER_FSM_TX : process --data buffer is necessary + + THE_DATAPACKER_FSM_TX : process --data buffer is necessary variable EvInf_TX : std_logic_vector(31 downto 0); variable EvLength_TX : std_logic_vector(15 downto 0); variable EvLength_TX_cntr : unsigned(15 downto 0); @@ -745,115 +772,109 @@ back_slave_ready_i <= BACK_SLAVE_READY; variable buf_fifo_cnt : std_logic_vector( 1 downto 0) := "00"; variable enable_fifo_rdEn : std_logic; variable pckr_TX_data_ready : std_logic; + variable dataready : std_logic; begin wait until rising_edge(clk_sys); - cts_dataready <= '0'; + cts_finished <= '0'; fifo_rdEn <= '0'; fifo_rdEn_r <= fifo_rdEn; - fifo_rdEn_2r <= fifo_rdEn_r; - fifo_rdEn_3r <= fifo_rdEn_2r; - pckr_TX_data_ready := fifo_rdEn_3r; - Data_Fifo := fifo_data_out; - enable_fifo_rdEn := '1'; + fifo_rdEn_2r <= fifo_rdEn_r; --2r is readySignal + dataready := '0'; - if reset_i='1' then - pckr_TX_state <= EVNT; - -- ToDo + if reset_i = '1' then + pckr_TX_state <= EVNT; + already_asked <= '0'; else - --BEGIN OF FIFO MANAGEMENT - if (cts_read = '0') then - case buf_fifo_cnt is - when "00" => buf_fifo_0 := fifo_data_out(35 downto 0); - buf_fifo_cnt := "01"; - - when "01" => buf_fifo_1 := fifo_data_out(35 downto 0); - buf_fifo_cnt := "10"; - - when "10" => buf_fifo_2 := fifo_data_out(35 downto 0); - buf_fifo_cnt := "11"; - - when "11" => null; - end case; - else - if buf_fifo_cnt /= "00" then - pckr_TX_data := buf_fifo_0(31 downto 0); - pckr_TX_data_type := buf_fifo_0(35 downto 32); - buf_fifo_0 := buf_fifo_1; - buf_fifo_1 := buf_fifo_2; - buf_fifo_cnt := std_logic_vector(unsigned(buf_fifo_cnt) - 1); - else -- buffer empty - pckr_TX_data := fifo_data_out(31 downto 0); - pckr_TX_data_type := fifo_data_out(35 downto 32); - end if; - end if; - if buf_fifo_cnt = "11" then - enable_fifo_rdEn := '0'; + if already_asked = '0' then + if cts_dataready = '0' then + already_asked <= '1'; + rd_enabled <= '0'; end if; - --END OF FIFO MANAGEMENT + end if; - if (pckr_TX_data_ready = '1') and (pckr_TX_data_type = x"1") then - EvInf_TX := pckr_TX_data; - end if; - - if (pckr_TX_data_ready = '1') and (pckr_TX_data_type = x"2") then - EvLength_TX := pckr_TX_data(31 downto 16); - EvLength_TX_cntr := pckr_TX_data(31 downto 16); - Header_ready := '1'; + if already_asked = '1' then + if pckr_fifo_empty = '0' and rd_enabled = '0' then + fifo_rdEn <= '1'; + rd_enabled <= '1'; end if; - + if fifo_rdEn_2r = '1' then + dataready := '1'; + already_asked <= '0'; + pckr_TX_data := fifo_data_out(31 downto 0); + pckr_TX_data_type := fifo_data_out(35 downto 32); + end if; + end if; + case pckr_TX_state is when EVNT => + if cts_start_readout = '1' then - cts_data <= EvInf_TX; - cts_length <= EvLength_TX; + if dataready = '1' then + if pckr_TX_data_type = x"1" then + --EvInf_TX := pckr_TX_data; + cts_data <= pckr_TX_data; + end if; --maybe a flag that x"1" is set before x"2" comes? + + if pckr_TX_data_type = x"2" then + cts_length <= pckr_TX_data(31 downto 16); + EvLength_TX_cntr := pckr_TX_data(31 downto 16); + Header_ready := '1'; + end if; + end if; + --cts_data <= EvInf_TX; + --cts_length <= EvLength_TX; if Header_ready = '1' then cts_dataready <= '1'; - if cts_read = '1' then + if cts_read = '1' and cts_dataready = '1' then pckr_TX_state <= DATA; + cts_dataready <= '0'; + Header_ready := '0'; end if; - else - cts_dataready <= '0'; end if; - if (pckr_fifo_empty = '0' and cts_read = '1' and enable_fifo_rdEn = '1') then --could be optimised with deleting cts_read - fifo_rdEn <= '1'; - end if; - --EvInf_data <= (others => '0'); - --Header_ready := '0'; + FSM_state_TX <= x"00000001"; + end if; when DATA => - if pckr_TX_data_type = x"3" then - cts_data <= pckr_TX_data; - cts_dataready <= '1'; - if cts_read = '1' then + + if pckr_TX_data_type = x"3" or pckr_TX_data_type = x"4" then + if dataready = '1' then + cts_data <= pckr_TX_data; + cts_dataready <= '1'; + end if; + + if cts_read = '1' and cts_dataready = '1' then EvLength_TX_cntr := EvLength_TX_cntr - 1; - - if enable_fifo_rdEn = '1' then - fifo_rdEn <= '1'; - end if; - + cts_dataready <= '0'; end if; - if EvLength_TX_cntr = x"0000" then + if EvLength_TX_cntr = 0 then pckr_TX_state <= FINISH; + cts_dataready <= '0'; end if; end if; + DEBUG_EvtLength <= EvLength_TX_cntr; + FSM_state_TX <= x"00000002"; when FINISH => cts_finished <= '1'; pckr_TX_state <= EVNT; + FSM_state_TX <= x"00000003"; when others => - null; + FSM_state_TX <= x"00000004"; end case; + + + DEBUG_enable_fifo_rdEn <= enable_fifo_rdEn; + end if; end process; - THE_FIFO_36x64 : fifo_36x32k_oreg port map ( @@ -863,9 +884,9 @@ back_slave_ready_i <= BACK_SLAVE_READY; WrEn => pckr_Data_ready, RdEn => fifo_rdEn, Reset => reset_i, - AmFullThresh(14 downto 0)=> b"111111111111111", + AmFullThresh(14 downto 0)=> b"011111111111111", Q => fifo_data_out, - WCNT(15 downto 0) => open, + WCNT(15 downto 0) => WCNT_i, Empty => pckr_fifo_empty, Full => pckr_fifo_full, AlmostFull => open); @@ -892,9 +913,9 @@ back_slave_ready_i <= BACK_SLAVE_READY; --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 6, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, others => 0), + PORT_NUMBER => 7, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", 6 => x"e000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9 , 6 => 12 , others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -910,15 +931,87 @@ back_slave_ready_i <= BACK_SLAVE_READY; BUS_RX(3) => bussci_rx(1), BUS_RX(4) => bussci_rx(2), BUS_RX(5) => bussci_rx(3), + BUS_RX(6) => busdebug_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bustc_tx, BUS_TX(2) => bussci_tx(0), BUS_TX(3) => bussci_tx(1), BUS_TX(4) => bussci_tx(2), BUS_TX(5) => bussci_tx(3), + BUS_TX(6) => busdebug_tx, STAT_DEBUG => open ); + THE_DEBUG : process begin + wait until rising_edge(clk_sys); + busdebug_tx.ack <= '0'; + busdebug_tx.nack <= '0'; + busdebug_tx.unknown <= '0'; + + if busdebug_rx.read = '1' then + if busdebug_rx.addr(7 downto 0) = x"00" then + busdebug_tx.data <= FSM_state_RX; + end if; + if busdebug_rx.addr(7 downto 0) = x"01" then + busdebug_tx.data <= FSM_state_TX; + end if; + if busdebug_rx.addr(7 downto 0) = x"02" then + busdebug_tx.data(0) <= pckr_fifo_empty; + busdebug_tx.data(3 downto 1) <= (others => '0'); + busdebug_tx.data(4) <= pckr_fifo_full; + busdebug_tx.data(15 downto 5) <= (others => '0'); + busdebug_tx.data(31 downto 16) <= WCNT_i; + end if; + if busdebug_rx.addr(7 downto 0) = x"03" then + busdebug_tx.data <= fifo_data_out(31 DOWNTO 0); + end if; + if busdebug_rx.addr( 7 downto 0) = x"04" then + busdebug_tx.data(0) <= fee_dataready; + busdebug_tx.data( 3 downto 1) <= (others => '0'); + busdebug_tx.data(4) <= fee_read; + busdebug_tx.data( 7 downto 5) <= (others => '0'); + busdebug_tx.data(8) <= fee_busy; + busdebug_tx.data(11 downto 9) <= (others => '0'); + busdebug_tx.data(12) <= cts_start_readout; + busdebug_tx.data(15 downto 13) <= (others => '0'); + busdebug_tx.data(31 downto 16) <= fee_data; + end if; + if busdebug_rx.addr( 7 downto 0) = x"05" then + busdebug_tx.data <= pckr_Data; + end if; + if busdebug_rx.addr( 7 downto 0) = x"06" then + busdebug_tx.data( 3 downto 0) <= pckr_Data_type; + busdebug_tx.data(31 downto 4) <= (others => '0'); + end if; + if busdebug_rx.addr( 7 downto 0) = x"07" then + busdebug_tx.data(15 downto 0) <= std_logic_vector(DEBUG_EvtLength); + busdebug_tx.data(31 downto 16) <= (others => '0'); + end if; + if busdebug_rx.addr( 7 downto 0) = x"08" then + busdebug_tx.data <= std_logic_vector(DEBUG_cts_read); + end if; + if busdebug_rx.addr( 7 downto 0) = x"09" then + busdebug_tx.data(0) <= DEBUG_enable_fifo_rdEn; + busdebug_tx.data(1) <= DEBUG_cts_dataready; + busdebug_tx.data(31 downto 2) <= (others => '0'); + end if; + if busdebug_rx.addr( 7 downto 0) = x"0A" then + busdebug_tx.data(15 downto 0) <= pckr_Data_Length_Ev; + busdebug_tx.data(31 downto 16) <= (others => '0'); + end if; + if busdebug_rx.addr( 7 downto 0) = x"0B" then + busdebug_tx.data(15 downto 0) <= pckr_Data_Source; + busdebug_tx.data(31 downto 16) <= (others => '0'); + end if; + + + busdebug_tx.ack <= '1'; + elsif busdebug_rx.write = '1' then + --additional_reg_i <= busdebug_rx.data(additional_reg_i'left downto 0); + busdebug_tx.ack <= '1'; + end if; + end process; + handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out; ---------------------------------------------------------------------------