From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Fri, 26 Apr 2013 12:50:27 +0000 (+0200)
Subject: Added table for RJ45 pin layout
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c91b42eed98e7054bb14d773a762c9d9e3779b65;p=daqdocu.git

Added table for RJ45 pin layout
---

diff --git a/trb3/CtsHowtos.tex b/trb3/CtsHowtos.tex
index 8ad0379..946f800 100644
--- a/trb3/CtsHowtos.tex
+++ b/trb3/CtsHowtos.tex
@@ -13,22 +13,65 @@
    prevent that you break the existing master branch code. If you have
    successfully tested everything, the changes can easily be merged.
 
+
+
 \subsubsection{The module's interface}
 %\label{sec:cts_howto_etm_instantiation}
-   An External Trigger Module (ETM) gives you the means to implement a high-level trigger criterion that does not require the
-   preprocessing of the general purpose trigger inputs. A typical example is a network bridge. A CTS build can include at
-   most one ETM. The module is directly connected to the trigger channel with the highest priority, thus if the ETM asserts
-   the trigger line while the CTS is idle, the TrbNet Event Type of the next event is defined by the type configured for the ETM.
-
-   Listing \ref{lst:cts_howto_etm_instantiation} shows a minimal ETM
-   instantiation. For a better readability, it is highly recommended,
-   that you keep the port's naming. Copy this into the top entity
-   (\files{trb3\_central.vhd}) and wrap it with an analogous
-   \verb!generate if! statement. Also add another config option in
-   \files{config.vhd}. You probably need to add signals, e.g. to
-   interface with off-board electronics, but you can some inspiration
-   two existing modules. The semantics of the CTS interface are very
-   straight-forward:
+An External Trigger Module (ETM) gives you the means to implement a
+high-level trigger criterion that does not require the preprocessing
+of the general purpose trigger inputs. A typical example is a network
+bridge. A CTS build can include at most one ETM. The module is
+directly connected to the trigger channel with the highest priority,
+thus if the ETM asserts the trigger line while the CTS is idle, the
+TrbNet Event Type of the next event is defined by the type configured
+for the ETM.
+
+% OLD STUFF FROM JAN MICHEL:
+% Signal        FPGA Pin (Diff-Typ A)    Anschluss
+% Input0 (u. MBS)    U9            RJ45(EXT_CLK) Pins 4,5
+% Input1        Y34            RJ45(EXT_CLK) Pins 7,8
+% Input2         W2            RJ45(TR_INP) Pins 3,6
+% Input3        W4            RJ45(TR_INP) Pins 7,8
+
+% TimeRefOut1    W8            RJ45(TR_INP) Pins 4,5
+% TimeRefOut2    V7            On-board Trigger Fan
+\begin{table}
+  \begin{center}
+    \begin{tabularx}{\textwidth}{lllllX} \hline
+      Signal      & FPGA Loc & RJ45 Socket      & RJ45 Pin & RJ45 Cable\\
+      \hline\hline    
+      CLK\_EXT(3) & U9 (P)   & EXTERNAL\_CLOCK1 & 4        & blue      \\
+                  & U8 (N)   & EXTERNAL\_CLOCK1 & 5        & white/blue\\
+      CLK\_EXT(4) & Y34 (P)  & EXTERNAL\_CLOCK1 & 7        & white/brown\\
+                  & Y33 (N)  & EXTERNAL\_CLOCK1 & 8        & brown\\ \hline  
+      TRIGGER\_EXT(2) & W2 (P) & TRIGGER\_INP1   & 3        & white/green\\
+                      & W1 (N) & TRIGGER\_INP1   & 6        & green\\    
+      TRIGGER\_EXT(3) & W4 (P) & TRIGGER\_INP1   & 7        & white/brown\\
+                      & W3 (N) & TRIGGER\_INP1   & 8        & brown\\    
+      TRIGGER\_OUT2   & W8 (P) & TRIGGER\_INP1   & 4        & blue\\
+                      & W9 (N) & TRIGGER\_INP1   & 5        & white/blue\\
+      \hline
+    \end{tabularx}
+    \caption[RJ45 Connections of the Central FPGA]{All signals are
+      LVDS, hence P/N pins. The column signal refers to the name in
+      \files{trb3/cts/trb3\_central.vhd}. The color coding standard of
+      the RJ45 cable is T568B. The parenthesis in column denote the
+      index of a std\_logic\_vector signal.}
+    \label{tab:trb3_central_rj45_connections}
+  \end{center}
+\end{table}
+
+
+
+Listing \ref{lst:cts_howto_etm_instantiation} shows a minimal ETM
+instantiation. For a better readability, it is highly recommended,
+that you keep the port's naming. Copy this into the top entity
+(\files{trb3\_central.vhd}) and wrap it with an analogous
+\verb!generate if! statement. Also add another config option in
+\files{config.vhd}. You probably need to add signals, e.g. to
+interface with off-board electronics, see table~\ref{tab:trb3_central_rj45_connections}. you can get some inspiration
+from the two existing modules. The semantics of the CTS interface are
+very straight-forward:
 
    \begin{itemize*}
       \item Synchronously assert the \signal{cts\_ext\_trigger} line to indicate an event. If the CTS is idle (as indicated by a
diff --git a/trb3/main.pdf b/trb3/main.pdf
index 7763dca..eb0e909 100644
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