From: Thomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Date: Wed, 30 Sep 2020 13:17:13 +0000 (+0200)
Subject: med_sync_control: Fix signal_sync source clocks
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c96a0e0116b435acecd93661eaadda13f984d807;p=trbnet.git

med_sync_control: Fix signal_sync source clocks

The signal_sync instances for the finished_reset_* signals from
tx_reset_fsm and rx_reset_fsm had the source clock set to CLK_SYS, but
both source signals are synchronous to CLK_REF.
---

diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd
index a692953..aded4e7 100644
--- a/media_interfaces/sync/med_sync_control.vhd
+++ b/media_interfaces/sync/med_sync_control.vhd
@@ -230,10 +230,10 @@ PROC_ALLOW : process begin
   end if;
 end process;
 
-LINK_RESET_FIN_TX  : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS,
+LINK_RESET_FIN_TX  : signal_sync port map(RESET => '0',CLK0 => CLK_REF, CLK1 => CLK_SYS,
                                           D_IN(0)  => finished_reset_tx, 
                                           D_OUT(0) => finished_reset_tx_q);
-LINK_RESET_FIN_RX  : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS,
+LINK_RESET_FIN_RX  : signal_sync port map(RESET => '0',CLK0 => CLK_REF, CLK1 => CLK_SYS,
                                           D_IN(0)  => finished_reset_rx, 
                                           D_OUT(0) => finished_reset_rx_q);