From: hadaq <hadaq>
Date: Wed, 26 Jan 2011 13:57:50 +0000 (+0000)
Subject: update
X-Git-Tag: v6.0~166
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c9c05dd8fdafadbb53f682c03622a17f790c33e1;p=trbnettools.git

update
---

diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c
index 048ab00..54fdcce 100644
--- a/libtrbnet/trbnet.c
+++ b/libtrbnet/trbnet.c
@@ -1,4 +1,4 @@
-const char trbnet_version[] = "$Revision: 4.0 $";
+const char trbnet_version[] = "$Revision: 4.1 $";
 
 #include <stdlib.h>
 #include <signal.h>
@@ -467,11 +467,13 @@ static int trb_init_transfer(uint8_t channel)
   }
   
   /* Check for TX not Busy */
+#ifndef PEXOR
   read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp);
   if (tmp != 0) {
     /* FIFO_TOGGLE_BIT-BUG Workaround */
     com_reset_FPGA();
   }
+#endif
   read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp);
   if (tmp != 0) {
     trb_errno = TRB_TX_BUSY;
@@ -479,12 +481,14 @@ static int trb_init_transfer(uint8_t channel)
   }
   
   /* Check receiver FIFO empty */
+#ifndef PEXOR
   read32_from_FPGA(CHANNEL_N_RECEIVER_FIFO_STATUS | ((channel * 2 + 1) << 4), 
                    &tmp);
   if ((tmp & MASK_FIFO_EMPTY) == 0) {
     /* FIFO_TOGGLE_BIT-BUG Workaround */
     com_reset_FPGA();
   }
+#endif
   read32_from_FPGA(CHANNEL_N_RECEIVER_FIFO_STATUS | ((channel * 2 + 1) << 4), 
                    &tmp);
   if ((tmp & MASK_FIFO_EMPTY) == 0) {
@@ -662,7 +666,8 @@ static int trb_fifo_read(uint8_t channel,
           trb_errno = TRB_FIFO_INVALID_HEADER;
           return -1;
         }
-      
+        
+#ifndef PEXOR
         /* Check Header H0 */
         if (((package.H0 & MASK_HEADER_REPLY) >> SHIFT_HEADER_REPLY
              != 0x01) ||
@@ -674,6 +679,7 @@ static int trb_fifo_read(uint8_t channel,
           trb_errno = TRB_FIFO_HEADERS;
           return -1;
         }
+#endif
       }
 
       /* Get Data F0 - F3 and store it in User-Data-Buffer if requested */