From: palka Date: Fri, 22 Feb 2008 09:45:14 +0000 (+0000) Subject: cleaning, shrinking etc. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c9e7f52803684ee2f35e74d3a8d03a7c9a2f79b2;p=trbv2.git cleaning, shrinking etc. --- diff --git a/trb_v2b_fpga.vhd b/trb_v2b_fpga.vhd index d8ca781..a6f3272 100644 --- a/trb_v2b_fpga.vhd +++ b/trb_v2b_fpga.vhd @@ -429,7 +429,7 @@ architecture trb_v2b_fpga of trb_v2b_fpga is FPGA_REGISTER_0B : in std_logic_vector(31 downto 0); FPGA_REGISTER_0C : in std_logic_vector(31 downto 0); FPGA_REGISTER_0D : in std_logic_vector(31 downto 0); - FPGA_REGISTER_0E : in std_logic_vector(31 downto 0); + FPGA_REGISTER_0E : out std_logic_vector(31 downto 0); EXTERNAL_RESET : out std_logic; LVL2_VALID : in std_logic ); @@ -645,10 +645,8 @@ architecture trb_v2b_fpga of trb_v2b_fpga is signal fpga_register_0c_i : std_logic_vector(31 downto 0); signal fpga_register_0d_i : std_logic_vector(31 downto 0); signal fpga_register_0e_i : std_logic_vector(31 downto 0); - signal fpga_register_19_i : std_logic_vector(31 downto 0); signal fpga_register_20_i : std_logic_vector(31 downto 0); - signal fpga_register_22_i : std_logic_vector(31 downto 0); signal fpga_register_23_i : std_logic_vector(31 downto 0); signal fpga_register_24_i : std_logic_vector(31 downto 0):=x"00000000"; @@ -670,8 +668,6 @@ architecture trb_v2b_fpga of trb_v2b_fpga is signal tdc_register_03_i : std_logic_vector(31 downto 0); signal tdc_register_04_i : std_logic_vector(31 downto 0); signal tdc_register_05_i : std_logic_vector(31 downto 0); - - signal tdc_control_register_e : std_logic_vector(31 downto 0); signal simulation_00 : std_logic_vector(3 downto 0); signal bunch_reset_i : std_logic; @@ -717,14 +713,8 @@ architecture trb_v2b_fpga of trb_v2b_fpga is signal sdram_address_i : std_logic_vector(31 downto 0); signal etrax_register_00_i : std_logic_vector(31 downto 0); signal lvl1_triggers : std_logic_vector(7 downto 0); - signal scaler_counter_0 : std_logic_vector(31 downto 0); - signal scaler_counter_1 : std_logic_vector(31 downto 0); - signal scaler_counter_2 : std_logic_vector(31 downto 0); - signal scaler_counter_3 : std_logic_vector(31 downto 0); - signal scaler_counter_4 : std_logic_vector(31 downto 0); - signal scaler_counter_5 : std_logic_vector(31 downto 0); - signal scaler_counter_6 : std_logic_vector(31 downto 0); - signal scaler_counter_7 : std_logic_vector(31 downto 0); + type scaler_counter_arr is array(0 to 7) of std_logic_vector(31 downto 0); + signal scaler_counter : scaler_counter_arr; signal scaler_pulse : std_logic_vector(7 downto 0); signal lvl1_ctu_status_i : std_logic_vector(31 downto 0); signal lvl2_ctu_status_i : std_logic_vector(31 downto 0); @@ -735,8 +725,8 @@ architecture trb_v2b_fpga of trb_v2b_fpga is signal self_data_valid : std_logic; signal external_reset : std_logic; signal generator_trigger_1 : std_logic; - signal generator_trigger_2 : std_logic; - signal generator_trigger : std_logic; + signal generator_trigger_2 : std_logic; + signal generator_trigger : std_logic; signal check_pulse : std_logic; signal check_counter : std_logic_vector(16 downto 0); --api @@ -818,717 +808,166 @@ architecture trb_v2b_fpga of trb_v2b_fpga is signal fs_pc17 : std_logic; signal med_packet_num_in_i : std_logic_vector(1 downto 0); begin - ------------------------------------------------------------------------------ - -- LVDS signals - ------------------------------------------------------------------------------ - -- CLK - IBUFGDS_CLK : IBUFGDS +------------------------------------------------------------------------------ +-- LVDS signals +------------------------------------------------------------------------------ + -- CLK ---------------------------------------------------------------------- + IBUFGDS_CLK : IBUFGDS + generic map ( + IOSTANDARD => "LVDS_25_DCI") + port map ( + O => CLK,--CLK, + I => VIRT_CLK, + IB => VIRT_CLKB -- Diff_n clock buffer input (connect to top-level port) + ); + -- TDC ---------------------------------------------------------------------- + IBUFGDS_TDC_CLK : IBUFGDS + generic map ( + IOSTANDARD => "LVDS_25_DCI") --_DCI + port map ( + O => tdc_clk, + I => REF_TDC_CLK, + IB => REF_TDC_CLKB-- Diff_n clock buffer input (connect to top-level port) + ); + IBUFDS_TRIGG_A : OBUFDS port map (O => A_TRIGGER, OB => A_TRIGGERB, I => a_trigg); + IBUFDS_TRIGG_B : OBUFDS port map (O => B_TRIGGER, OB => B_TRIGGERB, I => b_trigg); + IBUFDS_TRIGG_C : OBUFDS port map (O => C_TRIGGER, OB => C_TRIGGERB, I => c_trigg); + IBUFDS_TRIGG_D : OBUFDS port map (O => D_TRIGGER, OB => D_TRIGGERB, I => d_trigg); + IBUFDS_REFERENCE : IBUFGDS generic map (IOSTANDARD => "LVDS_25_DCI") + port map ( O => reference_signal, I => VIR_TRIG, IB => VIR_TRIGB); + OBUFDS_BUNCH_RESET_A : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => A_TDC_BU_RESET, OB =>A_TDC_BU_RESETB , I => bunch_reset_i); + OBUFDS_EVENT_RESET_A : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => A_TDC_EV_RESET, OB =>A_TDC_EV_RESETB , I => event_reset_i); + OBUFDS_BUNCH_RESET_B : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => B_TDC_BU_RESET, OB =>B_TDC_BU_RESETB, I => bunch_reset_i); + OBUFDS_EVENT_RESET_B : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => B_TDC_EV_RESET, OB =>B_TDC_EV_RESETB, I => event_reset_i); + OBUFDS_BUNCH_RESET_C : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => C_TDC_BU_RESET, OB =>C_TDC_BU_RESETB, I => bunch_reset_i); + OBUFDS_EVENT_RESET_C : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => C_TDC_EV_RESET, OB =>C_TDC_EV_RESETB, I => event_reset_i); + OBUFDS_BUNCH_RESET_D : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => D_TDC_BU_RESET, OB =>D_TDC_BU_RESETB, I => bunch_reset_i); + OBUFDS_EVENT_RESET_D : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => D_TDC_EV_RESET, OB =>D_TDC_EV_RESETB, I => event_reset_i); + -- SPI ---------------------------------------------------------------------- + --A + OBUFDS_SCK_A : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => A_SCK, OB => A_SCKB, I => spi_sck_a); + OBUFDS_SDO_A : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => A_SDO, OB => A_SDOB, I => spi_sdo_a); + OBUFDS_CS_A : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => A_CS, OB => A_CSB, I => spi_cs_a); + IBUFDS_SDI_A : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI") + port map (I => A_SDI, IB => A_SDIB, O => spi_sdi_a); + spi_sck_a <= fpga_register_07_i(0); + spi_sdo_a <= fpga_register_07_i(1); + spi_cs_a <= fpga_register_07_i(2); + fpga_register_08_i(0) <= spi_sdi_a; + --B + OBUFDS_SCK_B : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => B_SCK, OB => B_SCKB, I => spi_sck_b); + OBUFDS_SDO_B : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => B_SDO, OB => B_SDOB, I => spi_sdo_b); + OBUFDS_CS_B : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => B_CS, OB => B_CSB, I => spi_cs_b); + IBUFDS_SDI_B : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI") + port map ( I => B_SDI, IB => B_SDIB, O => spi_sdi_b); + spi_sck_b <= fpga_register_07_i(3); + spi_sdo_b <= fpga_register_07_i(4); + spi_cs_b <= fpga_register_07_i(5); + fpga_register_08_i(1) <= spi_sdi_b; + --C + OBUFDS_SCK_C : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => C_SCK, OB => C_SCKB, I => spi_sck_c); + OBUFDS_SDO_C : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => C_SDO, OB => C_SDOB, I => spi_sdo_c); + OBUFDS_CS_C : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => C_CS, OB => C_CSB, I => spi_cs_c); + IBUFDS_SDI_C : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI") + port map ( I => C_SDI, IB => C_SDIB, O => spi_sdi_c); + spi_sck_c <= fpga_register_07_i(6); + spi_sdo_c <= fpga_register_07_i(7); + spi_cs_c <= fpga_register_07_i(8); + fpga_register_08_i(2) <= spi_sdi_c; + --D + OBUFDS_SCK_D : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => D_SCK, OB => D_SCKB, I => spi_sck_d); + OBUFDS_SDO_D : OBUFDS generic map (IOSTANDARD => "LVDS_25") + port map ( O => D_SDO, OB => D_SDOB, I => spi_sdo_d ); + OBUFDS_CS_D : OBUFDS generic map ( IOSTANDARD => "LVDS_25" ) + port map ( O => D_CS, OB => D_CSB, I => spi_cs_d ); + IBUFDS_SDI_D : IBUFDS generic map ( IOSTANDARD => "LVDS_25_DCI" ) + port map (I => D_SDI, IB => D_SDIB, O => spi_sdi_d ); + spi_sck_d <= fpga_register_07_i(9); + spi_sdo_d <= fpga_register_07_i(10); + spi_cs_d <= fpga_register_07_i(11); + fpga_register_08_i(3) <= spi_sdi_d; + -- Test signals -------------------------------------------------------------- + OBUFDS_TEST_A1 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" ) + port map ( O => A_TEST1, OB => A_TEST1B, I => test_a1 ); + OBUFDS_TEST_A2 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" ) + port map ( O => A_TEST2, OB => A_TEST2B, I => test_a2 ); + OBUFDS_TEST_B1 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" ) + port map ( O => B_TEST1, OB => B_TEST1B, I => test_b1 ); + OBUFDS_TEST_B2 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" ) + port map ( O => B_TEST2, OB => B_TEST2B, I => test_b2 ); + OBUFDS_TEST_C1 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" ) + port map ( O => C_TEST1, OB => C_TEST1B, I => test_c1 ); + OBUFDS_TEST_C2 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" ) + port map ( O => C_TEST2, OB => C_TEST2B, I => test_c2 ); + OBUFDS_TEST_D1 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" ) + port map ( O => D_TEST1, OB => D_TEST1B, I => test_d1 ); + OBUFDS_TEST_D2 : OBUFDS generic map ( IOSTANDARD => "LVDS_25" ) + port map ( O => D_TEST2, OB => D_TEST2B, I => test_d2 ); + --i should be able to switch on off 1 or 2 + COUNTER_FOR_TEST_1: process (CLK, external_reset_i,test_counter_1) + begin + if rising_edge(CLK) then + if external_reset_i = '1' or test_counter_1 > x"186A0"then --1kHz + test_counter_1 <= (others => '0'); + else + test_counter_1 <= test_counter_1 + 1; + end if; + end if; + end process COUNTER_FOR_TEST_1; + COUNTER_FOR_TEST_2: process (CLK, external_reset_i,test_counter_2) + begin + if rising_edge(CLK) then + if external_reset_i = '1' or test_counter_2 > x"186A0" then --1kHz + test_counter_2 <= (others => '0'); + else + test_counter_2 <= test_counter_2 + 1; + end if; + end if; + end process COUNTER_FOR_TEST_2; + --lenght of signal depend on this condition: test_counter_1 < x". ." + --frequency in process:. . or test_counter_x > x". ." + test_a1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0'; + test_b1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0'; + test_c1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0'; + test_d1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0'; + test_a2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0'; + test_b2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0'; + test_c2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0'; + test_d2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0'; + trigger_for_test_signal <= '1' when ((test_counter_1 > x"C8" and test_counter_1 < x"CC") and (fpga_register_06_i(1)='1' or fpga_register_06_i(2) ='1' )) else '0'; + -- ADD_LVDS ------------------------------------------------------------------ + ADO_LVDS: for line in 0 to 24 generate --62 lines in total + IBUFDS_LVDS : IBUFDS generic map ( - IOSTANDARD => "LVDS_25_DCI") - port map ( - O => CLK,--CLK, - I => VIRT_CLK, - IB => VIRT_CLKB -- Diff_n clock buffer input (connect to top-level port) - ); - -- TDC - IBUFGDS_TDC_CLK : IBUFGDS - generic map ( - IOSTANDARD => "LVDS_25_DCI") --_DCI - port map ( - O => tdc_clk, - I => REF_TDC_CLK, - IB => REF_TDC_CLKB-- Diff_n clock buffer input (connect to top-level port) - ); - IBUFDS_TRIGG_A : OBUFDS - port map ( - O => A_TRIGGER, - OB => A_TRIGGERB, - I => a_trigg - ); - IBUFDS_TRIGG_B : OBUFDS - port map ( - O => B_TRIGGER, - OB => B_TRIGGERB, - I => b_trigg - ); - IBUFDS_TRIGG_C : OBUFDS - port map ( - O => C_TRIGGER, - OB => C_TRIGGERB, - I => c_trigg - ); - IBUFDS_TRIGG_D : OBUFDS - port map ( - O => D_TRIGGER, - OB => D_TRIGGERB, - I => d_trigg - ); - IBUFDS_REFERENCE : IBUFGDS - generic map ( - IOSTANDARD => "LVDS_25_DCI") - port map ( - O => reference_signal, - I => VIR_TRIG, - IB => VIR_TRIGB - ); - - OBUFDS_BUNCH_RESET_A : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => A_TDC_BU_RESET, - OB =>A_TDC_BU_RESETB , - I => bunch_reset_i - ); - OBUFDS_EVENT_RESET_A : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => A_TDC_EV_RESET, - OB =>A_TDC_EV_RESETB , - I => event_reset_i - ); - OBUFDS_BUNCH_RESET_B : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => B_TDC_BU_RESET, - OB =>B_TDC_BU_RESETB , - I => bunch_reset_i - ); - OBUFDS_EVENT_RESET_B : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => B_TDC_EV_RESET, - OB =>B_TDC_EV_RESETB , - I => event_reset_i - ); - OBUFDS_BUNCH_RESET_C : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => C_TDC_BU_RESET, - OB =>C_TDC_BU_RESETB , - I => bunch_reset_i - ); - OBUFDS_EVENT_RESET_C : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => C_TDC_EV_RESET, - OB =>C_TDC_EV_RESETB , - I => event_reset_i - ); - - OBUFDS_BUNCH_RESET_D : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => D_TDC_BU_RESET, - OB =>D_TDC_BU_RESETB , - I => bunch_reset_i - ); - OBUFDS_EVENT_RESET_D : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => D_TDC_EV_RESET, - OB =>D_TDC_EV_RESETB , - I => event_reset_i - ); --- SPI - --A - OBUFDS_SCK_A : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => A_SCK, - OB => A_SCKB, - I => spi_sck_a - ); - OBUFDS_SDO_A : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => A_SDO, - OB => A_SDOB, - I => spi_sdo_a - ); - OBUFDS_CS_A : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => A_CS, - OB => A_CSB, - I => spi_cs_a - ); - IBUFDS_SDI_A : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => A_SDI, - IB => A_SDIB, - O => spi_sdi_a - ); - spi_sck_a <= fpga_register_07_i(0); - spi_sdo_a <= fpga_register_07_i(1); - spi_cs_a <= fpga_register_07_i(2); - fpga_register_08_i(0) <= spi_sdi_a; - --B - OBUFDS_SCK_B : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => B_SCK, - OB => B_SCKB, - I => spi_sck_b - ); - OBUFDS_SDO_B : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) + IOSTANDARD => "LVDS_25_DCI" + ) port map ( - O => B_SDO, - OB => B_SDOB, - I => spi_sdo_b - ); - OBUFDS_CS_B : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => B_CS, - OB => B_CSB, - I => spi_cs_b - ); - IBUFDS_SDI_B : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => B_SDI, - IB => B_SDIB, - O => spi_sdi_b - ); - spi_sck_b <= fpga_register_07_i(3); - spi_sdo_b <= fpga_register_07_i(4); - spi_cs_b <= fpga_register_07_i(5); - fpga_register_08_i(1) <= spi_sdi_b; - --C - OBUFDS_SCK_C : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => C_SCK, - OB => C_SCKB, - I => spi_sck_c - ); - OBUFDS_SDO_C : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => C_SDO, - OB => C_SDOB, - I => spi_sdo_c - ); - OBUFDS_CS_C : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => C_CS, - OB => C_CSB, - I => spi_cs_c - ); - IBUFDS_SDI_C : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => C_SDI, - IB => C_SDIB, - O => spi_sdi_c - ); - spi_sck_c <= fpga_register_07_i(6); - spi_sdo_c <= fpga_register_07_i(7); - spi_cs_c <= fpga_register_07_i(8); - fpga_register_08_i(2) <= spi_sdi_c; - --D - OBUFDS_SCK_D : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => D_SCK, - OB => D_SCKB, - I => spi_sck_d - ); - OBUFDS_SDO_D : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => D_SDO, - OB => D_SDOB, - I => spi_sdo_d - ); - OBUFDS_CS_D : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => D_CS, - OB => D_CSB, - I => spi_cs_d - ); - IBUFDS_SDI_D : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => D_SDI, - IB => D_SDIB, - O => spi_sdi_d - ); - spi_sck_d <= fpga_register_07_i(9); - spi_sdo_d <= fpga_register_07_i(10); - spi_cs_d <= fpga_register_07_i(11); - fpga_register_08_i(3) <= spi_sdi_d; --- Test signals - OBUFDS_TEST_A1 : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => A_TEST1, - OB => A_TEST1B, - I => test_a1 - ); - OBUFDS_TEST_A2 : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => A_TEST2, - OB => A_TEST2B, - I => test_a2 - ); - OBUFDS_TEST_B1 : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => B_TEST1, - OB => B_TEST1B, - I => test_b1 - ); - OBUFDS_TEST_B2 : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => B_TEST2, - OB => B_TEST2B, - I => test_b2 - ); - OBUFDS_TEST_C1 : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => C_TEST1, - OB => C_TEST1B, - I => test_c1 - ); - OBUFDS_TEST_C2 : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => C_TEST2, - OB => C_TEST2B, - I => test_c2 - ); - OBUFDS_TEST_D1 : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => D_TEST1, - OB => D_TEST1B, - I => test_d1 - ); - OBUFDS_TEST_D2 : OBUFDS - generic map ( - IOSTANDARD => "LVDS_25" - ) - port map ( - O => D_TEST2, - OB => D_TEST2B, - I => test_d2 --i should be able to switch on off 1 - --or 2 - ); - COUNTER_FOR_TEST_1: process (CLK, external_reset_i,test_counter_1) - begin - if rising_edge(CLK) then - if external_reset_i = '1' or test_counter_1 > x"186A0"then --1kHz - test_counter_1 <= (others => '0'); - else - test_counter_1 <= test_counter_1 + 1; - end if; - end if; - end process COUNTER_FOR_TEST_1; - COUNTER_FOR_TEST_2: process (CLK, external_reset_i,test_counter_2) - begin - if rising_edge(CLK) then - if external_reset_i = '1' or test_counter_2 > x"186A0" then --1kHz - test_counter_2 <= (others => '0'); - else - test_counter_2 <= test_counter_2 + 1; - end if; - end if; - end process COUNTER_FOR_TEST_2; - --lenght of signal depend on this condition: test_counter_1 < x". ." - --frequency in process:. . or test_counter_x > x". ." - test_a1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0'; - test_b1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0'; - test_c1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0'; - test_d1 <= '1' when (test_counter_1 < x"64" and fpga_register_06_i(1)='1') else '0'; - test_a2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0'; - test_b2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0'; - test_c2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0'; - test_d2 <= '1' when (test_counter_2 < x"64" and fpga_register_06_i(2)='1') else '0'; - trigger_for_test_signal <= '1' when ((test_counter_1 > x"C8" and test_counter_1 < x"CC") and (fpga_register_06_i(1)='1' or fpga_register_06_i(2) ='1' )) else '0'; --- ADD_LVDS - IBUFDS_LVDS_0 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(0), - IB => ADO_LV(1), - O => lvds_add_on_data(0) - ); - IBUFDS_LVDS_1 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(2), - IB => ADO_LV(3), - O => lvds_add_on_data(1) - ); - IBUFDS_LVDS_2 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(4), - IB => ADO_LV(5), - O => lvds_add_on_data(2) - ); - IBUFDS_LVDS_3 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(6), - IB => ADO_LV(7), - O => lvds_add_on_data(3) - ); - IBUFDS_LVDS_4 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(8), - IB => ADO_LV(9), - O => lvds_add_on_data(4) - ); - IBUFDS_LVDS_5 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(10), - IB => ADO_LV(11), - O => lvds_add_on_data(5) - ); - IBUFDS_LVDS_6 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(12), - IB => ADO_LV(13), - O => lvds_add_on_data(6) - ); - IBUFDS_LVDS_7 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(14), - IB => ADO_LV(15), - O => lvds_add_on_data(7) - ); - IBUFDS_LVDS_8 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(16), - IB => ADO_LV(17), - O => lvds_add_on_data(8) - ); - IBUFDS_LVDS_9 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(18), - IB => ADO_LV(19), - O => lvds_add_on_data(9) - ); - IBUFDS_LVDS_10 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(20), - IB => ADO_LV(21), - O => lvds_add_on_data(10) - ); - IBUFDS_LVDS_11 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(22), - IB => ADO_LV(23), - O => lvds_add_on_data(11) - ); - IBUFDS_LVDS_12 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(24), - IB => ADO_LV(25), - O => lvds_add_on_data(12) - ); - IBUFDS_LVDS_13 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(26), - IB => ADO_LV(27), - O => lvds_add_on_data(13) - ); - IBUFDS_LVDS_14 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(28), - IB => ADO_LV(29), - O => lvds_add_on_data(14) - ); - IBUFDS_LVDS_15 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(30), - IB => ADO_LV(31), - O => lvds_add_on_data(15) - ); - IBUFDS_LVDS_16 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(32), - IB => ADO_LV(33), - O => lvds_add_on_data(16) - ); - IBUFDS_LVDS_17 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(34), - IB => ADO_LV(35), - O => lvds_add_on_data(17) - ); - IBUFDS_LVDS_18 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(36), - IB => ADO_LV(37), - O => lvds_add_on_data(18) - ); - IBUFDS_LVDS_19 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(38), - IB => ADO_LV(39), - O => lvds_add_on_data(19) - ); - IBUFDS_LVDS_20 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(40), - IB => ADO_LV(41), - O => lvds_add_on_data(20) - ); - IBUFDS_LVDS_21 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(42), - IB => ADO_LV(43), - O => lvds_add_on_data(21) - ); - IBUFDS_LVDS_22 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(44), - IB => ADO_LV(45), - O => lvds_add_on_data(22) - ); - IBUFDS_LVDS_23 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(46), - IB => ADO_LV(47), - O => lvds_add_on_data(23) - ); - IBUFDS_LVDS_24 : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(48), - IB => ADO_LV(49), - O => lvds_add_on_data(24) - ); - IBUFDS_LVDS_25_DCI : IBUFDS - generic map ( - IOSTANDARD => "LVDS_25_DCI" - ) - port map ( - I => ADO_LV(50), - IB => ADO_LV(51), - O => lvds_add_on_data(25) - ); --- IBUFDS_LVDS_26 : IBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25_DCI" --- ) --- port map ( --- I => ADO_LV(52), --- IB => ADO_LV(53), --- O => lvds_add_on_data(26) --- ); --- IBUFDS_LVDS_27 : IBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25_DCI" --- ) --- port map ( --- I => ADO_LV(54), --- IB => ADO_LV(55), --- O => lvds_add_on_data(27) --- ); --- IBUFDS_LVDS_28 : IBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25_DCI" --- ) --- port map ( --- I => ADO_LV(56) , --- IB => ADO_LV(57), --- O => lvds_add_on_data(28) --- ); --- IBUFDS_LVDS_29 : IBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25_DCI" --- ) --- port map ( --- I => ADO_LV(58), --- IB => ADO_LV(59), --- O => lvds_add_on_data(29) --- ); --- IBUFDS_LVDS_30 : IBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25_DCI" --- ) --- port map ( --- I => ADO_LV(60), --- IB => ADO_LV(61), --- O => lvds_add_on_data(30) --- ); - save_tlk_data: process (tlk_rx_clk_r, external_reset_i) - begin - if rising_edge(tlk_rx_clk_r) then - if external_reset_i = '1' then - saved_txd <= (others => '0'); - elsif TLK_RX_DV ='1'and TLK_RX_ER = '0' then - saved_txd <= TLK_RXD; - else - saved_txd <=saved_txd; - end if; - end if; - end process save_tlk_data; - --- ADO_TTL(0) <= apl_dataready_out_i; --- ADO_TTL(4 downto 1) <= apl_seqnr_out_i(3 downto 0); --- ADO_TTL(8) <= med_dataready_out_i; --- ADO_TTL(6 downto 5) <= apl_data_out_i(1 downto 0); --- ADO_TTL(7) <= end_of_transfer; --- ADO_TTL(9) <= med_dataready_in_i; --- ADO_TTL(10) <= apl_send_in_i; --- ADO_TTL(12 downto 11) <= stat_reply_buffer_i(15 downto 14); --- ADO_TTL(15 downto 13) <= api_stat_fifo_to_int_i(31 downto 29);--stat_reply_buffer_i(15 downto 14); - --- MED_DATA_READY_SYNCH: process (CLK, external_reset_i) --- begin --- if rising_edge( CLK) then --- if external_reset_i = '1' then --- med_dataready_in_i <= '0'; --- else --- med_dataready_in_i <= med_dataready_in_synch; --- end if; --- end if; --- end process MED_DATA_READY_SYNCH; - + I => ADO_LV(line*2), + IB => ADO_LV(line*2+1), + O => lvds_add_on_data(line) + ); + end generate ADO_LVDS; +------------------------------------------------------------------------------- +-- reset at startup +------------------------------------------------------------------------------- -- -- STARTUP_VIRTEX4_inst : STARTUP_VIRTEX4 -- port map ( @@ -1540,88 +979,11 @@ begin -- USRCCLKTS => open, -- USRCCLKTS 1-bit input -- USRDONEO => open, -- USRDONEO 1-bit input -- USRDONETS => open -- USRDONETS 1-bit input --- ); ---Shark links --- DSP_L0DATIP : out std_logic_vector (3 downto 0); --- DSP_L0DATIN : out std_logic_vector (3 downto 0); --- DSP_L0DATOP : in std_logic_vector (3 downto 0); --- DSP_L0DATON : in std_logic_vector (3 downto 0); --- DSP_L0CLKINP : out std_logic; --- DSP_L0CLKINN : out std_logic; --- DSP_L0CLKOUTP : in std_logic; --- DSP_L0CLKOUTN : in std_logic; --- DSP_DATA_LINK0_OUT_0 : IBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25" --- ) --- port map ( --- I => , --- IB =>, --- O => --- ); --- DSP_DATA_LINK0_OUT_1 : IBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25" --- ) --- port map ( --- I => , --- IB =>, --- O => --- ); --- DSP_DATA_LINK0_OUT_2 : IBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25" --- ) --- port map ( --- I => , --- IB =>, --- O => --- ); --- DSP_DATA_LINK0_OUT_3 : IBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25" --- ) --- port map ( --- I => , --- IB =>, --- O => --- ); --- DSP_DATA_LINK0_IN_0 : OBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25" --- ) --- port map ( --- I => , --- IB =>, --- O => dsp_link_data_in_0(0) --- ); --- DSP_DATA_LINK0_IN_1 : OBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25" --- ) --- port map ( --- I => , --- IB =>, --- O => dsp_link_data_in_0(1) --- ; --- DSP_DATA_LINK0_IN_2 : OBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25" --- ) --- port map ( --- I => , --- IB =>, --- O =>dsp_link_data_in_0(2) --- ); --- DSP_DATA_LINK0_IN_3 : OBUFDS --- generic map ( --- IOSTANDARD => "LVDS_25" --- ) --- port map ( --- I => , --- IB =>, --- O => dsp_link_data_in_0(3) --- ); +-- ); +------------------------------------------------------------------------------- +-- tiger sharc dma +------------------------------------------------------------------------------- + ------------------------------------------------------------------------------- -- api ------------------------------------------------------------------------------- @@ -1694,106 +1056,123 @@ begin -- end if; -- end if; -- end process COUNTER_FOR_API; - - ----------------------------------------------------------------------------- - -- Component Instance - ----------------------------------------------------------------------------- - reset_i <= not RESET_VIRT; - TOKEN_OUT <= token_out_i; - TDC_INT: tdc_interface - port map ( - CLK => CLK, - TDC_CLK => tdc_clk,--CLK,--tdc_clk,--mdc addon or CLK - RESET => external_reset_i,--not RESET_VIRT, - -- TDC_RESET => TDC_RESET, - TDC_DATA_IN => TDC_OUT,--x"0" & "00" & lvds_add_on_data(25 downto 0),--TDC_OUT,--mdc addon or - START_TDC_READOUT => lvl1_trigger_i,--lvl1_tdc_trigg_i, - A_TDC_ERROR => A_TDC_ERROR, - B_TDC_ERROR => B_TDC_ERROR, - C_TDC_ERROR => C_TDC_ERROR, - D_TDC_ERROR => D_TDC_ERROR, - A_TDC_POWERUP => open, --A_TDC_POWERUP, - B_TDC_POWERUP => open, --B_TDC_POWERUP, - C_TDC_POWERUP => open, --C_TDC_POWERUP, - D_TDC_POWERUP => open, --D_TDC_POWERUP, - A_TDC_READY => A_DATA_READY,--ADO_TTL(3),--A_DATA_READY,mdc addon or - B_TDC_READY => B_DATA_READY,--ADO_TTL(3),--B_DATA_READY,mdc addon or - C_TDC_READY => C_DATA_READY,--ADO_TTL(3),--C_DATA_READY,mdc addon or - D_TDC_READY => D_DATA_READY,--ADO_TTL(3),--D_DATA_READY,mdc addon or - SEND_TDC_TOKEN => token_out_i, - RECEIVED_TDC_TOKEN => TOKEN_IN,--ADO_TTL(2),--TOKEN_IN,--mdc addon or - --normal - GET_TDC_DATA => GET_DATA, - TO_MANY_TDC_DATA => to_many_tdc_data_i, - TDC_READOUT_COMPLETED => tdc_readout_completed_i, - LVL1_TAG => lvl1_trigger_tag_i,--TLK_RXD(7 downto 0),--apl_seqnr_out_i,--tdc_tag_i, - LVL1_CODE => lvl1_trigger_code_i,--TLK_RXD(11 downto 8),--apl_data_out_i(3 downto 0),--tdc_code_i, - HOW_MANY_ADD_DATA => fpga_register_06_i(23 downto 16),--how_many_add_data_i, - COUNTER_a => test_counter_1,--scaler_counter_0,--x"12311231", - COUNTER_b => scaler_counter_0,--x"12321232", - COUNTER_c => scaler_counter_1,--x"12331233", - COUNTER_d => scaler_counter_2,--x"12341234", - COUNTER_e => scaler_counter_3,--x"12351235", - COUNTER_f => scaler_counter_4,--x"12361236", - COUNTER_g => scaler_counter_5,--x"12371237", - COUNTER_h => scaler_counter_6,--x"12381238", - LVL2_TRIGGER => lvl2_trigger_i,--lvl2_tdc_trigg_i, here - TDC_DATA_OUT => tdc_data_out_i, - TDC_DATA_VALID => tdc_data_valid_i, - ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i, - LVL1_BUSY => lvl1_busy_i, - LVL2_BUSY => lvl2_busy_i, - TDC_REGISTER_00 => tdc_register_00_i, - TDC_REGISTER_01 => tdc_register_01_i, - TDC_REGISTER_02 => tdc_register_02_i, - TDC_REGISTER_03 => tdc_register_03_i, - TDC_REGISTER_04 => tdc_register_04_i, - TDC_REGISTER_05 => fpga_register_0e_i, - BUNCH_RESET => bunch_reset_i, - EVENT_RESET => event_reset_i, - READ_ADRESS_END_UP => trb_ack_lvl2_i, - DELAY_TRIGGER => x"00",--fpga_register_06_i(31 downto 24), - TDC_START => trigger_to_tdc_i, - TRIGGER_WITHOUT_HADES => fpga_register_06_i(7), - TRIGGER_WITH_GEN_EN => fpga_register_06_i(8), - TRIGGER_WITH_GEN => not_hades_trigger--trigger_for_test_signal or generator_trigger - ); - ADO_TTL(42 downto 35) <= tdc_register_01_i(26 downto 19); - not_hades_trigger <= trigger_for_test_signal or generator_trigger_1 or generator_trigger_2; - end_of_transfer <= not tdc_data_valid_i; - LVL2_BUSY_END_PULSER : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => end_of_transfer, - pulse => apl_send_in_i); - not_lvl1_busy <= not lvl1_busy_i; - LVL1_BUSY_PULSER : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => lvl1_busy_i, - pulse => apl_read_in_i); - LVL1_OPT_PULSER : edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => TLK_RX_DV, - pulse => lvl1_tdc_trigg_i); - LVL2_OPT_END_PULSER : edge_to_pulse - port map ( - clock => tlk_rx_clk_r, - en_clk => '1', - signal_in => end_of_transfer, - pulse => TLK_TX_EN); - TLK_TXD <= x"abcd"; - TLK_TX_ER <= '0'; --- SFP_TX_DIS <= '0'; - TLK_LOOPEN <= '0'; - TLK_LCKREFN <= '1'; - TLK_ENABLE <= '1'; - TLK_PRBSEN <= '0'; +----------------------------------------------------------------------------- +-- tdc interface +----------------------------------------------------------------------------- + reset_i <= not RESET_VIRT; + TOKEN_OUT <= token_out_i; + TDC_RESET <= '0';--fpga_register_06_i(5);--'0'; + VIRT_TRST <= not fpga_register_06_i(5);--'1'; + TDC_INT : tdc_interface + port map ( + CLK => CLK, + TDC_CLK => tdc_clk, --CLK,--tdc_clk, --mdc addon or CLK + RESET => external_reset_i, --not RESET_VIRT, + -- TDC_RESET => TDC_RESET, + TDC_DATA_IN => TDC_OUT, --x"0" & "00" & lvds_add_on_data(25 downto 0),--TDC_OUT, --mdc addon or + START_TDC_READOUT => lvl1_trigger_i, --lvl1_tdc_trigg_i, + A_TDC_ERROR => A_TDC_ERROR, + B_TDC_ERROR => B_TDC_ERROR, + C_TDC_ERROR => C_TDC_ERROR, + D_TDC_ERROR => D_TDC_ERROR, + A_TDC_POWERUP => open, --A_TDC_POWERUP, + B_TDC_POWERUP => open, --B_TDC_POWERUP, + C_TDC_POWERUP => open, --C_TDC_POWERUP, + D_TDC_POWERUP => open, --D_TDC_POWERUP, + A_TDC_READY => A_DATA_READY, --ADO_TTL(3), --A_DATA_READY,mdc addon or + B_TDC_READY => B_DATA_READY, --ADO_TTL(3), --B_DATA_READY,mdc addon or + C_TDC_READY => C_DATA_READY, --ADO_TTL(3), --C_DATA_READY,mdc addon or + D_TDC_READY => D_DATA_READY, --ADO_TTL(3), --D_DATA_READY,mdc addon or + SEND_TDC_TOKEN => token_out_i, + RECEIVED_TDC_TOKEN => TOKEN_IN, --ADO_TTL(2),--TOKEN_IN, --mdc addon or + --normal + GET_TDC_DATA => GET_DATA, + TO_MANY_TDC_DATA => to_many_tdc_data_i, + TDC_READOUT_COMPLETED => tdc_readout_completed_i, + LVL1_TAG => lvl1_trigger_tag_i, --TLK_RXD(7 downto 0),--apl_seqnr_out_i, --tdc_tag_i, + LVL1_CODE => lvl1_trigger_code_i, --TLK_RXD(11 downto 8),--apl_data_out_i(3 downto 0), --tdc_code_i, + HOW_MANY_ADD_DATA => fpga_register_06_i(23 downto 16), --how_many_add_data_i, + COUNTER_a => test_counter_1, --scaler_counter_0, --x"12311231", + COUNTER_b => scaler_counter(0), --x"12321232", + COUNTER_c => scaler_counter(1), --x"12331233", + COUNTER_d => scaler_counter(2), --x"12341234", + COUNTER_e => scaler_counter(3), --x"12351235", + COUNTER_f => scaler_counter(4), --x"12361236", + COUNTER_g => scaler_counter(5), --x"12371237", + COUNTER_h => scaler_counter(6), --x"12381238", + LVL2_TRIGGER => lvl2_trigger_i, --lvl2_tdc_trigg_i, here + TDC_DATA_OUT => tdc_data_out_i, + TDC_DATA_VALID => tdc_data_valid_i, + ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i, + LVL1_BUSY => lvl1_busy_i, + LVL2_BUSY => lvl2_busy_i, + TDC_REGISTER_00 => tdc_register_00_i, + TDC_REGISTER_01 => tdc_register_01_i, + TDC_REGISTER_02 => tdc_register_02_i, + TDC_REGISTER_03 => tdc_register_03_i, + TDC_REGISTER_04 => tdc_register_04_i, + TDC_REGISTER_05 => fpga_register_0e_i, + BUNCH_RESET => bunch_reset_i, + EVENT_RESET => event_reset_i, + READ_ADRESS_END_UP => trb_ack_lvl2_i, + DELAY_TRIGGER => x"00", --fpga_register_06_i(31 downto 24), + TDC_START => trigger_to_tdc_i, + TRIGGER_WITHOUT_HADES => fpga_register_06_i(7), + TRIGGER_WITH_GEN_EN => fpga_register_06_i(8), + TRIGGER_WITH_GEN => not_hades_trigger --trigger_for_test_signal or generator_trigger + ); + --ADO_TTL(42 downto 35) <= tdc_register_01_i(26 downto 19); + not_hades_trigger <= trigger_for_test_signal or generator_trigger_1 or generator_trigger_2; + a_trigg <= trigger_to_tdc_i; + b_trigg <= trigger_to_tdc_i; + c_trigg <= trigger_to_tdc_i; + d_trigg <= trigger_to_tdc_i; + A_TDC_POWERUP <= '1'; --in trbv2c this is diod + B_TDC_POWERUP <= '1'; --in trbv2c this is diod + C_TDC_POWERUP <= '1'; --in trbv2c this is diod + D_TDC_POWERUP <= '1'; --in trbv2c this is diod + DBAD <= lvl1_busy_i; + DINT <= etrax_bus_busy_i; + DWAIT <= fpga_register_06_i(6); +-- not hades trigger ---------------------------------------------------------- + EXT_TRIGGER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => ADO_TTL(0), + pulse => generator_trigger_1); + generator_trigger_2 <= '0'; + ADO_TTL(0) <= 'Z'; +------------------------------------------------------------------------------- +-- tdc to api +------------------------------------------------------------------------------- + end_of_transfer <= not tdc_data_valid_i; + LVL2_BUSY_END_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => end_of_transfer, + pulse => apl_send_in_i); + not_lvl1_busy <= not lvl1_busy_i; + LVL1_BUSY_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => lvl1_busy_i, + pulse => apl_read_in_i); + LVL1_OPT_PULSER : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => TLK_RX_DV, + pulse => lvl1_tdc_trigg_i); + LVL2_OPT_END_PULSER : edge_to_pulse + port map ( + clock => tlk_rx_clk_r, + en_clk => '1', + signal_in => end_of_transfer, + pulse => TLK_TX_EN); -- ADO_TTL(0) <= TLK_RX_DV; -- ADO_TTL(1) <= lvl1_tdc_trigg_i; -- ADO_TTL(2) <= fs_pc17;--FS_PC(17);--'0'; @@ -1802,12 +1181,11 @@ begin -- ADO_TTL(5) <= lvl2_busy_i; -- ADO_TTL(6) <= end_of_transfer; -- ADO_TTL(7) <= TLK_RX_ER; - -- lvl2_tdc_trigg_i <= '0' & apl_send_in_i; --should be real in normal operation -- 0 reset 1 token 2-5 code 6 token_back 7 data valid - -------------------------------------------------------------------------- - -- MDCaddon mdc addon or . . . --- -------------------------------------------------------------------------- +------------------------------------------------------------------------- +-- MDCaddon mdc addon or . . . +-------------------------------------------------------------------------- -- lvds_add_on_data(31) <= '1'; -- SEND_CODE: process (CLK, external_reset_i) -- begin @@ -1821,22 +1199,19 @@ begin -- end process SEND_CODE; -- ADO_TTL(7 downto 4) <= x"d" when switch_for_start ='0' else x"1"; -- not_external_reset <= not external_reset_i; - -- SEND_TDC_TRIGGER : edge_to_pulse -- port map ( -- clock => clk, -- en_clk => '1', -- signal_in => not_external_reset, -- pulse => not_reset_pulse); - -- ADO_TTL(1) <= token_out_i or not_reset_pulse; -- ADO_TTL(2) <= 'Z'; -- ADO_TTL(3) <= 'Z'; - -- ADO_TTL(0) <= external_reset_i; - -------------------------------------------------------------------------- - -- self mdc - -------------------------------------------------------------------------- +-------------------------------------------------------------------------- +-- self mdc +-------------------------------------------------------------------------- -- COUNTER_FOR_SELF_TOKEN_BACK: process (CLK,token_out_i) -- begin -- process COUNTER_FOR_SELF_TOKEN_BACK -- if rising_edge(CLK) then @@ -1851,7 +1226,6 @@ begin -- end process COUNTER_FOR_SELF_TOKEN_BACK; -- self_token <= '1' when token_counter = x"0a" else '0'; -- self_data_valid <= '1' when token_counter < x"0a" else '0'; - -- SYNCH_EXT_TRIGG: process (CLK, external_reset_i) -- begin -- process SYNCH_EXT_TRIGG -- if rising_edge(CLK) then -- rising clock edge @@ -1866,29 +1240,25 @@ begin -- end if; -- end if; -- end process SYNCH_EXT_TRIGG; - a_trigg <= trigger_to_tdc_i; - b_trigg <= trigger_to_tdc_i; - c_trigg <= trigger_to_tdc_i; - d_trigg <= trigger_to_tdc_i; - - tdc_control_register_i <= "0000000" & fpga_register_06_i(7);--tdc_control_register_e(7 downto 0); - - MULTIPLEX_DATA_TO_ETRAX: process(CLK,external_reset_i,external_mode_i) - begin - if rising_edge(CLK) then - if external_reset_i = '1' then - external_data_in_i <= (others => '0'); - elsif external_mode_i(7 downto 0) = x"01" then - external_data_in_i <= dsp_data_out_i; - elsif external_mode_i(7 downto 0) = x"02" then - external_data_in_i <= sdram_data_out_i; --- elsif external_mode_i(7 downto 0) = x"03" then +----------------------------------------------------------------------------- +-- MULTIPLEX_DATA_TO_ETRAX +----------------------------------------------------------------------------- + MULTIPLEX_DATA_TO_ETRAX: process(CLK,external_reset_i,external_mode_i) + begin + if rising_edge(CLK) then + if external_reset_i = '1' then + external_data_in_i <= (others => '0'); + elsif external_mode_i(7 downto 0) = x"01" then + external_data_in_i <= dsp_data_out_i; + elsif external_mode_i(7 downto 0) = x"02" then + external_data_in_i <= sdram_data_out_i; +-- elsif external_mode_i(7 downto 0) = x"03" then -- external_data_in_i <= x"add000" & ADO_TTL(42 downto 35); - else - external_data_in_i <= x"0000"&external_mode_i; - end if; - end if; - end process MULTIPLEX_DATA_TO_ETRAX; + else + external_data_in_i <= x"0000"&external_mode_i; + end if; + end if; + end process MULTIPLEX_DATA_TO_ETRAX; -- ADO_TTL(42 downto 35) <= (others => 'Z'); -- ADO_TTL(34 downto 19) <= external_address_i(15 downto 0); -- ADO_TTL(18 downto 11) <= external_data_out_i(7 downto 0); @@ -1898,98 +1268,94 @@ begin -- -- external_valid_i <= dsp_external_valid_i or sdram_external_valid_i or ADO_TTL(12); -- external_valid_i <= ADO_TTL(8); -- ADO_TTL(8) <= 'Z'; - - - ETRAX_INTERFACE_LOGIC : etrax_interface - port map ( - CLK => CLK, - RESET => reset_i, - DATA_BUS => tdc_data_out_i, - ETRAX_DATA_BUS_B => FS_PB, - ETRAX_DATA_BUS_C => FS_PC, - DATA_VALID => tdc_data_valid_i, - ETRAX_BUS_BUSY => etrax_bus_busy_i, - ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i, - TDC_TCK => VIRT_TCK, - TDC_TDI => VIRT_TDI, - TDC_TMS => VIRT_TMS, - TDC_TRST => open, --VIRT_TRST, - TDC_TDO => VIRT_TDO, - TDC_RESET => open, --TDC_RESET, - EXTERNAL_ADDRESS => external_address_i, - EXTERNAL_DATA_OUT => external_data_out_i, - EXTERNAL_DATA_IN => external_data_in_i, - EXTERNAL_ACK => external_ack_i, - EXTERNAL_VALID => external_valid_i, - EXTERNAL_MODE => external_mode_i, - FPGA_REGISTER_00 => x"00000000", - FPGA_REGISTER_01 => fpga_register_01_i,--ppp tlk_register_00_i, - FPGA_REGISTER_02 => fpga_register_02_i,--ppp tlk_register_01_i, - FPGA_REGISTER_03 => fpga_register_03_i,--ppp tdc_register_00_i,--x"abbaab02", - FPGA_REGISTER_04 => fpga_register_04_i, --ppp busy_register_00_i, - FPGA_REGISTER_05 => tdc_register_04_i,--lvds_add_on_data(31 downto 0),--tdc_register_04_i,--fpga_register_05_i, --ppp trigger_register_00_i, - FPGA_REGISTER_06 => fpga_register_06_i,--open, -- ppp x"abbaab05", - FPGA_REGISTER_07 => fpga_register_07_i, - FPGA_REGISTER_08 => fpga_register_08_i, - FPGA_REGISTER_09 => fpga_register_09_i, - FPGA_REGISTER_0A => fpga_register_0A_i, - FPGA_REGISTER_0B => fpga_register_0b_i, - FPGA_REGISTER_0C => fpga_register_0c_i, - FPGA_REGISTER_0D => fpga_register_0d_i, - FPGA_REGISTER_0E => fpga_register_0e_i, - EXTERNAL_RESET => external_reset, - LVL2_VALID => '0'--lvl2_trigger_code_i(3) - ); --- lvl2_valid_i <= lvl2_trigger_code_i(3); - fpga_register_01_i <= tdc_register_00_i; - fpga_register_02_i <= tdc_register_01_i;--tdc_data_valid_i & write_lvl1_busy_i & lvl2_busy_fast & lvl2_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl1_busy_i & trigger_register_00_i(11 downto 0) & sdram_register_00_i(5 downto 0) & dsp_register_00_i(2 downto 0); - fpga_register_03_i <= tdc_register_02_i;--busy_register_01_i; - fpga_register_04_i <= tdc_register_03_i; - fpga_register_05_i <= tdc_register_04_i; - fpga_register_09_i <= x"000" & "00" & TLK_RX_ER & TLK_RX_DV & TLK_RXD;--tlk_register_00_i; - fpga_register_0a_i <= tlk_register_01_i; - fpga_register_0b_i <= saved_txd & x"00" & apl_seqnr_out_i; - fpga_register_0c_i <= med_data_in_i_saved(63 downto 32);--stat_reply_buffer_i; - fpga_register_0d_i <= med_data_in_i_saved(31 downto 0);--stat_init_buffer_i; --- lvds_or <= lvds_add_on_data(0) or lvds_add_on_data(1) or --- lvds_add_on_data(2) or lvds_add_on_data(3) or --- lvds_add_on_data(4) or lvds_add_on_data(5) or --- lvds_add_on_data(6) or lvds_add_on_data(7) or --- lvds_add_on_data(8) or lvds_add_on_data(9) or --- lvds_add_on_data(10) or lvds_add_on_data(11) or --- lvds_add_on_data(12) or lvds_add_on_data(13) or --- lvds_add_on_data(14) or lvds_add_on_data(15) or --- lvds_add_on_data(16) or lvds_add_on_data(17) or --- lvds_add_on_data(18) or lvds_add_on_data(19) or --- lvds_add_on_data(20) or lvds_add_on_data(21) or --- lvds_add_on_data(22) or lvds_add_on_data(23) or --- lvds_add_on_data(24) or lvds_add_on_data(25) ; - - - SYNCH_RESET: process (CLK) - begin -- process SYNCH_RESET - if rising_edge(CLK) then -- rising clock edge - external_reset_i <= external_reset; - else - external_reset_i <= external_reset_i; - end if; - end process SYNCH_RESET; - fpga_register_10_i <= x"0000"& external_mode_i; - TLK_RX_CLK_BUFR: BUFR - port map( - CE => '1', - CLR => '0', - I => TLK_RX_CLK, - O => tlk_rx_clk_r - ); - TLK_CLK_BUFR: BUFR - port map( - CE => '1', - CLR => '0', - I => TLK_CLK, - O => tlk_clk_r - ); --- tlk_interface_logic: tlk_interface +------------------------------------------------------------------------------- +-- etrax interface +------------------------------------------------------------------------------- + ETRAX_INTERFACE_LOGIC : etrax_interface + port map ( + CLK => CLK, + RESET => reset_i, + DATA_BUS => tdc_data_out_i, + ETRAX_DATA_BUS_B => FS_PB, + ETRAX_DATA_BUS_C => FS_PC, + DATA_VALID => tdc_data_valid_i, + ETRAX_BUS_BUSY => etrax_bus_busy_i, + ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i, + TDC_TCK => VIRT_TCK, + TDC_TDI => VIRT_TDI, + TDC_TMS => VIRT_TMS, + TDC_TRST => open, --VIRT_TRST, + TDC_TDO => VIRT_TDO, + TDC_RESET => open, --TDC_RESET, + EXTERNAL_ADDRESS => external_address_i, + EXTERNAL_DATA_OUT => external_data_out_i, + EXTERNAL_DATA_IN => external_data_in_i, + EXTERNAL_ACK => external_ack_i, + EXTERNAL_VALID => external_valid_i, + EXTERNAL_MODE => external_mode_i, + FPGA_REGISTER_00 => x"00000000", + FPGA_REGISTER_01 => fpga_register_01_i, --ppp tlk_register_00_i, + FPGA_REGISTER_02 => fpga_register_02_i, --ppp tlk_register_01_i, + FPGA_REGISTER_03 => fpga_register_03_i, --ppp tdc_register_00_i, --x"abbaab02", + FPGA_REGISTER_04 => fpga_register_04_i, --ppp busy_register_00_i, + FPGA_REGISTER_05 => tdc_register_04_i, --lvds_add_on_data(31 downto 0),--tdc_register_04_i,--fpga_register_05_i, --ppp trigger_register_00_i, + FPGA_REGISTER_06 => fpga_register_06_i, --open, -- ppp x"abbaab05", + FPGA_REGISTER_07 => fpga_register_07_i, + FPGA_REGISTER_08 => fpga_register_08_i, + FPGA_REGISTER_09 => fpga_register_09_i, + FPGA_REGISTER_0A => fpga_register_0A_i, + FPGA_REGISTER_0B => fpga_register_0b_i, + FPGA_REGISTER_0C => fpga_register_0c_i, + FPGA_REGISTER_0D => fpga_register_0d_i, + FPGA_REGISTER_0E => fpga_register_0e_i, + EXTERNAL_RESET => external_reset, + LVL2_VALID => '0' --lvl2_trigger_code_i(3) + ); + fpga_register_01_i <= tdc_register_00_i; + fpga_register_02_i <= tdc_register_01_i;--tdc_data_valid_i & write_lvl1_busy_i & lvl2_busy_fast & lvl2_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl1_busy_i & trigger_register_00_i(11 downto 0) & sdram_register_00_i(5 downto 0) & dsp_register_00_i(2 downto 0); + fpga_register_03_i <= tdc_register_02_i;--busy_register_01_i; + fpga_register_04_i <= tdc_register_03_i; + fpga_register_05_i <= tdc_register_04_i; + fpga_register_09_i <= x"000" & "00" & TLK_RX_ER & TLK_RX_DV & TLK_RXD;--tlk_register_00_i; + fpga_register_0a_i <= tlk_register_01_i; + fpga_register_0b_i <= saved_txd & x"00" & apl_seqnr_out_i; + fpga_register_0c_i <= med_data_in_i_saved(63 downto 32);--stat_reply_buffer_i; + fpga_register_0d_i <= med_data_in_i_saved(31 downto 0);--stat_init_buffer_i; + SYNCH_RESET: process (CLK) + begin -- process SYNCH_RESET + if rising_edge(CLK) then -- rising clock edge + external_reset_i <= external_reset; + else + external_reset_i <= external_reset_i; + end if; + end process SYNCH_RESET; + fpga_register_10_i <= x"0000"& external_mode_i; +------------------------------------------------------------------------------- +-- tlk +------------------------------------------------------------------------------- + DGOOD <= lvl2_busy_i; + TLK_TXD <= x"abcd"; + TLK_TX_ER <= '0'; + SFP_TX_DIS <= fpga_register_06_i(15); + TLK_LOOPEN <= '0'; + TLK_LCKREFN <= '1'; + TLK_ENABLE <= '1'; + TLK_PRBSEN <= '0'; + TLK_RX_CLK_BUFR: BUFR + port map( + CE => '1', + CLR => '0', + I => TLK_RX_CLK, + O => tlk_rx_clk_r + ); + TLK_CLK_BUFR: BUFR + port map( + CE => '1', + CLR => '0', + I => TLK_CLK, + O => tlk_clk_r + ); +-- tlk_interface_logic: tlk_interface -- port map ( -- VIRT_CLK => CLK, -- ENABLE => TLK_ENABLE, @@ -2015,30 +1381,26 @@ begin -- TLK_TX_EN <= '0'; -- TLK_TX_ER <= '0'; -- fpga_register_08_i(4) <= SFP_LOS; - SFP_TX_DIS <= fpga_register_06_i(15); - - - DSP_DATA_REGISTER: process (CLK, external_reset_i) - begin -- process DSP_DATA_REGISTER - if CLK'event and CLK = '1' then - if external_reset_i = '1' then - dsp_data_reg_in_i <= x"00000000"; - dsp_data_reg_out_i <= x"00000000"; - dsp_bm_reg <= '0'; - sdram_data_i <= x"00000000"; --- fs_pc17 <= '0'; - else - dsp_bm_reg <= DSP_BM; - dsp_data_reg_in_i <= DSPDAT; - dsp_data_reg_out_i <= dspdat_out_i; - sdram_data_i <= VSD_D ; --- fs_pc17 <= FS_PC(17); - end if; - end if; - end process DSP_DATA_REGISTER; - +------------------------------------------------------------------------------- +-- dsp +------------------------------------------------------------------------------- + DSP_DATA_REGISTER: process (CLK, external_reset_i) + begin -- process DSP_DATA_REGISTER + if CLK'event and CLK = '1' then + if external_reset_i = '1' then + dsp_data_reg_in_i <= x"00000000"; + dsp_data_reg_out_i <= x"00000000"; + dsp_bm_reg <= '0'; + sdram_data_i <= x"00000000"; + else + dsp_bm_reg <= DSP_BM; + dsp_data_reg_in_i <= DSPDAT; + dsp_data_reg_out_i <= dspdat_out_i; + sdram_data_i <= VSD_D ; + end if; + end if; + end process DSP_DATA_REGISTER; -- DSP_HBR <= '1'; - -- DSP_RESET <= fpga_register_06_i(4); -- DSP_HBR <= dsp_hbr_i; -- DSPDAT <= dspdat_out_i; @@ -2047,7 +1409,6 @@ begin -- DSP_RD <= DSP_RD_i; -- DSPADDR <= dspaddr_i; -- DSP_BOFF <= fpga_register_06_i(5); - -- DSP_IRQ <= x"1"; -- DSP_BMS <= '1' when fpga_register_06_i(3) = '0' else 'Z'; -- DSP_BM <= '0' when fpga_register_06_i(3) = '0' else 'Z'; @@ -2075,6 +1436,9 @@ begin -- VALID_DATA_SENT => dsp_external_valid_i, -- ACKNOWLEDGE => dsp_strobe_i, -- DEBUGSTATE_MACHINE => dsp_register_00_i); +------------------------------------------------------------------------------- +-- sdram interface +------------------------------------------------------------------------------- -- SDRAM_INTERFACE_LOGIC: sdram_interface -- port map ( -- CLK_SDRAM => VSD_CLOCK, @@ -2100,6 +1464,9 @@ begin VSD_CSEL <= vsd_cs_i; -- ADO_TTL(18) <= '1'; -- ADO_TTL(15 downto 0) <= (others => 'Z'); +------------------------------------------------------------------------------- +-- dtu +------------------------------------------------------------------------------- -- DTU_INT: dtu_interface -- port map ( -- CLK => CLK, @@ -2124,9 +1491,12 @@ begin -- LVL2_BUSY => '0',--lvl2_busy_i, --1:1 downscaling -- LVL2_TRB_ACK => trb_ack_lvl2_i, -- DTU_DEBUG_00 => open); - ADO_TTL(15 downto 4) <= (others => 'Z'); - ADO_TTL(2) <= '0'; - ADO_TTL(3) <= '0'; +-- ADO_TTL(15 downto 4) <= (others => 'Z'); +-- ADO_TTL(2) <= '0'; +-- ADO_TTL(3) <= '0'; +------------------------------------------------------------------------------- +-- ctu +------------------------------------------------------------------------------- -- lvl2_trigger_code_i(3) <= '0';--mdc lvl2_trigger_i(1); -- ADO_TTL(15 downto 0) <= (others => 'Z'); -- CTU_INT: ctu @@ -2146,170 +1516,38 @@ begin -- CTU_CONTROL => x"0000" & fpga_register_06_i(23 downto16), --26 -- LVL1_CTU_STATUS => lvl1_ctu_status_i, -- LVL2_CTU_STATUS => lvl2_ctu_status_i); - PULSE_TO_EDGE_0: edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ADO_TTL(35), - pulse => scaler_pulse(0)); - SCALER_0: simpleupcounter_32bit - port map ( - QOUT => scaler_counter_0, - UP => scaler_pulse(0), - CLK => CLK, - CLR => external_reset_i); - PULSE_TO_EDGE_1: edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ADO_TTL(36), - pulse => scaler_pulse(1)); - SCALER_1: simpleupcounter_32bit - port map ( - QOUT => scaler_counter_1, - UP => scaler_pulse(1), - CLK => CLK, - CLR => external_reset_i); - PULSE_TO_EDGE_2: edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ADO_TTL(37), - pulse => scaler_pulse(2)); - SCALER_2: simpleupcounter_32bit - port map ( - QOUT => scaler_counter_2, - UP => scaler_pulse(2), - CLK => CLK, - CLR => external_reset_i); - PULSE_TO_EDGE_3: edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ADO_TTL(38), - pulse => scaler_pulse(3)); - SCALER_3: simpleupcounter_32bit - port map ( - QOUT => scaler_counter_3, - UP => scaler_pulse(3), - CLK => CLK, - CLR => external_reset_i); - PULSE_TO_EDGE_4: edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ADO_TTL(39), - pulse => scaler_pulse(4)); - SCALER_4: simpleupcounter_32bit - port map ( - QOUT => scaler_counter_4, - UP => scaler_pulse(4), - CLK => CLK, - CLR => external_reset_i); - PULSE_TO_EDGE_5: edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ADO_TTL(40), - pulse => scaler_pulse(5)); - SCALER_5: simpleupcounter_32bit - port map ( - QOUT => scaler_counter_5, - UP => scaler_pulse(5), - CLK => CLK, - CLR => external_reset_i); - PULSE_TO_EDGE_6: edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ADO_TTL(41), - pulse => scaler_pulse(6)); - SCALER_6: simpleupcounter_32bit - port map ( - QOUT => scaler_counter_6, - UP => scaler_pulse(6), - CLK => CLK, - CLR => external_reset_i); - PULSE_TO_EDGE_7: edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ADO_TTL(42), - pulse => scaler_pulse(7)); - SCALER_7: simpleupcounter_32bit - port map ( - QOUT => scaler_counter_7, - UP => scaler_pulse(7), - CLK => CLK, - CLR => external_reset_i); - TRIGG_WITHOUT_HAD_1: edge_to_pulse - port map ( - clock => CLK, - en_clk => '1', - signal_in => ADO_TTL(0), - pulse => generator_trigger_1); - ADO_TTL(16) <= 'Z'; --- TRIGG_WITHOUT_HAD_2: edge_to_pulse --- port map ( --- clock => CLK, --- en_clk => '1', --- signal_in => ADO_TTL(16), --- pulse => generator_trigger_2); - generator_trigger_2 <= '0'; - MAKE_LONG_LVL2_ACK: process (CLK, external_reset_i) - begin -- process MAKE_LONG_ACK - if rising_edge(CLK) then -- rising clock edge - if external_reset_i = '1' then--or trb_ack_lvl2_i ='1' then -- asynchronous reset (active low) - lvl2_counter_ack <= x"1f"; - elsif trb_ack_lvl2_i ='1' then - lvl2_counter_ack <= x"00"; - elsif lvl2_counter_ack < x"1f" then - lvl2_counter_ack <= lvl2_counter_ack + 1; - else - lvl2_counter_ack <= lvl2_counter_ack; - end if; - end if; - end process MAKE_LONG_LVL2_ACK; - LVL2_CODE_SYNCH: process (CLK, external_reset_i) +-------------------------------------------------------------------------- +-- scalers +-------------------------------------------------------------------------- + SCALER: for ttl_line in 16 to 23 generate + PULSE_TO_EDGE : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => ADO_TTL(ttl_line), + pulse => scaler_pulse(ttl_line - 16)); + SCALER : simpleupcounter_32bit + port map ( + QOUT => scaler_counter(ttl_line - 16), + UP => scaler_pulse(ttl_line - 16), + CLK => CLK, + CLR => external_reset_i); + end generate SCALER; + ADO_TTL(23 downto 16) <= (others => 'Z'); +-------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------- + ETRAX_IRQ <= '1'; + COUNTER_FOR_CLOCK_CHECK: process (CLK, external_reset_i) begin if rising_edge(CLK) then - if external_reset_i = '1' then - - lvl2_trigger_code_synch <= '0' ; - else - lvl2_trigger_code_synch <= lvl2_trigger_code_i(3); + if external_reset_i = '1' then + check_counter <= (others => '0'); + else + check_counter <= check_counter + 1; end if; end if; - end process LVL2_CODE_SYNCH; - trb_ack_lvl2_long_i <= '1' when lvl2_counter_ack < x"1f" else '0'; - - ETRAX_IRQ <= '1'; - DBAD <= lvl1_busy_i; - DGOOD <= lvl2_busy_i; - --DINT <= '1'; - DINT <= etrax_bus_busy_i; - DWAIT <= fpga_register_06_i(6); --'0'enable clock for TDC - + end process COUNTER_FOR_CLOCK_CHECK; + check_pulse <= '1' when check_counter > x"fffe" else '0'; - - - - COUNTER_FOR_CLOCK_CHECK: process (CLK, external_reset_i) - begin - if rising_edge(CLK) then - if external_reset_i = '1' then - check_counter <= (others => '0'); - else - check_counter <= check_counter + 1; - end if; - end if; - end process COUNTER_FOR_CLOCK_CHECK; - check_pulse <= '1' when check_counter > x"fffe" else '0'; - TDC_RESET <= '0';--fpga_register_06_i(5);--'0'; - VIRT_TRST <= not fpga_register_06_i(5);--'1'; - - A_TDC_POWERUP <= '1'; - B_TDC_POWERUP <= '1'; - C_TDC_POWERUP <= '1'; - D_TDC_POWERUP <= '1'; end trb_v2b_fpga;