From: Tobias Weber Date: Thu, 5 Jul 2018 13:02:05 +0000 (+0200) Subject: first version ready for synthesis. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ca1004e9ce99e52cfa3280c11370c4f4b93fe9e9;p=trb3.git first version ready for synthesis. --- diff --git a/mupix/Mupix8/sources/GrayCounter2.vhd b/mupix/Mupix8/sources/GrayCounter2.vhd index a700293..79c9c3f 100644 --- a/mupix/Mupix8/sources/GrayCounter2.vhd +++ b/mupix/Mupix8/sources/GrayCounter2.vhd @@ -3,14 +3,12 @@ -- Tobias Weber 27.06.2018 -- Ruhr University Bochum ---------------------------------------------------- - - library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -entity Graycounter is +entity Graycounter2 is generic ( COUNTWIDTH : integer := 8 ); @@ -22,7 +20,7 @@ entity Graycounter is ); end Graycounter; -architecture rtl of Graycounter is +architecture rtl of Graycounter2 is signal binary_counter : unsigned(COUNTWIDTH - 1 downto 0) := (others => '0'); signal gray_counter : std_logic_vector(COUNTWIDTH - 1 downto 0) := (others => '0'); diff --git a/mupix/Mupix8/sources/LinkSynchronizer.vhd b/mupix/Mupix8/sources/LinkSynchronizer.vhd index c90aff6..dde4142 100644 --- a/mupix/Mupix8/sources/LinkSynchronizer.vhd +++ b/mupix/Mupix8/sources/LinkSynchronizer.vhd @@ -12,13 +12,14 @@ entity LinkSynchronizer is generic ( clk_speed : integer := 8); -- clk speed in ns port ( - clk_in : in std_logic; -- clk in synchronous to serdes rx clock - reset_in : in std_logic; -- reset - comma_in : in std_logic; -- comma word detected by serdes - cverr_in : in std_logic; -- serdes data error in - link_sync_out : out std_logic; -- realign to link out pulse low to high to start word alignminment - link_sync_flag : out std_logic; -- link is synchronous - comma_counter_out : out std_logic_vector(15 downto 0)); -- comma word counter + clk_in : in std_logic; -- clk in synchronous to serdes rx clock + reset_in : in std_logic; -- reset + comma_in : in std_logic; -- comma word detected by serdes + cverr_in : in std_logic; -- serdes data error in + link_sync_out : out std_logic; -- realign to link out pulse low to high to start word alignminment + link_sync_flag : out std_logic; -- link is synchronous + comma_counter_gray : out std_logic_vector(31 downto 0); -- comma word gray count + comma_counter_out : out std_logic_vector(31 downto 0)); -- comma word counter end entity LinkSynchronizer; architecture rtl of LinkSynchronizer is @@ -30,13 +31,36 @@ architecture rtl of LinkSynchronizer is signal sync_fsm : sync_state_type := idle; signal look_counter : integer range 0 to look_counter_max - 1 := 0; - signal comma_counter : integer range 0 to 2**16 - 1 := 0; + signal comma_counter : integer range 0 to 2**32 - 1 := 0; signal look_enable : std_logic := '0'; signal comma_seen : std_logic := '0'; signal link_sync_i : std_logic := '0'; + signal inc_en_i : std_logic; + + component Graycounter2 is + generic ( + COUNTWIDTH : integer); + port ( + clk : in std_logic; + reset : in std_logic; + inc_en : in std_logic; + counter : out std_logic_vector(COUNTWIDTH - 1 downto 0)); + end component Graycounter2; + begin -- architecture rtl + inc_en_i <= '1' when comma_in = '1' and cverr_in = '0' else '0'; + + Graycounter2_1: entity work.Graycounter2 + generic map ( + COUNTWIDTH => 32) + port map ( + clk => clk_in, + reset => reset_in, + inc_en => inc_en_i, + counter => comma_counter_gray); + counter_proc : process (clk_in) is begin -- process counter_proc if rising_edge(clk_in) then @@ -85,7 +109,7 @@ begin -- architecture rtl end if; when sync => link_sync_flag <= '1'; - sync_fsm <= sync; + sync_fsm <= sync; if look_enable = '1' then if comma_seen = '0' then sync_fsm <= notsync; @@ -95,7 +119,7 @@ begin -- architecture rtl end if; when notsync => link_sync_flag <= '0'; - sync_fsm <= notsync; + sync_fsm <= notsync; if look_enable = '1' then if comma_seen = '1' then sync_fsm <= sync; diff --git a/mupix/Mupix8/sources/MuPixDataLink_new.vhd b/mupix/Mupix8/sources/MuPixDataLink_new.vhd index b46066a..08bfea7 100644 --- a/mupix/Mupix8/sources/MuPixDataLink_new.vhd +++ b/mupix/Mupix8/sources/MuPixDataLink_new.vhd @@ -144,32 +144,44 @@ architecture rtl of MupixDataLinkWithUnpacker is g_countersize : integer := 32 ); port( - clk : in std_logic; - reset : in std_logic; - data_in : in std_logic_vector(7 downto 0); - komma : in std_logic; - valid : in std_logic; - hit_out : out std_logic_vector(g_hitsize - 1 downto 0); - hit_enable : out std_logic; - coarsecounter : out std_logic_vector(g_countersize - 1 downto 0); - counter_enable : out std_logic; - link_flag : out std_logic; - errorcounter : out std_logic_vector(31 downto 0)); + clk : in std_logic; + reset : in std_logic; + data_in : in std_logic_vector(7 downto 0); + komma : in std_logic; + valid : in std_logic; + hit_out : out std_logic_vector(g_hitsize - 1 downto 0); + hit_enable : out std_logic; + coarsecounter : out std_logic_vector(g_countersize - 1 downto 0); + counter_enable : out std_logic; + link_flag : out std_logic; + errorcounter_gray : out std_logic_vector(31 downto 0); + errorcounter : out std_logic_vector(31 downto 0)); end component MupixUnpacker; component LinkSynchronizer generic ( clk_speed : integer := 8); port ( - clk_in : in std_logic; - reset_in : in std_logic; - comma_in : in std_logic; - cverr_in : in std_logic; - link_sync_out : out std_logic; - link_sync_flag : out std_logic; - comma_counter_out : out std_logic_vector(15 downto 0)); + clk_in : in std_logic; + reset_in : in std_logic; + comma_in : in std_logic; + cverr_in : in std_logic; + link_sync_out : out std_logic; + link_sync_flag : out std_logic; + comma_counter_gray : out std_logic_vector(31 downto 0); + comma_counter_out : out std_logic_vector(31 downto 0)); end component LinkSynchronizer; + component Graycounter2 is + generic ( + COUNTWIDTH : integer); + port ( + clk : in std_logic; + reset : in std_logic; + inc_en : in std_logic; + counter : out std_logic_vector(COUNTWIDTH - 1 downto 0)); + end component Graycounter2; + constant ch_powerup_i : std_logic_vector(3 downto 0) := "1111"; -- change to powerdown unused channels constant ch_divmode_i : std_logic_vector(3 downto 0) := "0000"; -- use half rx clock speed @@ -184,8 +196,14 @@ architecture rtl of MupixDataLinkWithUnpacker is signal rx_cdr_i : std_logic_vector(3 downto 0); -- clock recovery failure -- synced signals - signal rx_cdr_sync : std_logic_vector(3 downto 0); - signal rx_sig_lost_sync : std_logic_vector(3 downto 0); + signal rx_cdr_sync : std_logic_vector(3 downto 0); + signal rx_sig_lost_sync : std_logic_vector(3 downto 0); + signal rx_disp_err_sync : std_logic_vector(3 downto 0); + signal rx_dataerror_sync : std_logic_vector(3 downto 0); + signal rx_data_sync : std_logic_vector(4*8 - 1 downto 0); + signal rx_komma_sync : std_logic_vector(3 downto 0); + signal rx_disp_err_sync : std_logic_vector(3 downto 0); + signal rx_dataerror_sync : std_logic_vector(3 downto 0); -- fifo signals signal fifo_data_oi : std_logic_vector(c_links*c_mupixhitsize - 1 downto 0); @@ -204,13 +222,18 @@ architecture rtl of MupixDataLinkWithUnpacker is signal unpacker_error_counter : t_counter_array(0 to 3) := (others => (others => '0')); -- link synchronizer signals - signal link_sync_out_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); signal link_sync_flag_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); signal komma_counter : t_counter_array(0 to 3) := (others => (others => '0')); -- unpacker signals signal unpacker_valid_i : std_logic_vector(c_links - 1 downto 0) := (others => '0'); + -- slow control resets + signal reset_counters_i : std_logic := '0'; + signal reset_quad_i : std_logic := '0'; + signal reset_serdes_i : std_logic := '1'; + signal reset_fifos_i : std_logic := '0'; + begin gen_receive_clock_rec : if useRecoveredClock = c_Yes generate @@ -287,27 +310,62 @@ begin rx_cdr_lol_ch3_s => rx_cdr_i(3), rx_div2_mode_ch3_c => ch_divmode_i(2), fpga_txrefclk => dataclk, - tx_sync_qd_c => '0', + tx_sync_qd_c => '0', -- serializer reset (not needed for receiving) refclk2fpga => open, - rst_n => '1', - serdes_rst_qd_c => clear); + rst_n => reset_serdes_i, -- reset all channels including PCS (active + -- low, not documented in maunal -> consult + -- vhdl code) + serdes_rst_qd_c => clear_quad_i); -- reset all serdes channels but not PCS (active high) + + -- synchronize rx data signals into receive clock domain (maybe not + -- necessary, but should not do any harm) + rx_komma_s : InputSynchronizer + generic map (depth => 2, width => 4) + port map (clk => clkrx, rst => rst, input => rx_komma_i, sync_output => rx_komma_sync); + + rx_disp_err_s : InputSynchronizer + generic map (depth => 2, width => 4) + port map (clk => clkrx, rst => rst, input => rx_disp_err_i, sync_output => rx_disp_err_sync); + + rx_dataerror_s : InputSynchronizer + generic map (depth => 2, width => 4) + port map (clk => clkrx, rst => rst, input => rx_dataerror_i, sync_output => rx_dataerror_sync); + + rx_data_gen : for i in 0 to 3 generate + rx_data_s : InputSynchronizer + generic map (depth => 2, width => 8) + port map (clk => clkrx, rst => rst, + input => rx_data_i((i + 1)*8 - 1 downto i*8), + sync_output => rx_data_sync((i + 1)*8 - 1 downto i*8)) + end generate rx_data_s; + + -- synchronize status signals into trb clock domain + sync_los_low : InputSynchronizer + generic map(depth => 2, width => 4) + port map(clk => sysclk, rst => rst, input => rx_sig_lost_i, sync_output => rx_sig_lost_sync); + + sync_cdr_lol : InputSynchronizer + generic map(depth => 2, width => 4) + port map(clk => sysclk, rst => rst, input => rx_cdr_i, sync_output => rx_cdr_sync); + -- component to generate sync signal to serdes based on comma word detection generate_synchronizer : for j in 0 to c_links - 1 generate entity work.LinkSynchronizer generic map ( clk_speed => 8) port map ( - clk_in => clkrx, - reset_in => rst, - comma_in => rx_komma_i(j), - cverr_in => rx_dataerror_i(j), - link_sync_out => link_sync_out_i(j), - link_sync_flag => link_sync_flag_i(j), - comma_counter_out => komma_counter(j)); + clk_in => clkrx, + reset_in => rst, + comma_in => rx_komma_sync(j), + cverr_in => rx_dataerror_sync(j), + link_sync_out => align_en_i(j), + link_sync_flag => link_sync_flag_i(j), + comma_counter_gray => std_logic_vector(komma_counter(j)), + comma_counter_out => open); end generate generate_synchronizer; - unpacker_valid_i <= not rx_dataerror_i; - + -- unpacker for mupix data from serdes data stream + unpacker_valid_i <= not rx_dataerror_sync and link_sync_flag_i; generate_unpacker : for j in 0 to c_links - 1 generate entity work.MupixUnpacker generic map ( @@ -316,15 +374,16 @@ begin port map ( clk => clkrx, reset => rst, - data_in => rx_data_i((j + 1)*8 - 1 downto j*8), - komma => rx_komma_i(j), + data_in => rx_data_sync((j + 1)*8 - 1 downto j*8), + komma => rx_komma_sync(j), valid => unpacker_valid_i(j), hit_out => fifo_data_ii((j + 1)*c_mupixhitsize downto j*c_mupixhitsize), hit_enable => fifo_wren_i(j), coarsecounter => open, counter_enable => open, link_flag => open, - errorcounter => unpacker_error_counter(j)); + errorcounter_gray => unpacker_error_counter(j) + errorcounter => open); end generate generate_fifo; generate_fifo : for j in 0 to c_links - 1 generate @@ -335,20 +394,108 @@ begin RdClock => sysclk, WrEn => fifo_wren_i(j), RdEn => fifo_rden_i(j), - Reset => rst, - RPReset => rst, + Reset => reset_fifos_i, + RPReset => reset_fifos_i, Q => fifo_data_oi((j + 1)*c_mupixhitsize downto j*c_mupixhitsize), RCNT => fifo_readcnt_i((j + 1)*fifo_depth - 1 downto j*fifo_depth), Empty => fifo_empty_i(j), Full => fifo_full_i(j)); end generate generate_fifo; - sync_los_low : InputSynchronizer - generic map(depth => 2, width => 4) - port map(clk => sysclk, rst => rst, input => rx_sig_lost_i, sync_output => rx_sig_lost_sync); + -- error counters (using gray counters because of possible clock domain + -- crossing to trb clock) + disp_err_cnt_gen : for i in 0 to 3 generate + disp_err_cnt : Graycounter2 + generic map (COUNTWIDTH => 32) + port map ( + clk => clkrx, + reset => rst, + inc_en => rx_disp_err_sync(i), + counter => std_logic_vector(disp_error_counter(i))) + end generate disp_err_cnt; - sync_cdr_lol : InputSynchronizer - generic map(depth => 2, width => 4) - port map(clk => sysclk, rst => rst, input => rx_cdr_i, sync_output => rx_cdr_sync); + data_err_cnt_gen : for i in 0 to 3 generate + data_err_cnt : Graycounter2 + generic map (COUNTWIDTH => 32) + port map ( + clk => clkrx, + reset => rst, + inc_en => rx_dataerror_sync(i), + counter => std_logic_vector(data_error_counter(i))) + end generate data_error_cnt_gen; + + -- purpose: slow control of data link + slowcontrol_proc : process (sysclk) is + begin -- process slowcontrol_proc + if rising_edge(sysclk) then -- rising clock edge + if rst = '1' then -- synchronous reset (active low) + slv_data_out <= (others => '0'); + slv_ack_out <= '0'; + slv_no_more_data_out <= '0'; + slv_unknown_addr_out <= '0'; + serdes_channel_select <= 0; + else + slv_data_out <= (others => '0'); + slv_ack_out <= '0'; + slv_no_more_data_out <= '0'; + slv_unknown_addr_out <= '0'; + reset_counters_i <= '0'; + reset_serdes_i <= '1'; --active low + clear_quad_i <= '0'; + reset_fifos_i <= '0'; + if slv_write_in = '1' then + case slv_addr_in is + when x"0160" => + slv_ack_out <= '1'; + reset_counters_i <= slv_data_in(0); + when x"0161" => + slv_ack_out <= '1'; + reset_quad_i <= slv_data_in(0); + when x"0162" => + slv_ack_out <= '1'; + reset_serdes_i <= slv_data_in(0); -- active low + when x"0163" => + slv_ack_out <= '1'; + reset_fifos_i <= slv_data_in(0); + when x"0164" => + slv_ack_out <= '1'; + serdes_channel_select <= to_integer(unsigned(slv_data_in(1 downto 0))); + when others => + slv_unknown_addr_out <= '1'; + end case; + elsif slv_read_in = '1' then + case slv_addr_in is + when x"0164" => + slv_ack_out <= '1'; + slv_data_out(1 downto 0) <= std_logic_vector(to_unsigned(serdes_channel_select, 2)); + when x"0165" => + slv_ack_out <= '1'; + slv_data_out <= disp_error_counter(serdes_channel_select); + when x"0166" => + slv_ack_out <= '1'; + slv_data_out <= data_error_counter(serdes_channel_select); + when x"0167" => + slv_ack_out <= '1'; + slv_data_out <= unpacker_error_counter(serdes_channel_select); + when x"0168" => + slv_ack_out <= '1'; + slv_data_out <= komma_counter(serdes_channel_select); + when x"0169" => + slv_ack_out <= '1'; + slv_data_out <= fifo_readcnt_i((serdes_channel_select + 1)*fifo_depth - 1 downto serdes_channel_select*fifo_depth); + when x"016a" => + slv_ack_out <= '1'; + slv_data_out(4 downto 0) <= rx_disp_err_sync(serdes_channel_select) + & rx_dataerror_sync(serdes_channel_select) + & rx_cdr_sync(serdes_channel_select) + & rx_sig_lost_sync(serdes_channel_select) + & link_sync_flag_i(serdes_channel_select); + when others => + slv_unknown_addr_out <= '1'; + end case; + end if; + end if; + end if; + end process slowcontrol_proc; -end architecture; + end architecture; diff --git a/mupix/Mupix8/sources/MuPixUnpacker.vhd b/mupix/Mupix8/sources/MuPixUnpacker.vhd index b628e51..3ae0c2a 100644 --- a/mupix/Mupix8/sources/MuPixUnpacker.vhd +++ b/mupix/Mupix8/sources/MuPixUnpacker.vhd @@ -13,17 +13,18 @@ entity MupixUnpacker is g_countersize : integer := 32 ); port( - clk : in std_logic; -- clk input - reset : in std_logic; -- reset input - data_in : in std_logic_vector(7 downto 0); -- 10b8b decoded data - komma : in std_logic; -- komma word indicator - valid : in std_logic; -- incoming data valid - hit_out : out std_logic_vector(g_hitsize - 1 downto 0); -- mupix 8 word output - hit_enable : out std_logic; -- new hit word - coarsecounter : out std_logic_vector(g_countersize - 1 downto 0); --coarsecounter output - counter_enable : out std_logic; -- new counter value - link_flag : out std_logic; -- link flag - errorcounter : out std_logic_vector(31 downto 0)); -- error counter + clk : in std_logic; -- clk input + reset : in std_logic; -- reset input + data_in : in std_logic_vector(7 downto 0); -- 10b8b decoded data + komma : in std_logic; -- komma word indicator + valid : in std_logic; -- incoming data valid + hit_out : out std_logic_vector(g_hitsize - 1 downto 0); -- mupix 8 word output + hit_enable : out std_logic; -- new hit word + coarsecounter : out std_logic_vector(g_countersize - 1 downto 0); --coarsecounter output + counter_enable : out std_logic; -- new counter value + link_flag : out std_logic; -- link flag + errorcounter_gray : out std_logic_vector(31 downto 0); -- error counter gray code + errorcounter : out std_logic_vector(31 downto 0)); -- error counter end entity MupixUnpacker; architecture RTL of MupixUnpacker is @@ -43,10 +44,28 @@ architecture RTL of MupixUnpacker is signal hit_reg : std_logic; signal link_flag_reg : std_logic; -begin + component Graycounter2 is + generic ( + COUNTWIDTH : integer); + port ( + clk : in std_logic; + reset : in std_logic; + inc_en : in std_logic; + counter : out std_logic_vector(COUNTWIDTH - 1 downto 0)); + end component Graycounter2; + signal inc_en_i : std_logic; +begin errorcounter <= std_logic_vector(errorcounter_i); + Graycounter2_1 : entity work.Graycounter2 + generic map ( + COUNTWIDTH => 32) + port map ( + clk => clk_in, + reset => reset_in, + inc_en => inc_en_i, + counter => errorcounter_gray); unpacker_proc : process (clk, reset) is begin -- process unpacker_proc @@ -74,6 +93,7 @@ begin link_flag_reg <= '0'; coarse_reg <= '0'; hit_reg <= '0'; + inc_en_i <= '0'; hit_enable <= hit_reg or coarse_reg; counter_enable <= coarse_reg; link_flag <= link_flag_reg; @@ -163,6 +183,7 @@ begin when receive_err => errorcounter_i <= errorcounter_i + 1; + inc_en_i <= '1'; if komma = '1' and data_in = k28_5 then unpacker_state <= idle; else diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd index 1fa2ea1..5f5579b 100644 --- a/mupix/Mupix8/sources/MupixBoard.vhd +++ b/mupix/Mupix8/sources/MupixBoard.vhd @@ -17,36 +17,36 @@ use wirk.Constants.all; entity MupixBoard8 is port( --Clock signal - clk : in std_logic; --trb system clock for slow control - fast_clk : in std_logic; --200 MHz clock for hitbus sampling - data_clk : in std_logic; --mupix clock - reset : in std_logic; --reset input - + clk : in std_logic; --trb system clock for slow control + fast_clk : in std_logic; --200 MHz clock for hitbus sampling + data_clk : in std_logic; --mupix clock + reset : in std_logic; --reset input + --slow control signals - testpulse : out std_logic; --generate injection pulse - ctrl_din : out std_logic; --serial data to mupix - ctrl_clk1 : out std_logic; --slow control clk1 - ctrl_clk2 : out std_logic; --slow control clk2 - ctrl_ld : out std_logic; --slow control load latched data - ctrl_dout : in std_logic; --serial data from mupix - ctrl_rb : out std_logic; --slow control readback - spi_dout_adc : in std_logic; --adc serial data from board - spi_dout_dac : in std_logic; --dac serial data from board - dac4_dout : in std_logic; --serial data in from threshold dac - spi_clk : out std_logic; --serial clock - spi_din : out std_logic; --serial data out - spi_ld_tmp_dac : out std_logic; --load temperature dac - spi_cs_adc : out std_logic; --load adc - spi_ld_thres : out std_logic; --load threshold and injection dac - hitbus : in std_logic; --hitbus signal - - mupix_data : in std_logic_vector(7 downto 0); --serdes data link from mupix - channel_status_led : out std_logic_vector(3 downto 0); --status leds of serdes connection - + testpulse : out std_logic; --generate injection pulse + ctrl_din : out std_logic; --serial data to mupix + ctrl_clk1 : out std_logic; --slow control clk1 + ctrl_clk2 : out std_logic; --slow control clk2 + ctrl_ld : out std_logic; --slow control load latched data + ctrl_dout : in std_logic; --serial data from mupix + ctrl_rb : out std_logic; --slow control readback + spi_dout_adc : in std_logic; --adc serial data from board + spi_dout_dac : in std_logic; --dac serial data from board + dac4_dout : in std_logic; --serial data in from threshold dac + spi_clk : out std_logic; --serial clock + spi_din : out std_logic; --serial data out + spi_ld_tmp_dac : out std_logic; --load temperature dac + spi_cs_adc : out std_logic; --load adc + spi_ld_thres : out std_logic; --load threshold and injection dac + hitbus : in std_logic; --hitbus signal + + mupix_data : in std_logic_vector(7 downto 0); --serdes data link from mupix + channel_status_led : out std_logic_vector(3 downto 0); --status leds of serdes connection + --resets timestampreset_in : in std_logic; --time stamp reset eventcounterreset_in : in std_logic; --event number reset - + --TRB trigger connections TIMING_TRG_IN : in std_logic; LVL1_TRG_DATA_VALID_IN : in std_logic; @@ -67,7 +67,7 @@ entity MupixBoard8 is FEE_DATA_FINISHED_OUT : out std_logic; FEE_DATA_ALMOST_FULL_IN : in std_logic; - --TRB slow control connections + --TRB slow control connections REGIO_ADDR_IN : in std_logic_vector(15 downto 0); REGIO_DATA_IN : in std_logic_vector(31 downto 0); REGIO_DATA_OUT : out std_logic_vector(31 downto 0); @@ -84,208 +84,208 @@ end MupixBoard8; architecture Behavioral of MupixBoard8 is - component MupixBoardInterface - port( - clk_in : in std_logic; - fast_clk_in : in std_logic; - reset : in std_logic; - --input signals from mupix sensorboard - ctrl_dout : in std_logic; --serial data from mupix - spi_dout_adc : in std_logic; --adc serial data from board - spi_dout_dac : in std_logic; --dac serial data from board - dac4_dout : in std_logic; --serial data in from dac 4?? - hitbus : in std_logic; --hitbus signal - hit : in std_logic; --hit signal (replacement for priout?) - trigger : in std_logic; --external trigger - --synchronized signals to FPGA logic - ctrl_dout_sync : out std_logic; - spi_dout_adc_sync : out std_logic; - spi_dout_dac_sync : out std_logic; - dac4_dout_sync : out std_logic; - hitbus_sync : out std_logic; - trigger_sync : out std_logic; - hitbus_sync_fast : out std_logic; --sampled with 200 MHz clock - trigger_sync_fast : out std_logic; --sampled with 200 MHz clock - hit_sync : out std_logic); - end component MupixBoardInterface; - - signal ctrl_dout_sync : std_logic; - signal spi_dout_adc_sync : std_logic; - signal spi_dout_dac_sync : std_logic; - signal dac4_dout_sync : std_logic; - signal hitbus_sync : std_logic; - signal trigger_sync : std_logic; - signal hitbus_sync_fast : std_logic; --sampled with 200 MHz clock - signal trigger_sync_fast : std_logic; --sampled with 200 MHz clock - signal hit_sync : std_logic; - - signal testpulse_i : std_logic; - signal spi_clk_i : std_logic; - signal spi_din_i : std_logic; - signal spi_ld_tmp_dac_i : std_logic; - signal spi_cs_adc_i : std_logic; - signal spi_ld_thres_i : std_logic; - - component HitbusHistogram - generic( - HistogramRange : integer; - PostOscillationWaitCycles : integer); - port( - clk : in std_logic; - hitbus : in std_logic; - trigger : in std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic - ); - end component HitbusHistogram; - - component PixelControl - generic( - fpga_clk_speed : integer; - spi_clk_speed : integer - ); - port( - clk : in std_logic; --clock - reset : in std_logic; --reset - --mupix control - mupixslctrl : out MupixSlowControl; - ctrl_dout : in std_logic; --serial data from mupix - --TRB slow control - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic); - end component PixelControl; - - constant fpga_clk_speed : integer := 1e8; --100 MHz - constant mupix_spi_clk_speed : integer := 5e4;--50 kHz - signal mupixslctrl_i : MupixSlowControl; - - component MupixBoardDAC is - port( - clk : in std_logic; --clock - reset : in std_logic; --reset - --DAC signals - spi_dout_dac : in std_logic; --dac serial data from board - dac4_dout : in std_logic; --serial data in from threshold dac - spi_dout_adc : in std_logic; --adc serial data from board - spi_clk : out std_logic; --serial clock - spi_din : out std_logic; --serial data out - spi_ld_tmp_dac : out std_logic; --load temperature dac - spi_ld_thres : out std_logic; --load threshold and injection dac - spi_cs_adc : out std_logic; --load adc - injection_pulse : out std_logic; --injection pulse to board - --TRB slow control - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic); - end component MupixBoardDAC; - - component MupixTRBReadout - generic( - g_mupix_links : natural := 4; - g_cyc_mem_address_width : integer := 13; - g_datawidthfifo : integer := 40; - g_datawidthtrb : integer := 32 - ); - port( - clk : in std_logic; - rst : in std_logic; - fifo_empty : in std_logic_vector(g_mupix_links - 1 downto 0); - fifo_full : in std_logic_vector(g_mupix_links - 1 downto 0); - fifo_datain : in std_logic_vector(g_mupix_links*g_datawidth - 1 downto 0); - fifo_rden : out std_logic_vector(g_mupix_links - 1 downto 0); - trb_trigger : in std_logic; - dataout : out std_logic_vector(g_datawidth - 1 downto 0); - data_valid : out std_logic; - busy : out std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic - ); - end component MupixTRBReadout; - - component TriggerHandler - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - TIMING_TRIGGER_IN : in std_logic; - LVL1_TRG_DATA_VALID_IN : in std_logic; - LVL1_VALID_TIMING_TRG_IN : in std_logic; - LVL1_VALID_NOTIMING_TRG_IN : in std_logic; - LVL1_INVALID_TRG_IN : in std_logic; - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - FEE_DATA_OUT : out std_logic_vector(31 downto 0); - FEE_DATA_WRITE_OUT : out std_logic; - FEE_DATA_FINISHED_OUT : out std_logic; - FEE_TRG_RELEASE_OUT : out std_logic; - FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); - FEE_DATA_0_IN : in std_logic_vector(31 downto 0); - FEE_DATA_WRITE_0_IN : in std_logic; - TRIGGER_BUSY_BUFFER_READ_IN : in std_logic; - VALID_TRIGGER_OUT : out std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic - ); - end component TriggerHandler; - - component FrameGeneratorMux - generic( - FIFODEPTH : positive; - DATAWIDTH : natural - ); - port( - clk : in std_logic; - reset : in std_logic; - serdes_data : in std_logic_vector(4*DATAWIDTH - 1 downto 0); - serdes_fifo_full : in std_logic_vector(3 downto 0); - serdes_fifo_empty : in std_logic_vector(3 downto 0); - in_rden : in std_logic_vector(3 downto 0); - serdes_fifo_rden : out std_logic_vector(3 downto 0); - out_data : out std_logic_vector(4*DATAWIDTH - 1 downto 0); - out_fifo_full : out std_logic_vector(3 downto 0); - out_fifo_empty : out std_logic_vector(3 downto 0); - --TRB slow control - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic - ); - end component FrameGeneratorMux; - - component MupixDataLink is + component MupixBoardInterface + port( + clk_in : in std_logic; + fast_clk_in : in std_logic; + reset : in std_logic; + --input signals from mupix sensorboard + ctrl_dout : in std_logic; --serial data from mupix + spi_dout_adc : in std_logic; --adc serial data from board + spi_dout_dac : in std_logic; --dac serial data from board + dac4_dout : in std_logic; --serial data in from dac 4?? + hitbus : in std_logic; --hitbus signal + hit : in std_logic; --hit signal (replacement for priout?) + trigger : in std_logic; --external trigger + --synchronized signals to FPGA logic + ctrl_dout_sync : out std_logic; + spi_dout_adc_sync : out std_logic; + spi_dout_dac_sync : out std_logic; + dac4_dout_sync : out std_logic; + hitbus_sync : out std_logic; + trigger_sync : out std_logic; + hitbus_sync_fast : out std_logic; --sampled with 200 MHz clock + trigger_sync_fast : out std_logic; --sampled with 200 MHz clock + hit_sync : out std_logic); + end component MupixBoardInterface; + + signal ctrl_dout_sync : std_logic; + signal spi_dout_adc_sync : std_logic; + signal spi_dout_dac_sync : std_logic; + signal dac4_dout_sync : std_logic; + signal hitbus_sync : std_logic; + signal trigger_sync : std_logic; + signal hitbus_sync_fast : std_logic; --sampled with 200 MHz clock + signal trigger_sync_fast : std_logic; --sampled with 200 MHz clock + signal hit_sync : std_logic; + + signal testpulse_i : std_logic; + signal spi_clk_i : std_logic; + signal spi_din_i : std_logic; + signal spi_ld_tmp_dac_i : std_logic; + signal spi_cs_adc_i : std_logic; + signal spi_ld_thres_i : std_logic; + + component HitbusHistogram + generic( + HistogramRange : integer; + PostOscillationWaitCycles : integer); + port( + clk : in std_logic; + hitbus : in std_logic; + trigger : in std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); + end component HitbusHistogram; + + component PixelControl + generic( + fpga_clk_speed : integer; + spi_clk_speed : integer + ); + port( + clk : in std_logic; --clock + reset : in std_logic; --reset + --mupix control + mupixslctrl : out MupixSlowControl; + ctrl_dout : in std_logic; --serial data from mupix + --TRB slow control + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic); + end component PixelControl; + + constant fpga_clk_speed : integer := 1e8; --100 MHz + constant mupix_spi_clk_speed : integer := 5e4; --50 kHz + signal mupixslctrl_i : MupixSlowControl; + + component MupixBoardDAC is + port( + clk : in std_logic; --clock + reset : in std_logic; --reset + --DAC signals + spi_dout_dac : in std_logic; --dac serial data from board + dac4_dout : in std_logic; --serial data in from threshold dac + spi_dout_adc : in std_logic; --adc serial data from board + spi_clk : out std_logic; --serial clock + spi_din : out std_logic; --serial data out + spi_ld_tmp_dac : out std_logic; --load temperature dac + spi_ld_thres : out std_logic; --load threshold and injection dac + spi_cs_adc : out std_logic; --load adc + injection_pulse : out std_logic; --injection pulse to board + --TRB slow control + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic); + end component MupixBoardDAC; + + component MupixTRBReadout + generic( + g_mupix_links : natural := 4; + g_cyc_mem_address_width : integer := 13; + g_datawidthfifo : integer := 40; + g_datawidthtrb : integer := 32 + ); + port( + clk : in std_logic; + rst : in std_logic; + fifo_empty : in std_logic_vector(g_mupix_links - 1 downto 0); + fifo_full : in std_logic_vector(g_mupix_links - 1 downto 0); + fifo_datain : in std_logic_vector(g_mupix_links*g_datawidth - 1 downto 0); + fifo_rden : out std_logic_vector(g_mupix_links - 1 downto 0); + trb_trigger : in std_logic; + dataout : out std_logic_vector(g_datawidth - 1 downto 0); + data_valid : out std_logic; + busy : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); + end component MupixTRBReadout; + + component TriggerHandler + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TIMING_TRIGGER_IN : in std_logic; + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_VALID_TIMING_TRG_IN : in std_logic; + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; + LVL1_INVALID_TRG_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_FINISHED_OUT : out std_logic; + FEE_TRG_RELEASE_OUT : out std_logic; + FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_0_IN : in std_logic_vector(31 downto 0); + FEE_DATA_WRITE_0_IN : in std_logic; + TRIGGER_BUSY_BUFFER_READ_IN : in std_logic; + VALID_TRIGGER_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); + end component TriggerHandler; + + component FrameGeneratorMux + generic( + FIFODEPTH : positive; + DATAWIDTH : natural + ); + port( + clk : in std_logic; + reset : in std_logic; + serdes_data : in std_logic_vector(4*DATAWIDTH - 1 downto 0); + serdes_fifo_full : in std_logic_vector(3 downto 0); + serdes_fifo_empty : in std_logic_vector(3 downto 0); + in_rden : in std_logic_vector(3 downto 0); + serdes_fifo_rden : out std_logic_vector(3 downto 0); + out_data : out std_logic_vector(4*DATAWIDTH - 1 downto 0); + out_fifo_full : out std_logic_vector(3 downto 0); + out_fifo_empty : out std_logic_vector(3 downto 0); + --TRB slow control + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); + end component FrameGeneratorMux; + + component MupixDataLink is port( sysclk : in std_logic; dataclk : in std_logic; @@ -311,12 +311,12 @@ architecture Behavioral of MupixBoard8 is SLV_UNKNOWN_ADDR_OUT : out std_logic); end component MupixDataLink; - constant FIFO_DEPTH : positive := 256; --size of pseudo data generator fifos + constant FIFO_DEPTH : positive := 256; --size of pseudo data generator fifos - signal mux_fifo_data : std_logic_vector(c_mupixhitsize*c_links downto 0); - signal mux_fifo_full : std_logic_vector(c_links - 1 downto 0); - signal mux_fifo_empty : std_logic_vector(c_links - 1 downto 0); - signal mux_fifo_rden : std_logic_vector(c_links - 1 downto 0); + signal mux_fifo_data : std_logic_vector(c_mupixhitsize*c_links - 1 downto 0); + signal mux_fifo_full : std_logic_vector(c_links - 1 downto 0); + signal mux_fifo_empty : std_logic_vector(c_links - 1 downto 0); + signal mux_fifo_rden : std_logic_vector(c_links - 1 downto 0); --signal declarations -- Bus Handler @@ -335,7 +335,7 @@ architecture Behavioral of MupixBoard8 is signal mupixreadout_busy_i : std_logic; signal mupixdata_valid_i : std_logic; signal mupixdata_i : std_logic_vector(31 downto 0); - + --connections between mupix data fifos and mupix board signal fifo_rden_serdes_i : std_logic_vector(c_links - 1 downto 0); signal fifo_empty_serdes_i : std_logic_vector(c_links - 1 downto 0); @@ -353,24 +353,24 @@ begin -- Behavioral PORT_NUMBER => NUM_PORTS, PORT_ADDRESSES => ( - 0 => x"0070", -- Hitbus Histograms - 1 => x"0080", -- Mupix DAC and Pixel Control - 2 => x"0090", -- Board Control - 3 => x"0100", -- mupix readout - 4 => x"0120", -- trigger handler - 5 => x"0140", -- hit generator - 6 => x"0160", -- mupix serdes - others => x"0000"), - PORT_ADDR_MASK => ( - 0 => 4, -- HitBus Histograms - 1 => 4, -- Mupix DAC and Pixel Control - 2 => 4, -- Board Control - 3 => 4, -- mupix readout - 4 => 4, -- trigger handler - 5 => 4, -- hit generator - 6 => 4, -- mupix serdes - others => 0) - --PORT_MASK_ENABLE => 1 + 0 => x"0070", -- Hitbus Histograms + 1 => x"0080", -- Mupix DAC and Pixel Control + 2 => x"0090", -- Board Control + 3 => x"0100", -- mupix readout + 4 => x"0120", -- trigger handler + 5 => x"0140", -- hit generator + 6 => x"0160", -- mupix serdes + others => x"0000"), + PORT_ADDR_MASK => ( + 0 => 4, -- HitBus Histograms + 1 => 4, -- Mupix DAC and Pixel Control + 2 => 4, -- Board Control + 3 => 4, -- mupix readout + 4 => 4, -- trigger handler + 5 => 4, -- hit generator + 6 => 4, -- mupix serdes + others => 0) + --PORT_MASK_ENABLE => 1 ) port map( CLK => CLK, @@ -402,230 +402,230 @@ begin -- Behavioral -- DEBUG STAT_DEBUG => open ); - - mupixboardinterface_1 : entity work.MupixBoardInterface - port map( - clk_in => clk, - fast_clk_in => fast_clk, - reset => reset, - ctrl_dout => ctrl_dout, - spi_dout_adc => spi_dout_adc, - spi_dout_dac => spi_dout_dac, - dac4_dout => dac4_dout, - hitbus => hitbus, - hit => '0', - trigger => '0', - ctrl_dout_sync => ctrl_dout_sync, - spi_dout_adc_sync => spi_dout_adc_sync, - spi_dout_dac_sync => spi_dout_dac_sync, - dac4_dout_sync => dac4_dout_sync, - hitbus_sync => hitbus_sync, - trigger_sync => trigger_sync, - hitbus_sync_fast => hitbus_sync_fast, - trigger_sync_fast => trigger_sync_fast, - hit_sync => hit_sync - ); - - hitbushistogram_1 : entity work.HitbusHistogram - generic map( - HistogramRange => 10, - PostOscillationWaitCycles => 5 - ) - port map( - clk => clk, - hitbus => hitbus_sync, - trigger => trigger_sync, - SLV_READ_IN => slv_read(0), - SLV_WRITE_IN => slv_write(0), - SLV_DATA_OUT => slv_data_rd(0*32 + 31 downto 0*32), - SLV_DATA_IN => slv_data_wr(0*32 + 31 downto 0*32), - SLV_ADDR_IN => slv_addr(0*16 + 15 downto 0*16), - SLV_ACK_OUT => slv_ack(0), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(0), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0) - ); - - pixelcontrol_1 : entity work.PixelControl - generic map( - fpga_clk_speed => fpga_clk_speed, - spi_clk_speed => mupix_spi_clk_speed - ) - port map( - clk => clk, - reset => reset, - mupixslctrl => mupixslctrl_i, - ctrl_dout => ctrl_dout_sync, - SLV_READ_IN => slv_read(1), - SLV_WRITE_IN => slv_write(1), - SLV_DATA_OUT => slv_data_rd(1*32 + 31 downto 1*32), - SLV_DATA_IN => slv_data_wr(1*32 + 31 downto 1*32), - SLV_ADDR_IN => slv_addr(1*16 + 15 downto 1*16), - SLV_ACK_OUT => slv_ack(1), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(1), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1) - ); - - ctrl_din <= mupixslctrl_i.sin; - ctrl_clk1 <= mupixslctrl_i.clk1; - ctrl_clk2 <= mupixslctrl_i.clk2; - ctrl_ld <= mupixslctrl_i.load; - ctrl_rb <= mupixslctrl_i.rb; - - - boardcontrol_1 : entity work.MupixBoardDAC - port map( - clk => clk, - reset => reset, - spi_dout_dac => spi_dout_dac_sync, - dac4_dout => dac4_dout_sync, - spi_dout_adc => spi_dout_adc_sync, - spi_clk => spi_clk_i, - spi_din => spi_din_i, - spi_ld_tmp_dac => spi_ld_tmp_dac_i, - spi_ld_thres => spi_ld_thres_i, - spi_cs_adc => spi_cs_adc_i, - injection_pulse => testpulse_i, - SLV_READ_IN => slv_read(2), - SLV_WRITE_IN => slv_write(2), - SLV_DATA_OUT => slv_data_rd(2*32 + 31 downto 2*32), - SLV_DATA_IN => slv_data_wr(2*32 + 31 downto 2*32), - SLV_ADDR_IN => slv_addr(2*16 + 15 downto 2*16), - SLV_ACK_OUT => slv_ack(2), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2) - ); - - testpulse <= testpulse_i; - - spi_output_pipe : process (clk) is - begin - if rising_edge(clk) then - if reset = '1' then - spi_clk <= '0'; - spi_din <= '0'; - spi_ld_tmp_dac <= '0'; - spi_ld_thres <= '0'; - spi_cs_adc <= '1'; - else - spi_clk <= spi_clk_i; - spi_din <= spi_din_i; - spi_ld_tmp_dac <= spi_ld_tmp_dac_i; - spi_ld_thres <= spi_ld_thres_i; - spi_cs_adc <= spi_cs_adc_i; - end if; - end if; - end process spi_output_pipe; - - mupixreadout1 : entity work.MupixTRBReadout - generic map( - g_mupix_links => 4, - g_cyc_mem_address_width => 12, - g_datawidthfifo => c_mupixhitsize, - g_datawidthtrb => 32 - ) - port map( - clk => clk, - rst => reset, - fifo_empty => mux_fifo_empty, - fifo_full => mux_fifo_full, - fifo_datain => mux_fifo_data, - fifo_rden => mux_fifo_rden, - trb_trigger => trb_trigger_i, - dataout => mupixdata_i, - data_valid => mupixdata_valid_i, - busy => mupixreadout_busy_i, - SLV_READ_IN => slv_read(3), - SLV_WRITE_IN => slv_write(3), - SLV_DATA_OUT => slv_data_rd(3*32 + 31 downto 3*32), - SLV_DATA_IN => slv_data_wr(3*32 + 31 downto 3*32), - SLV_ADDR_IN => slv_addr(3*16 + 15 downto 3*16), - SLV_ACK_OUT => slv_ack(3), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(3), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3) - ); - - triggerhandler1 : entity work.TriggerHandler - port map( - CLK_IN => clk, - RESET_IN => reset, - TIMING_TRIGGER_IN => TIMING_TRG_IN, - LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN, - LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN, - LVL1_VALID_NOTIMING_TRG_IN => LVL1_VALID_NOTIMING_TRG_IN, - LVL1_INVALID_TRG_IN => LVL1_INVALID_TRG_IN, - LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, - LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, - LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN, - FEE_DATA_OUT => FEE_DATA_OUT, - FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT, - FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT, - FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT, - FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT, - FEE_DATA_0_IN => mupixdata_i, - FEE_DATA_WRITE_0_IN => mupixdata_valid_i, - TRIGGER_BUSY_BUFFER_READ_IN => mupixreadout_busy_i, - VALID_TRIGGER_OUT => trb_trigger_i, - SLV_READ_IN => slv_read(4), - SLV_WRITE_IN => slv_write(4), - SLV_DATA_OUT => slv_data_rd(4*32 + 31 downto 4*32), - SLV_DATA_IN => slv_data_wr(4*32 + 31 downto 4*32), - SLV_ADDR_IN => slv_addr(4*16 + 15 downto 4*16), - SLV_ACK_OUT => slv_ack(4), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(4), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4) - ); - - hitgenerator_1: entity work.FrameGeneratorMux - generic map( - FIFODEPTH => FIFO_DEPTH, - DATAWIDTH => c_mupixhitsize - ) - port map( - clk => clk, - reset => reset, - serdes_data => fifo_data_serdes_i, - serdes_fifo_full => fifo_full_serdes_i, - serdes_fifo_empty => fifo_empty_serdes_i, - serdes_fifo_rden => fifo_rden_serdes_i, - in_rden => mux_fifo_rden, - out_data => mux_fifo_data, - out_fifo_full => mux_fifo_full, - out_fifo_empty => mux_fifo_empty, - --TRB slow control - SLV_READ_IN => slv_read(5), - SLV_WRITE_IN => slv_write(5), - SLV_DATA_OUT => slv_data_rd(5*32 + 31 downto 5*32), - SLV_DATA_IN => slv_data_wr(5*32 + 31 downto 5*32), - SLV_ADDR_IN => slv_addr(5*16 + 15 downto 5*16), - SLV_ACK_OUT => slv_ack(5), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(5), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5) - ); - - mupix_data_link : entity work.MupixDataLink + + mupixboardinterface_1 : entity work.MupixBoardInterface + port map( + clk_in => clk, + fast_clk_in => fast_clk, + reset => reset, + ctrl_dout => ctrl_dout, + spi_dout_adc => spi_dout_adc, + spi_dout_dac => spi_dout_dac, + dac4_dout => dac4_dout, + hitbus => hitbus, + hit => '0', + trigger => '0', + ctrl_dout_sync => ctrl_dout_sync, + spi_dout_adc_sync => spi_dout_adc_sync, + spi_dout_dac_sync => spi_dout_dac_sync, + dac4_dout_sync => dac4_dout_sync, + hitbus_sync => hitbus_sync, + trigger_sync => trigger_sync, + hitbus_sync_fast => hitbus_sync_fast, + trigger_sync_fast => trigger_sync_fast, + hit_sync => hit_sync + ); + + hitbushistogram_1 : entity work.HitbusHistogram + generic map( + HistogramRange => 10, + PostOscillationWaitCycles => 5 + ) + port map( + clk => clk, + hitbus => hitbus_sync, + trigger => trigger_sync, + SLV_READ_IN => slv_read(0), + SLV_WRITE_IN => slv_write(0), + SLV_DATA_OUT => slv_data_rd(0*32 + 31 downto 0*32), + SLV_DATA_IN => slv_data_wr(0*32 + 31 downto 0*32), + SLV_ADDR_IN => slv_addr(0*16 + 15 downto 0*16), + SLV_ACK_OUT => slv_ack(0), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(0), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0) + ); + + pixelcontrol_1 : entity work.PixelControl + generic map( + fpga_clk_speed => fpga_clk_speed, + spi_clk_speed => mupix_spi_clk_speed + ) + port map( + clk => clk, + reset => reset, + mupixslctrl => mupixslctrl_i, + ctrl_dout => ctrl_dout_sync, + SLV_READ_IN => slv_read(1), + SLV_WRITE_IN => slv_write(1), + SLV_DATA_OUT => slv_data_rd(1*32 + 31 downto 1*32), + SLV_DATA_IN => slv_data_wr(1*32 + 31 downto 1*32), + SLV_ADDR_IN => slv_addr(1*16 + 15 downto 1*16), + SLV_ACK_OUT => slv_ack(1), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(1), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1) + ); + + ctrl_din <= mupixslctrl_i.sin; + ctrl_clk1 <= mupixslctrl_i.clk1; + ctrl_clk2 <= mupixslctrl_i.clk2; + ctrl_ld <= mupixslctrl_i.load; + ctrl_rb <= mupixslctrl_i.rb; + + + boardcontrol_1 : entity work.MupixBoardDAC + port map( + clk => clk, + reset => reset, + spi_dout_dac => spi_dout_dac_sync, + dac4_dout => dac4_dout_sync, + spi_dout_adc => spi_dout_adc_sync, + spi_clk => spi_clk_i, + spi_din => spi_din_i, + spi_ld_tmp_dac => spi_ld_tmp_dac_i, + spi_ld_thres => spi_ld_thres_i, + spi_cs_adc => spi_cs_adc_i, + injection_pulse => testpulse_i, + SLV_READ_IN => slv_read(2), + SLV_WRITE_IN => slv_write(2), + SLV_DATA_OUT => slv_data_rd(2*32 + 31 downto 2*32), + SLV_DATA_IN => slv_data_wr(2*32 + 31 downto 2*32), + SLV_ADDR_IN => slv_addr(2*16 + 15 downto 2*16), + SLV_ACK_OUT => slv_ack(2), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2) + ); + + testpulse <= testpulse_i; + + spi_output_pipe : process (clk) is + begin + if rising_edge(clk) then + if reset = '1' then + spi_clk <= '0'; + spi_din <= '0'; + spi_ld_tmp_dac <= '0'; + spi_ld_thres <= '0'; + spi_cs_adc <= '1'; + else + spi_clk <= spi_clk_i; + spi_din <= spi_din_i; + spi_ld_tmp_dac <= spi_ld_tmp_dac_i; + spi_ld_thres <= spi_ld_thres_i; + spi_cs_adc <= spi_cs_adc_i; + end if; + end if; + end process spi_output_pipe; + + mupixreadout1 : entity work.MupixTRBReadout + generic map( + g_mupix_links => 4, + g_cyc_mem_address_width => 12, + g_datawidthfifo => c_mupixhitsize, + g_datawidthtrb => 32 + ) + port map( + clk => clk, + rst => reset, + fifo_empty => mux_fifo_empty, + fifo_full => mux_fifo_full, + fifo_datain => mux_fifo_data, + fifo_rden => mux_fifo_rden, + trb_trigger => trb_trigger_i, + dataout => mupixdata_i, + data_valid => mupixdata_valid_i, + busy => mupixreadout_busy_i, + SLV_READ_IN => slv_read(3), + SLV_WRITE_IN => slv_write(3), + SLV_DATA_OUT => slv_data_rd(3*32 + 31 downto 3*32), + SLV_DATA_IN => slv_data_wr(3*32 + 31 downto 3*32), + SLV_ADDR_IN => slv_addr(3*16 + 15 downto 3*16), + SLV_ACK_OUT => slv_ack(3), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(3), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3) + ); + + triggerhandler1 : entity work.TriggerHandler + port map( + CLK_IN => clk, + RESET_IN => reset, + TIMING_TRIGGER_IN => TIMING_TRG_IN, + LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN, + LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN, + LVL1_VALID_NOTIMING_TRG_IN => LVL1_VALID_NOTIMING_TRG_IN, + LVL1_INVALID_TRG_IN => LVL1_INVALID_TRG_IN, + LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, + LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, + LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN, + FEE_DATA_OUT => FEE_DATA_OUT, + FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT, + FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT, + FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT, + FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT, + FEE_DATA_0_IN => mupixdata_i, + FEE_DATA_WRITE_0_IN => mupixdata_valid_i, + TRIGGER_BUSY_BUFFER_READ_IN => mupixreadout_busy_i, + VALID_TRIGGER_OUT => trb_trigger_i, + SLV_READ_IN => slv_read(4), + SLV_WRITE_IN => slv_write(4), + SLV_DATA_OUT => slv_data_rd(4*32 + 31 downto 4*32), + SLV_DATA_IN => slv_data_wr(4*32 + 31 downto 4*32), + SLV_ADDR_IN => slv_addr(4*16 + 15 downto 4*16), + SLV_ACK_OUT => slv_ack(4), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(4), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4) + ); + + hitgenerator_1 : entity work.FrameGeneratorMux + generic map( + FIFODEPTH => FIFO_DEPTH, + DATAWIDTH => c_mupixhitsize + ) + port map( + clk => clk, + reset => reset, + serdes_data => fifo_data_serdes_i, + serdes_fifo_full => fifo_full_serdes_i, + serdes_fifo_empty => fifo_empty_serdes_i, + serdes_fifo_rden => fifo_rden_serdes_i, + in_rden => mux_fifo_rden, + out_data => mux_fifo_data, + out_fifo_full => mux_fifo_full, + out_fifo_empty => mux_fifo_empty, + --TRB slow control + SLV_READ_IN => slv_read(5), + SLV_WRITE_IN => slv_write(5), + SLV_DATA_OUT => slv_data_rd(5*32 + 31 downto 5*32), + SLV_DATA_IN => slv_data_wr(5*32 + 31 downto 5*32), + SLV_ADDR_IN => slv_addr(5*16 + 15 downto 5*16), + SLV_ACK_OUT => slv_ack(5), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(5), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5) + ); + + mupix_data_link : entity work.MupixDataLinkWithUnpacker port map( - sysclk => clk, - dataclk => data_clk, - rst => reset, - clear => reset, - mupix_data => mupix_data, - refclk2core => open, - clk_rx_half_out => open, - clk_rx_full_out => open, - fifo_rden => fifo_rden_serdes_i, - fifo_empty => fifo_empty_serdes_i, - fifo_full => fifo_full_serdes_i, - fifo_data => fifo_data_serdes_i, + sysclk => clk, + dataclk => data_clk, + rst => reset, + clear => reset, + mupix_data => mupix_data, + refclk2core => open, + clk_rx_half_out => open, + clk_rx_full_out => open, + fifo_rden => fifo_rden_serdes_i, + fifo_empty => fifo_empty_serdes_i, + fifo_full => fifo_full_serdes_i, + fifo_data => fifo_data_serdes_i, --misc - channel_status_led => channel_status_led, + channel_status_led => channel_status_led, --trb slow control - SLV_READ_IN => slv_read(6), - SLV_WRITE_IN => slv_write(6), - SLV_DATA_OUT => slv_data_rd(6*32 + 31 downto 6*32), - SLV_DATA_IN => slv_data_wr(6*32 + 31 downto 6*32), - SLV_ADDR_IN => slv_addr(6*16 + 15 downto 6*16), - SLV_ACK_OUT => slv_ack(6), - SLV_NO_MORE_DATA_OUT => slv_no_more_data(6), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6)); + SLV_READ_IN => slv_read(6), + SLV_WRITE_IN => slv_write(6), + SLV_DATA_OUT => slv_data_rd(6*32 + 31 downto 6*32), + SLV_DATA_IN => slv_data_wr(6*32 + 31 downto 6*32), + SLV_ADDR_IN => slv_addr(6*16 + 15 downto 6*16), + SLV_ACK_OUT => slv_ack(6), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(6), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6)); end Behavioral; diff --git a/mupix/Mupix8/trb3_periph.prj b/mupix/Mupix8/trb3_periph.prj index 834d673..37af33d 100644 --- a/mupix/Mupix8/trb3_periph.prj +++ b/mupix/Mupix8/trb3_periph.prj @@ -144,14 +144,14 @@ add_file -vhdl -lib work "../../../trbnet/media_interfaces/trb_net16_med_ecp3_sf #ip cores for mupix design add_file -vhdl -lib "work" "../../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "cores/pll_mupix_main.vhd" -add_file -vhdl -lib "work" "cores/mupix_serdes.vhd" -add_file -vhdl -lib "work" "cores/serdes_fifo_large.vhd" +add_file -vhdl -lib "work" "cores/mupix_serdes_new.vhd" add_file -vhdl -lib "work" "cores/serdes_fifo.vhd" #MuPix Files add_file -vhdl -lib "work" "trb3_periph.vhd" add_file -vhdl -lib "work" "sources/StdTypes.vhd" +add_file -vhdl -lib "work" "sources/constants.vhd" add_file -vhdl -lib "work" "sources/MupixBoard.vhd" add_file -vhdl -lib "work" "sources/InputSynchronizer.vhd" add_file -vhdl -lib "work" "sources/MupixBoardInterface.vhd" @@ -170,10 +170,13 @@ add_file -vhdl -lib "work" "sources/ResetHandler.vhd" add_file -vhdl -lib "work" "sources/CircularMemory.vhd" add_file -vhdl -lib "work" "sources/ReadoutController.vhd" add_file -vhdl -lib "work" "sources/MupixTRBReadout.vhd" -add_file -vhdl -lib "work" "sources/DataMux.vhd" -add_file -vhdl -lib "work" "sources/MupixDataLink.vhd" +add_file -vhdl -lib "work" "sources/MupixDataLink_new.vhd" add_file -vhdl -lib "work" "sources/TriggerHandler.vhd" add_file -vhdl -lib "work" "sources/Arbiter.vhd" add_file -vhdl -lib "work" "sources/DatasourceSelector.vhd" add_file -vhdl -lib "work" "sources/FrameGenMux2.vhd" add_file -vhdl -lib "work" "sources/Generator3.vhd" +add_file -vhdl -lib "work" "sources/DataMuxWithConversion.vhd" +add_file -vhdl -lib "work" "sources/GrayCounter2.vhd" +add_file -vhdl -lib "work" "sources/MuPixUnpacker.vhd" +add_file -vhdl -lib "work" "sources/LinkSynchronizer.vhd"