From: Jan Michel <j.michel@gsi.de>
Date: Fri, 21 Nov 2014 15:48:08 +0000 (+0100)
Subject: added new padiwa register
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=caf72a4a09c98276debb20232a4699f74cedfac8;p=padiwadocu.git

added new padiwa register
---

diff --git a/fw_spiconfig.tex b/fw_spiconfig.tex
index c5a4b59..72b59b3 100644
--- a/fw_spiconfig.tex
+++ b/fw_spiconfig.tex
@@ -34,6 +34,8 @@ when temperature is changing. See below. \\
 0x20 & 10 & Test & Reads a word from the test Fifo. \\
 0x21 & 0--2 & Design & Design Information. Register 0/1: lower/upper part of 
 Unix timestamp of time of compilation. Register 2: Padiwa version number.\\
+0x22 & any & Cnt & Lower 16 Bits of input signal counters for all 16 channels.\\
+0x23 & any & Cnt & Upper 8 Bit of input signal counters.\\
 0x40 & any & Memory & Read/Write to/from RAM. 16 registers with 8 Bit each.\\
 0x50 & 0 & Flash & Execute Flash command.\\
 0x51 & 0--1 & Flash & Load RAM content to PWM settings. Channel Bit 0 selects upper or lower half of PWM channels. No data payload\\