From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Fri, 11 Feb 2022 17:38:37 +0000 (+0100)
Subject: typos fixed
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=cb40b11dbe75a0a730b2196af11962dba5e78dea;p=trbnet.git

typos fixed
---

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index f372974..bdc408f 100644
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -18,7 +18,6 @@ entity med_ecp3_sfp_sync_all_RS is
     -- Clocks and reset
     CLK_REF_FULL       : in  std_logic; -- TRBnet reference clock
     SYSCLK             : in  std_logic; -- FPGA fabric clock
-    SAMPLE_CLK         : in  std_logic; -- DLM measurement clock
     RESET              : in  std_logic; -- synchronous reset
     -- Media Interface TX/RX
     MEDIA_MED2INT      : out med2int_array_t(0 to 3);
diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd
index aec6701..47d523b 100644
--- a/media_interfaces/sync/main_rx_reset_RS.vhd
+++ b/media_interfaces/sync/main_rx_reset_RS.vhd
@@ -150,7 +150,7 @@ begin
           RX_SERDES_RST_OUT <= '0';
           RX_PCS_RST_OUT    <= '1';
           LINK_RX_READY_OUT <= '0';
-          if( cnt(Tshort_bit) ) then
+          if( cnt(Tshort_bit) = '1' ) then
             cnt <= (others => '0');
             rx_sm <= WAIT_RXPCS_LOCK;
           else