From: Ingo Froehlich Date: Thu, 24 Aug 2017 16:14:26 +0000 (+0200) Subject: generic flash ctrl with generic bus width, IF X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=cbd83d9ad3cbfd5c8ec06c80009ce2a73220f790;p=vhdlbasics.git generic flash ctrl with generic bus width, IF --- diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd index ee5670c..7cfeeea 100644 --- a/machxo3/flash/generic_flash_ctrl.vhd +++ b/machxo3/flash/generic_flash_ctrl.vhd @@ -30,22 +30,24 @@ library work; use work.trb_net_std.all; entity generic_flash_ctrl is - generic (MASTER_STARTPAGE : std_logic_vector(12 downto 0) := "1" & x"C00"); + generic (MASTER_STARTPAGE : std_logic_vector(12 downto 0) := "1" & x"C00"; + DATA_BUS_WIDTH : integer := 16 + ); port( CLK : in std_logic; RESET : in std_logic; -- SPI in host direction - SPI_DATA_IN : in std_logic_vector(15 downto 0); - SPI_DATA_OUT : out std_logic_vector(15 downto 0); + SPI_DATA_IN : in std_logic_vector(DATA_BUS_WIDTH-1 downto 0); + SPI_DATA_OUT : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0); SPI_ADDR_IN : in std_logic_vector(7 downto 0); SPI_WRITE_IN : in std_logic; SPI_READ_IN : in std_logic; SPI_READY_OUT : out std_logic; -- SPI in local direction - LOC_DATA_OUT : out std_logic_vector(15 downto 0); - LOC_DATA_IN : in std_logic_vector(15 downto 0); + LOC_DATA_OUT : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0); + LOC_DATA_IN : in std_logic_vector(DATA_BUS_WIDTH-1 downto 0); LOC_ADDR_OUT : out std_logic_vector(7 downto 0); LOC_WRITE_OUT : out std_logic; LOC_READ_OUT : out std_logic; @@ -73,9 +75,9 @@ architecture arch of generic_flash_ctrl is ); end component; - signal reg_SPI_DATA_OUT : std_logic_vector(15 downto 0); + signal reg_SPI_DATA_OUT : std_logic_vector(DATA_BUS_WIDTH-1 downto 0); signal reg_SPI_READY_OUT : std_logic; - signal reg_LOC_DATA_OUT : std_logic_vector(15 downto 0); + signal reg_LOC_DATA_OUT : std_logic_vector(DATA_BUS_WIDTH-1 downto 0); signal reg_LOC_ADDR_OUT : std_logic_vector(7 downto 0); signal reg_LOC_WRITE_OUT : std_logic; signal reg_LOC_READ_OUT : std_logic; @@ -103,7 +105,7 @@ architecture arch of generic_flash_ctrl is signal spi_ram_addr_i : std_logic_vector(3 downto 0); signal enable_cfg_flash : std_logic; - signal testreg : std_logic_vector(15 downto 0); + signal testreg : std_logic_vector(DATA_BUS_WIDTH-1 downto 0); signal out_delay : std_logic_vector(1 downto 0); @@ -117,7 +119,7 @@ architecture arch of generic_flash_ctrl is signal master_flash_go : std_logic; signal master_start_reg : std_logic := '0'; signal clean_master_start_reg : std_logic := '0'; - signal master_DATA_OUT : std_logic_vector(15 downto 0); + signal master_DATA_OUT : std_logic_vector(DATA_BUS_WIDTH-1 downto 0); signal master_ADDR_OUT : std_logic_vector(7 downto 0); signal master_WRITE_OUT : std_logic; @@ -179,7 +181,7 @@ PROC_SELECTOR : process begin reg_LOC_READ_OUT <= SPI_READ_IN; reg_SPI_DATA_OUT <= LOC_DATA_IN; reg_SPI_READY_OUT <= LOC_READY_IN; - + ram_write_i <= '0'; ram_data_i <= x"00"; spi_ram_addr_i <= x"0"; @@ -221,7 +223,10 @@ PROC_SELECTOR : process begin reg_LOC_ADDR_OUT <= master_ADDR_OUT; end if; - + if (DATA_BUS_WIDTH-1 > 15) then + reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 16) <= (others => '0'); + end if; + if (out_delay = "01") then reg_LOC_READ_OUT <= '0'; reg_SPI_READY_OUT <= '0'; @@ -229,13 +234,13 @@ PROC_SELECTOR : process begin elsif (out_delay = "10") then reg_LOC_READ_OUT <= '0'; reg_SPI_READY_OUT <= '1'; - reg_SPI_DATA_OUT <= flash_busy & flash_err & "000000" & ram_data_o; + reg_SPI_DATA_OUT(15 downto 0) <= flash_busy & flash_err & "000000" & ram_data_o; out_delay <= "00"; else out_delay <= "00"; end if; - if (SPI_READ_IN = '1') then + if (SPI_READ_IN = '1') then if (SPI_ADDR_IN(7 downto 4) = x"4") then out_delay <= "01"; reg_LOC_READ_OUT <= '0'; @@ -246,11 +251,11 @@ PROC_SELECTOR : process begin elsif (SPI_ADDR_IN(7 downto 0) = x"5C") then reg_LOC_READ_OUT <= '0'; reg_SPI_READY_OUT <= '1'; - reg_SPI_DATA_OUT <= x"01" & "00000" & master_running & master_start_reg & enable_cfg_flash; + reg_SPI_DATA_OUT(15 downto 0) <= x"01" & "00000" & master_running & master_start_reg & enable_cfg_flash; elsif (SPI_ADDR_IN(7 downto 0) = x"5d") then reg_LOC_READ_OUT <= '0'; reg_SPI_READY_OUT <= '1'; - reg_SPI_DATA_OUT <= auto_dbg & "00" & master_flash_page; + reg_SPI_DATA_OUT(15 downto 0) <= auto_dbg & "00" & master_flash_page; elsif (SPI_ADDR_IN(7 downto 0) = x"5e") then reg_LOC_READ_OUT <= '0'; reg_SPI_READY_OUT <= '1'; @@ -259,7 +264,7 @@ PROC_SELECTOR : process begin reg_LOC_READ_OUT <= '0'; reg_SPI_READY_OUT <= '1'; -- reg_SPI_DATA_OUT <= testreg; - reg_SPI_DATA_OUT <= x"000" & master_word_counter; + reg_SPI_DATA_OUT(15 downto 0) <= x"000" & master_word_counter; end if; end if; @@ -278,12 +283,16 @@ begin master_WRITE_OUT <= '0'; clean_master_start_reg <= '0'; + if (DATA_BUS_WIDTH-1 > 15) then + master_DATA_OUT(DATA_BUS_WIDTH-1 downto 16) <= (others => '0'); + end if; + case state is when IDLE => if (master_start_reg = '1' or auto_reset = '1') then state <= Start; clean_master_start_reg <= '1'; - master_DATA_OUT <= x"0000"; + master_DATA_OUT <= (others => '0'); master_ADDR_OUT <= x"00"; if (auto_reset = '1') then auto_cnt <= std_logic_vector(unsigned(auto_cnt) + 1); @@ -331,7 +340,7 @@ begin state <= WaitRAM2; master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1); else - master_DATA_OUT <= x"ff" & ram_data_o; + master_DATA_OUT(15 downto 0) <= x"ff" & ram_data_o; state <= IDLE; end if; when WaitRAM2 => @@ -339,16 +348,16 @@ begin state <= WaitRAM3; master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1); when WaitRAM3 => - master_DATA_OUT <= ram_data_o & x"00"; + master_DATA_OUT(15 downto 0) <= ram_data_o & x"00"; state <= WaitRAM4; when WaitRAM4 => - master_DATA_OUT <= master_DATA_OUT(15 downto 8) & ram_data_o; + master_DATA_OUT(15 downto 0) <= master_DATA_OUT(15 downto 8) & ram_data_o; state <= WriteSPI; master_WRITE_OUT <= '1'; when WriteSPI => -- prepare for next cycle if (master_word_counter = x"F") then - master_DATA_OUT <= x"eeee"; + --master_DATA_OUT(15 downto 0) <= x"eeee"; state <= ReadPage; master_word_counter <= "0000"; master_flash_page <= std_logic_vector(unsigned(master_flash_page) + 1);