From: hadeshyp <hadeshyp>
Date: Fri, 18 Apr 2008 12:56:44 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~569
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=cc20923d5064bb1fbf7c4ea897da4f45bc15f0e9;p=trbnet.git

*** empty log message ***
---

diff --git a/trb_net_rom_16x8.vhd b/trb_net_rom_16x8.vhd
new file mode 100644
index 0000000..dc8f734
--- /dev/null
+++ b/trb_net_rom_16x8.vhd
@@ -0,0 +1,40 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_rom_16x8 is
+  generic(
+    INIT0 : std_logic_vector(15 downto 0) := x"0000";
+    INIT1 : std_logic_vector(15 downto 0) := x"0000";
+    INIT2 : std_logic_vector(15 downto 0) := x"0000";
+    INIT3 : std_logic_vector(15 downto 0) := x"0000";
+    INIT4 : std_logic_vector(15 downto 0) := x"0000";
+    INIT5 : std_logic_vector(15 downto 0) := x"0000";
+    INIT6 : std_logic_vector(15 downto 0) := x"0000";
+    INIT7 : std_logic_vector(15 downto 0) := x"0000"
+    );
+  port(
+    CLK  : in  std_logic;
+    a    : in  std_logic_vector(2 downto 0);
+    dout : out std_logic_vector(15 downto 0)
+    );
+end entity;
+
+architecture trb_net_rom_16x8_arch of trb_net_rom_16x8 is
+  type ram_t is array(0 to 7) of std_logic_vector(15 downto 0);
+  SIGNAL ram : ram_t := (INIT0, INIT1, INIT2, INIT3, INIT4, INIT5, INIT6, INIT7);
+begin
+
+
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        dout <= ram(conv_integer(a));
+      end if;
+    end process;
+
+end architecture;
\ No newline at end of file