From: Michael Boehmer Date: Thu, 27 Jan 2022 17:00:06 +0000 (+0100) Subject: phaser code changed for placement X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=cc319acc33bce52ce6e1ed72b9aad480d42c8ac2;p=trbnet.git phaser code changed for placement --- diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index 784fedd..69622e0 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -18,6 +18,7 @@ entity med_ecp3_sfp_sync_all_RS is -- Clocks and reset CLK_REF_FULL : in std_logic; -- TRBnet reference clock SYSCLK : in std_logic; -- FPGA fabric clock + SAMPLE_CLK : in std_logic; -- DLM measurement clock RESET : in std_logic; -- synchronous reset -- Media Interface TX/RX MEDIA_MED2INT : out med2int_array_t(0 to 3); @@ -49,6 +50,7 @@ entity med_ecp3_sfp_sync_all_RS is DESTROY_LINK_IN : in std_logic_vector(3 downto 0); -- hard reset for links WAP_REQUESTED_IN : in std_logic_vector(3 downto 0); -- TESTTESTTEST RX_INDEX_OUT : out std_logic_vector(3 downto 0); -- TESTTESTTEST + DLM_RESULT_OUT : out std_logic_vector(4*32-1 downto 0); -- TESTTESTTEST --SFP Connection SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) @@ -124,6 +126,7 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is signal rx_rst_word_i : std_logic_vector(4*8-1 downto 0); signal rx_rst_i : std_logic_vector(3 downto 0); + signal rx_dlm_i : std_logic_vector(3 downto 0); signal global_reset_i : std_logic_vector(3 downto 0); @@ -140,6 +143,8 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is signal wap_requested_i : std_logic_vector(15 downto 0); signal rx_index_i : std_logic_vector(3 downto 0); + signal dlm_result_i : std_logic_vector(4*32-1 downto 0); + signal quad_mode : integer range 0 to 100; @@ -486,7 +491,7 @@ gen_control : for i in 0 to 3 generate TX_DLM_WORD_IN => TX_DLM_WORD_IN, TX_RST_IN => tx_rst_i(i), TX_RST_WORD_IN => TX_RST_WORD_IN, - RX_DLM_OUT => RX_DLM_OUT(i), + RX_DLM_OUT => rx_dlm_i(i), RX_DLM_WORD_OUT => RX_DLM_WORD_OUT(i*8+7 downto i*8), RX_RST_OUT => rx_rst_i(i), RX_RST_WORD_OUT => rx_rst_word_i(i*8+7 downto i*8), @@ -513,8 +518,29 @@ gen_control : for i in 0 to 3 generate MEDIA_MED2INT(i).stat_op <= x"0007"; end generate; + gen_phaser : if (IS_MODE(i) = c_IS_MASTER) generate + THE_PHASER : entity work.phaser + port map( + SAMPLE_CLK => SAMPLE_CLK, + RESET => RESET, + START_IN => TX_DLM_IN, -- TX DLM + STOP_IN => rx_dlm_i(i), -- RX DLM + PING_IN => word_sync_sel, -- TX K + CLK_PING => MASTER_CLK_IN, -- TX CLK + PONG_IN => rx_index_i(i), -- RX K + CLK_PONG => clk_rx_full(i), -- RX CLK + RESULT_OUT => dlm_result_i(i*32+31 downto i*32), + UPDATE_OUT => open + ); + + --- BUG BUG BUG word_sync_sel works not always + end generate; + end generate; + RX_DLM_OUT <= rx_dlm_i; + DLM_RESULT_OUT <= dlm_result_i; + THE_SCI_READER : entity work.sci_reader_RS port map( CLK => SYSCLK, diff --git a/special/phaser.vhd b/special/phaser.vhd index 59f6e8d..936fd2e 100644 --- a/special/phaser.vhd +++ b/special/phaser.vhd @@ -6,12 +6,15 @@ library work; entity phaser is port( - SAMPLE_CLK : in std_logic; + SAMPLE_CLK : in std_logic; -- clock for sampling XOR RESET : in std_logic; - SIGNAL_A_IN : in std_logic; - SIGNAL_B_IN : in std_logic; - LOW_CNT_OUT : out std_logic_vector(15 downto 0); - HI_CNT_OUT : out std_logic_vector(15 downto 0); + START_IN : in std_logic; -- TX DLM + STOP_IN : in std_logic; -- RX DLM + PING_IN : in std_logic; -- TX K + CLK_PING : in std_logic; -- TX CLK + PONG_IN : in std_logic; -- RX K + CLK_PONG : in std_logic; -- RX CLK + RESULT_OUT : out std_logic_vector(31 downto 0); UPDATE_OUT : out std_logic ); end entity phaser; @@ -23,68 +26,68 @@ architecture arch of phaser is -- state machine signals -- Signals - signal low_cnt : unsigned(15 downto 0); - signal hi_cnt : unsigned(15 downto 0); - signal cyc_cnt : unsigned(15 downto 0); - signal update : std_logic; - signal cycle_done_x : std_logic; - signal cycle_done : std_logic; - signal phase_x : std_logic; - signal phase : std_logic; - - signal low_cnt_int : std_logic_vector(15 downto 0); - signal hi_cnt_int : std_logic_vector(15 downto 0); - ---attribute HGROUP: string; ---attribute BBOX: string; ---attribute HGROUP of behavioural: architecture is "phaser"; ---attribute BBOX   of behavioural: architecture is "5,5"; + signal hi_cnt : unsigned(20 downto 0); + signal cyc_cnt : unsigned(20 downto 0); + signal update : std_logic; + signal cyc_done_x : std_logic; + signal cyc_done : std_logic; + signal phase_x : std_logic; + signal phase : std_logic; + signal hi_cnt_int : std_logic_vector(20 downto 0); + + signal coarse_counter : unsigned(11 downto 0); + signal coarse_delay : std_logic_vector(11 downto 0); begin --------------------------------------------------------------------------- --- Sync process +-- coarse delay measurement, based on TX clock --------------------------------------------------------------------------- - THE_SYNC_PROCESS: process( SAMPLE_CLK ) + THE_COARSE_COUNTER_PROC: process( CLK_PING ) begin - if( rising_edge(SAMPLE_CLK) ) then - cycle_done <= cycle_done_x; - update <= cycle_done; - phase <= phase_x; + if( rising_edge(CLK_PING) ) then + if( START_IN = '1' ) then + coarse_counter <= (others => '0'); + else + coarse_counter <= coarse_counter + 1; + end if; + if( STOP_IN = '1' ) then + coarse_delay <= std_logic_vector(coarse_counter); + end if; end if; - end process THE_SYNC_PROCESS; - - phase_x <= SIGNAL_A_IN xor SIGNAL_B_IN; + end process THE_COARSE_COUNTER_PROC; + +--------------------------------------------------------------------------- +--------------------------------------------------------------------------- + THE_PHASER_CORE: entity phaser_core + port map( + SAMPLE_CLK => SAMPLE_CLK, + PING_IN => PING_IN, + CLK_PING => CLK_PING, + PONG_IN => PONG_IN, + CLK_PONG => CLK_PONG, + PHASE_OUT => phase + ); -- Cycle counter THE_CYC_CNT_PROC: process( SAMPLE_CLK, RESET ) begin if( RESET = '1' ) then - cyc_cnt <= (others => '0'); + cyc_cnt <= (others => '0'); + cyc_done <= '0'; + update <= '0'; elsif( rising_edge(SAMPLE_CLK) ) then - if( cycle_done = '1' ) then + if( cyc_done = '1' ) then cyc_cnt <= (others => '0'); else cyc_cnt <= cyc_cnt + 1; end if; + cyc_done <= cyc_done_x; + update <= cyc_done; end if; end process THE_CYC_CNT_PROC; - cycle_done_x <= '1' when (cyc_cnt = x"fffc") else '0'; - - -- low signal count - THE_LOW_CNT_PROC: process( SAMPLE_CLK, RESET ) - begin - if( RESET = '1' ) then - low_cnt <= (others => '0'); - elsif( rising_edge(SAMPLE_CLK) ) then - if( cycle_done = '1' ) then - low_cnt <= (others => '0'); - elsif( phase = '0') then - low_cnt <= low_cnt + 1; - end if; - end if; - end process THE_LOW_CNT_PROC; + cyc_done_x <= '1' when (cyc_cnt = x"fffffc") else '0'; -- high signal count THE_HI_CNT_PROC: process( SAMPLE_CLK, RESET ) @@ -92,7 +95,7 @@ begin if( RESET = '1' ) then hi_cnt <= (others => '0'); elsif( rising_edge(SAMPLE_CLK) ) then - if( cycle_done = '1' ) then + if( cyc_done = '1' ) then hi_cnt <= (others => '0'); elsif( phase = '1') then hi_cnt <= hi_cnt + 1; @@ -103,11 +106,9 @@ begin THE_COUNTER_STORE_PROC: process( SAMPLE_CLK, RESET ) begin if( RESET = '1' ) then - low_cnt_int <= (others => '0'); hi_cnt_int <= (others => '0'); elsif( rising_edge(SAMPLE_CLK) ) then -- added - if( cycle_done = '1' ) then - low_cnt_int <= std_logic_vector(low_cnt); + if( cyc_done = '1' ) then hi_cnt_int <= std_logic_vector(hi_cnt); end if; end if; @@ -116,8 +117,8 @@ begin --------------------------------------------------------------------------- --------------------------------------------------------------------------- - LOW_CNT_OUT <= low_cnt_int; - HI_CNT_OUT <= hi_cnt_int; - UPDATE_OUT <= update; + RESULT_OUT(31 downto 20) <= coarse_delay(11 downto 0); + RESULT_OUT(19 downto 0) <= hi_cnt_int(19 downto 0); + UPDATE_OUT <= update; end architecture; diff --git a/special/phaser_core.vhd b/special/phaser_core.vhd new file mode 100644 index 0000000..db36867 --- /dev/null +++ b/special/phaser_core.vhd @@ -0,0 +1,55 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; + +entity phaser_core is + port( + SAMPLE_CLK : in std_logic; + PING_IN : in std_logic; -- TX K + CLK_PING : in std_logic; -- TX CLK + PONG_IN : in std_logic; -- RX K + CLK_PONG : in std_logic; -- RX CLK + PHASE_OUT : out std_logic + ); +end entity phaser_core; + +architecture phaser_core_arch of phaser_core is + +-- Components + +-- state machine signals + +-- Signals + signal ping_i : std_logic; + signal pong_i : std_logic; + signal phase_x : std_logic; + signal phase : std_logic; + + attribute HGROUP : string; + attribute BBOX : string; + attribute HGROUP of phaser_core_arch : architecture is "phaser_core_group"; + attribute BBOX of phaser_core_arch : architecture is "1,1"; + attribute syn_sharing : string; + attribute syn_sharing of phaser_core_arch : architecture is "off"; + attribute syn_hier : string; + attribute syn_hier of phaser_core_arch : architecture is "hard"; + +begin + +--------------------------------------------------------------------------- +-- we want all logic in here in one PFU (defined timing)! +--------------------------------------------------------------------------- + + -- slice 0 + ping_i <= PING_IN when rising_edge(CLK_PING); -- FF + -- slice 1 + pong_i <= PONG_IN when rising_edge(CLK_PONG); -- FF + -- slice 2 + phase_x <= ping_i xor pong_i; -- LUT4 + phase <= phase_x when rising_edge(SAMPLE_CLK); -- FF + + PHASE_OUT <= phase; + +end architecture;