From: hadaq Date: Wed, 28 Apr 2010 12:17:49 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: v1.0~3 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=cc335a0403ab06b2af086217038605905e5700ac;p=adcm.git *** empty log message *** --- diff --git a/lookup_adc.txt b/lookup_adc.txt index b07211d..53043ac 100755 --- a/lookup_adc.txt +++ b/lookup_adc.txt @@ -1,119 +1,119 @@ -Backplane 0 -=========== - -ADC0/0 0 0/6 3 0xb000 0x20030001 -ADC0/1 1 0/7 5 0xb001 0x20050001 -ADC0/2 2 0/0 10 0xb002 0x200a0001 -ADC0/3 3 0/2 12 0xb003 0x200c0001 -ADC0/4 4 0/1 9 0xb004 0x20090001 -ADC0/5 5 0/3 7 0xb005 0x20070001 -ADC0/6 6 0/5 0 0xb006 0x20000001 -ADC0/7 7 -/- -- 0xb007 0x200f0001 - -ADC1/0 8 1/6 4 0xb008 0x20040001 -ADC1/1 9 1/7 6 0xb009 0x20060001 -ADC1/2 10 1/1 11 0xb00a 0x200b0001 -ADC1/3 11 1/0 8 0xb00b 0x20080001 -ADC1/4 12 1/3 14 0xb00c 0x200e0001 -ADC1/5 13 1/2 13 0xb00d 0x200d0001 -ADC1/6 14 1/5 2 0xb00e 0x20020001 -ADC1/7 15 1/4 1 0xb00f 0x20010001 - -realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1 - -Backplane 1 -========== - -ADC0/0 0 0/6 12 0xb000 0x200c0001 -ADC0/1 1 0/7 11 0xb001 0x200b0001 -ADC0/2 2 0/0 10 0xb002 0x200a0001 -ADC0/3 3 0/2 9 0xb003 0x20090001 -ADC0/4 4 0/1 8 0xb004 0x20080001 -ADC0/5 5 0/3 7 0xb005 0x20070001 -ADC0/6 6 0/5 13 0xb006 0x200d0001 -ADC0/7 7 0/4 14 0xb007 0x200e0001 - -ADC1/0 8 1/6 3 0xb008 0x20030001 -ADC1/1 9 1/7 2 0xb009 0x20020001 -ADC1/2 10 1/1 1 0xb00a 0x20010001 -ADC1/3 11 1/0 0 0xb00b 0x20000001 -ADC1/4 12 1/3 6 0xb00c 0x20060001 -ADC1/5 13 1/2 5 0xb00d 0x20050001 -ADC1/6 14 1/5 4 0xb00e 0x20040001 -ADC1/7 15 -/- -- 0xb00f 0x200f0001 - -realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 - - -Backplane 2 -=========== - -ADC0/0 0 -/- -- 0xb000 0x200f0001 -ADC0/1 1 0/7 4 0xb001 0x20040001 -ADC0/2 2 0/0 5 0xb002 0x20050001 -ADC0/3 3 0/2 6 0xb003 0x20060001 -ADC0/4 4 0/1 0 0xb004 0x20000001 -ADC0/5 5 0/3 1 0xb005 0x20010001 -ADC0/6 6 0/5 2 0xb006 0x20020001 -ADC0/7 7 0/4 3 0xb007 0x20030001 - -ADC1/0 8 1/6 14 0xb008 0x200e0001 -ADC1/1 9 1/7 13 0xb009 0x200d0001 -ADC1/2 10 1/1 7 0xb00a 0x20070001 -ADC1/3 11 1/0 8 0xb00b 0x20080001 -ADC1/4 12 1/3 9 0xb00c 0x20090001 -ADC1/5 13 1/2 10 0xb00d 0x200a0001 -ADC1/6 14 1/5 11 0xb00e 0x200b0001 -ADC1/7 15 1/4 12 0xb00f 0x200c0001 - -realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12 - -Backplane 3 -=========== - -ADC0/0 0 0/6 10 0xb000 0x200a0001 -ADC0/1 1 0/7 9 0xb001 0x20090001 -ADC0/2 2 0/0 8 0xb002 0x20080001 -ADC0/3 3 0/2 7 0xb003 0x20070001 -ADC0/4 4 0/1 6 0xb004 0x20060001 -ADC0/5 5 0/3 5 0xb005 0x20050001 -ADC0/6 6 0/5 12 0xb006 0x200c0001 -ADC0/7 7 0/4 11 0xb007 0x200b0001 - -ADC1/0 8 1/6 4 0xb008 0x20040001 -ADC1/1 9 1/7 3 0xb009 0x20030001 -ADC1/2 10 1/1 0 0xb00a 0x20000001 -ADC1/3 11 1/0 2 0xb00b 0x20020001 -ADC1/4 12 1/3 1 0xb00c 0x20010001 -ADC1/5 13 -/- -- 0xb00d 0x200f0001 -ADC1/6 14 1/5 13 0xb00e 0x200d0001 -ADC1/7 15 1/4 14 0xb00f 0x200e0001 - -realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14 - -Backplane 4 -=========== - -ADC0/0 0 0/6 14 0xb000 0x200e0001 -ADC0/1 1 0/7 13 0xb001 0x200d0001 -ADC0/2 2 -/- -- 0xb002 0x200f0001 -ADC0/3 3 0/2 1 0xb003 0x20010001 -ADC0/4 4 0/1 2 0xb004 0x20020001 -ADC0/5 5 0/3 0 0xb005 0x20000001 -ADC0/6 6 0/5 3 0xb006 0x20030001 -ADC0/7 7 0/4 4 0xb007 0x20040001 - -ADC1/0 8 1/6 11 0xb008 0x200b0001 -ADC1/1 9 1/7 12 0xb009 0x200c0001 -ADC1/2 10 1/1 5 0xb00a 0x20050001 -ADC1/3 11 1/0 6 0xb00b 0x20060001 -ADC1/4 12 1/3 7 0xb00c 0x20070001 -ADC1/5 13 1/2 8 0xb00d 0x20080001 -ADC1/6 14 1/5 9 0xb00e 0x20090001 -ADC1/7 15 1/4 10 0xb00f 0x200a0001 - -realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10 +Backplane 0 +=========== + +ADC0/0 0 0/6 3 0xb000 0x20030001 +ADC0/1 1 0/7 5 0xb001 0x20050001 +ADC0/2 2 0/0 10 0xb002 0x200a0001 +ADC0/3 3 0/2 12 0xb003 0x200c0001 +ADC0/4 4 0/1 9 0xb004 0x20090001 +ADC0/5 5 0/3 7 0xb005 0x20070001 +ADC0/6 6 0/5 0 0xb006 0x20000001 +ADC0/7 7 -/- -- 0xb007 0x200f0001 + +ADC1/0 8 1/6 4 0xb008 0x20040001 +ADC1/1 9 1/7 6 0xb009 0x20060001 +ADC1/2 10 1/1 11 0xb00a 0x200b0001 +ADC1/3 11 1/0 8 0xb00b 0x20080001 +ADC1/4 12 1/3 14 0xb00c 0x200e0001 +ADC1/5 13 1/2 13 0xb00d 0x200d0001 +ADC1/6 14 1/5 2 0xb00e 0x20020001 +ADC1/7 15 1/4 1 0xb00f 0x20010001 + +realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +mapAPV 3 5 10 12 9 7 0 - 4 6 11 8 14 13 2 1 + +Backplane 1 +========== + +ADC0/0 0 0/6 12 0xb000 0x200c0001 +ADC0/1 1 0/7 11 0xb001 0x200b0001 +ADC0/2 2 0/0 10 0xb002 0x200a0001 +ADC0/3 3 0/2 9 0xb003 0x20090001 +ADC0/4 4 0/1 8 0xb004 0x20080001 +ADC0/5 5 0/3 7 0xb005 0x20070001 +ADC0/6 6 0/5 13 0xb006 0x200d0001 +ADC0/7 7 0/4 14 0xb007 0x200e0001 + +ADC1/0 8 1/6 3 0xb008 0x20030001 +ADC1/1 9 1/7 2 0xb009 0x20020001 +ADC1/2 10 1/1 1 0xb00a 0x20010001 +ADC1/3 11 1/0 0 0xb00b 0x20000001 +ADC1/4 12 1/3 6 0xb00c 0x20060001 +ADC1/5 13 1/2 5 0xb00d 0x20050001 +ADC1/6 14 1/5 4 0xb00e 0x20040001 +ADC1/7 15 -/- -- 0xb00f 0x200f0001 + +realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +mapAPV 12 11 10 9 8 7 13 14 3 2 1 0 6 5 4 - + +Backplane 2 +=========== + +ADC0/0 0 -/- -- 0xb000 0x200f0001 +ADC0/1 1 0/7 4 0xb001 0x20040001 +ADC0/2 2 0/0 5 0xb002 0x20050001 +ADC0/3 3 0/2 6 0xb003 0x20060001 +ADC0/4 4 0/1 0 0xb004 0x20000001 +ADC0/5 5 0/3 1 0xb005 0x20010001 +ADC0/6 6 0/5 2 0xb006 0x20020001 +ADC0/7 7 0/4 3 0xb007 0x20030001 + +ADC1/0 8 1/6 14 0xb008 0x200e0001 +ADC1/1 9 1/7 13 0xb009 0x200d0001 +ADC1/2 10 1/1 7 0xb00a 0x20070001 +ADC1/3 11 1/0 8 0xb00b 0x20080001 +ADC1/4 12 1/3 9 0xb00c 0x20090001 +ADC1/5 13 1/2 10 0xb00d 0x200a0001 +ADC1/6 14 1/5 11 0xb00e 0x200b0001 +ADC1/7 15 1/4 12 0xb00f 0x200c0001 + +realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +mapAPV - 4 5 6 0 1 2 3 14 13 7 8 9 10 11 12 + +Backplane 3 +=========== + +ADC0/0 0 0/6 10 0xb000 0x200a0001 +ADC0/1 1 0/7 9 0xb001 0x20090001 +ADC0/2 2 0/0 8 0xb002 0x20080001 +ADC0/3 3 0/2 7 0xb003 0x20070001 +ADC0/4 4 0/1 6 0xb004 0x20060001 +ADC0/5 5 0/3 5 0xb005 0x20050001 +ADC0/6 6 0/5 12 0xb006 0x200c0001 +ADC0/7 7 0/4 11 0xb007 0x200b0001 + +ADC1/0 8 1/6 4 0xb008 0x20040001 +ADC1/1 9 1/7 3 0xb009 0x20030001 +ADC1/2 10 1/1 0 0xb00a 0x20000001 +ADC1/3 11 1/0 2 0xb00b 0x20020001 +ADC1/4 12 1/3 1 0xb00c 0x20010001 +ADC1/5 13 -/- -- 0xb00d 0x200f0001 +ADC1/6 14 1/5 13 0xb00e 0x200d0001 +ADC1/7 15 1/4 14 0xb00f 0x200e0001 + +realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +mapAPV 10 9 8 7 6 5 12 11 4 3 0 2 1 - 13 14 + +Backplane 4 +=========== + +ADC0/0 0 0/6 14 0xb000 0x200e0001 +ADC0/1 1 0/7 13 0xb001 0x200d0001 +ADC0/2 2 -/- -- 0xb002 0x200f0001 +ADC0/3 3 0/2 1 0xb003 0x20010001 +ADC0/4 4 0/1 2 0xb004 0x20020001 +ADC0/5 5 0/3 0 0xb005 0x20000001 +ADC0/6 6 0/5 3 0xb006 0x20030001 +ADC0/7 7 0/4 4 0xb007 0x20040001 + +ADC1/0 8 1/6 11 0xb008 0x200b0001 +ADC1/1 9 1/7 12 0xb009 0x200c0001 +ADC1/2 10 1/1 5 0xb00a 0x20050001 +ADC1/3 11 1/0 6 0xb00b 0x20060001 +ADC1/4 12 1/3 7 0xb00c 0x20070001 +ADC1/5 13 1/2 8 0xb00d 0x20080001 +ADC1/6 14 1/5 9 0xb00e 0x20090001 +ADC1/7 15 1/4 10 0xb00f 0x200a0001 + +realADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +mapAPV 14 13 - 1 2 0 3 4 11 12 5 6 7 8 9 10 diff --git a/src/adc_channel_select.vhd b/src/adc_channel_select.vhd index 20e653b..743a41a 100644 --- a/src/adc_channel_select.vhd +++ b/src/adc_channel_select.vhd @@ -1,71 +1,76 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.adcmv3_components.all; entity adc_channel_select is - port( RESET_IN : in std_logic; - ADC_CLK_IN : in std_logic; - ADC_SEL_IN : in std_logic_vector(2 downto 0); - ADC_7_IN : in std_logic_vector(11 downto 0); - ADC_6_IN : in std_logic_vector(11 downto 0); - ADC_5_IN : in std_logic_vector(11 downto 0); - ADC_4_IN : in std_logic_vector(11 downto 0); - ADC_3_IN : in std_logic_vector(11 downto 0); - ADC_2_IN : in std_logic_vector(11 downto 0); - ADC_1_IN : in std_logic_vector(11 downto 0); - ADC_0_IN : in std_logic_vector(11 downto 0); - ADC_CH_OUT : out std_logic_vector(11 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + RESET_IN : in std_logic; + ADC_CLK_IN : in std_logic; + ADC_SEL_IN : in std_logic_vector(2 downto 0); + ADC_7_IN : in std_logic_vector(11 downto 0); + ADC_6_IN : in std_logic_vector(11 downto 0); + ADC_5_IN : in std_logic_vector(11 downto 0); + ADC_4_IN : in std_logic_vector(11 downto 0); + ADC_3_IN : in std_logic_vector(11 downto 0); + ADC_2_IN : in std_logic_vector(11 downto 0); + ADC_1_IN : in std_logic_vector(11 downto 0); + ADC_0_IN : in std_logic_vector(11 downto 0); + ADC_CH_OUT : out std_logic_vector(11 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of adc_channel_select is - -- Placer Directives +-- Placer Directives - -- normal signals - signal adc_ch : std_logic_vector(11 downto 0); - signal adc_sel : std_logic_vector(2 downto 0); - signal reset : std_logic; +-- normal signals +signal adc_ch : std_logic_vector(11 downto 0); +signal adc_sel : std_logic_vector(2 downto 0); +signal reset : std_logic; - signal debug : std_logic_vector(15 downto 0); +signal debug : std_logic_vector(15 downto 0); -begin +begin -- Reset synchronizer THE_RESET_SYNC: state_sync -port map( STATE_A_IN => reset_in, - CLK_B_IN => adc_clk_in, - RESET_B_IN => '0', - STATE_B_OUT => reset - ); +port map( + STATE_A_IN => reset_in, + CLK_B_IN => adc_clk_in, + RESET_B_IN => '0', + STATE_B_OUT => reset +); -- select signals are from 100MHz clock domain! THE_SEL2_SYNC: state_sync -port map( STATE_A_IN => adc_sel_in(2), - CLK_B_IN => adc_clk_in, - RESET_B_IN => reset, - STATE_B_OUT => adc_sel(2) - ); +port map( + STATE_A_IN => adc_sel_in(2), + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset, + STATE_B_OUT => adc_sel(2) +); THE_SEL1_SYNC: state_sync -port map( STATE_A_IN => adc_sel_in(1), - CLK_B_IN => adc_clk_in, - RESET_B_IN => reset, - STATE_B_OUT => adc_sel(1) - ); +port map( + STATE_A_IN => adc_sel_in(1), + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset, + STATE_B_OUT => adc_sel(1) +); THE_SEL0_SYNC: state_sync -port map( STATE_A_IN => adc_sel_in(0), - CLK_B_IN => adc_clk_in, - RESET_B_IN => reset, - STATE_B_OUT => adc_sel(0) - ); +port map( + STATE_A_IN => adc_sel_in(0), + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset, + STATE_B_OUT => adc_sel(0) +); + - -- registered multiplexer THE_SEL_PROC: process( adc_clk_in ) begin @@ -74,18 +79,18 @@ begin adc_ch <= (others => '0'); else case adc_sel is - when b"000" => adc_ch <= adc_0_in; - when b"001" => adc_ch <= adc_1_in; - when b"010" => adc_ch <= adc_2_in; - when b"011" => adc_ch <= adc_3_in; - when b"100" => adc_ch <= adc_4_in; - when b"101" => adc_ch <= adc_5_in; - when b"110" => adc_ch <= adc_6_in; - when b"111" => adc_ch <= adc_7_in; - when others => adc_ch <= x"000"; -- never + when b"000" => adc_ch <= adc_0_in; + when b"001" => adc_ch <= adc_1_in; + when b"010" => adc_ch <= adc_2_in; + when b"011" => adc_ch <= adc_3_in; + when b"100" => adc_ch <= adc_4_in; + when b"101" => adc_ch <= adc_5_in; + when b"110" => adc_ch <= adc_6_in; + when b"111" => adc_ch <= adc_7_in; + when others => adc_ch <= x"000"; -- never end case; end if; - end if; + end if; end process THE_SEL_PROC; -- debug signals @@ -93,6 +98,6 @@ debug(15 downto 0) <= (others => '0'); -- output signals adc_ch_out <= adc_ch; -debug_out <= debug; +debug_out <= debug; -end behavioral; +end behavioral; diff --git a/src/adc_crossover.vhd b/src/adc_crossover.vhd index 870c990..2d970ea 100644 --- a/src/adc_crossover.vhd +++ b/src/adc_crossover.vhd @@ -7,51 +7,52 @@ library work; use work.adcmv3_components.all; entity adc_crossover is - port( CLK_APV_IN : in std_logic; -- APV 40MHz local clock - RESET_IN : in std_logic; -- general reset (100MHz) - -- ADC clock domain signals - ADC_CLK_IN : in std_logic; - ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse... - ADC_DATA_VALID_IN : in std_logic; - ADC_DATA_7_IN : in std_logic_vector(11 downto 0); - ADC_DATA_6_IN : in std_logic_vector(11 downto 0); - ADC_DATA_5_IN : in std_logic_vector(11 downto 0); - ADC_DATA_4_IN : in std_logic_vector(11 downto 0); - ADC_DATA_3_IN : in std_logic_vector(11 downto 0); - ADC_DATA_2_IN : in std_logic_vector(11 downto 0); - ADC_DATA_1_IN : in std_logic_vector(11 downto 0); - ADC_DATA_0_IN : in std_logic_vector(11 downto 0); - LEVEL_WR_OUT : out std_logic_vector(4 downto 0); - -- APV clock domain signals - APV_DATA_7_OUT : out std_logic_vector(11 downto 0); - APV_DATA_6_OUT : out std_logic_vector(11 downto 0); - APV_DATA_5_OUT : out std_logic_vector(11 downto 0); - APV_DATA_4_OUT : out std_logic_vector(11 downto 0); - APV_DATA_3_OUT : out std_logic_vector(11 downto 0); - APV_DATA_2_OUT : out std_logic_vector(11 downto 0); - APV_DATA_1_OUT : out std_logic_vector(11 downto 0); - APV_DATA_0_OUT : out std_logic_vector(11 downto 0); - APV_DATA_VALID_OUT : out std_logic; - LEVEL_RD_OUT : out std_logic_vector(4 downto 0); - -- Debug signals - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); +port( + CLK_APV_IN : in std_logic; -- APV 40MHz local clock + RESET_IN : in std_logic; -- general reset (100MHz) + -- ADC clock domain signals + ADC_CLK_IN : in std_logic; + ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse... + ADC_DATA_VALID_IN : in std_logic; + ADC_DATA_7_IN : in std_logic_vector(11 downto 0); + ADC_DATA_6_IN : in std_logic_vector(11 downto 0); + ADC_DATA_5_IN : in std_logic_vector(11 downto 0); + ADC_DATA_4_IN : in std_logic_vector(11 downto 0); + ADC_DATA_3_IN : in std_logic_vector(11 downto 0); + ADC_DATA_2_IN : in std_logic_vector(11 downto 0); + ADC_DATA_1_IN : in std_logic_vector(11 downto 0); + ADC_DATA_0_IN : in std_logic_vector(11 downto 0); + LEVEL_WR_OUT : out std_logic_vector(4 downto 0); + -- APV clock domain signals + APV_DATA_7_OUT : out std_logic_vector(11 downto 0); + APV_DATA_6_OUT : out std_logic_vector(11 downto 0); + APV_DATA_5_OUT : out std_logic_vector(11 downto 0); + APV_DATA_4_OUT : out std_logic_vector(11 downto 0); + APV_DATA_3_OUT : out std_logic_vector(11 downto 0); + APV_DATA_2_OUT : out std_logic_vector(11 downto 0); + APV_DATA_1_OUT : out std_logic_vector(11 downto 0); + APV_DATA_0_OUT : out std_logic_vector(11 downto 0); + APV_DATA_VALID_OUT : out std_logic; + LEVEL_RD_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(31 downto 0) +); end; architecture behavioral of adc_crossover is - signal debug : std_logic_vector(31 downto 0); - - signal fifo_rd_level : std_logic_vector(4 downto 0); - signal fifo_wr_level : std_logic_vector(4 downto 0); - signal next_fifo_rd_ena : std_logic; - signal fifo_rd_ena : std_logic; - signal next_fifo_wr_ena : std_logic; - signal fifo_wr_ena : std_logic; - signal next_reset : std_logic; - signal reset : std_logic; - signal apv_data_valid : std_logic_vector(2 downto 0); - +signal debug : std_logic_vector(31 downto 0); + +signal fifo_rd_level : std_logic_vector(4 downto 0); +signal fifo_wr_level : std_logic_vector(4 downto 0); +signal next_fifo_rd_ena : std_logic; +signal fifo_rd_ena : std_logic; +signal next_fifo_wr_ena : std_logic; +signal fifo_wr_ena : std_logic; +signal next_reset : std_logic; +signal reset : std_logic; +signal apv_data_valid : std_logic_vector(2 downto 0); + begin --------------------------------------------------------------------------- @@ -66,27 +67,28 @@ debug(31 downto 0) <= (others => '0'); next_reset <= reset_in or not adc_data_valid_in; THE_RESET_STATE_SYNC: state_sync -port map( STATE_A_IN => next_reset, - CLK_B_IN => clk_apv_in, - RESET_B_IN => '0', - STATE_B_OUT => reset - ); +port map( + STATE_A_IN => next_reset, + CLK_B_IN => clk_apv_in, + RESET_B_IN => '0', + STATE_B_OUT => reset +); --------------------------------------------------------------------------- --- Crossover fifo for ADC +-- Crossover fifo for ADC --------------------------------------------------------------------------- next_fifo_wr_ena <= adc_ce_in and adc_data_valid_in; next_fifo_rd_ena <= '1' when ( fifo_rd_level > b"0_0101" ) else '0'; -SYNC_WRCLK_PROC: process( adc_clk_in ) +SYNC_WRCLK_PROC: process( adc_clk_in ) begin if( rising_edge(adc_clk_in) ) then fifo_wr_ena <= next_fifo_wr_ena; end if; end process SYNC_WRCLK_PROC; -SYNC_RDCLK_PROC: process( clk_apv_in ) +SYNC_RDCLK_PROC: process( clk_apv_in ) begin if( rising_edge(clk_apv_in) ) then fifo_rd_ena <= next_fifo_rd_ena; @@ -95,33 +97,34 @@ begin end process SYNC_RDCLK_PROC; THE_CROSSOVER: crossover -port map( DATA(95 downto 84) => adc_data_7_in, - DATA(83 downto 72) => adc_data_6_in, - DATA(71 downto 60) => adc_data_5_in, - DATA(59 downto 48) => adc_data_4_in, - DATA(47 downto 36) => adc_data_3_in, - DATA(35 downto 24) => adc_data_2_in, - DATA(23 downto 12) => adc_data_1_in, - DATA(11 downto 0) => adc_data_0_in, - WRCLOCK => adc_clk_in, - RDCLOCK => clk_apv_in, - WREN => fifo_wr_ena, - RDEN => fifo_rd_ena, - RESET => reset, -- this is an async clear input! - RPRESET => '0', -- not needed, as OR'ed with RESET - Q(95 downto 84) => apv_data_7_out, - Q(83 downto 72) => apv_data_6_out, - Q(71 downto 60) => apv_data_5_out, - Q(59 downto 48) => apv_data_4_out, - Q(47 downto 36) => apv_data_3_out, - Q(35 downto 24) => apv_data_2_out, - Q(23 downto 12) => apv_data_1_out, - Q(11 downto 0) => apv_data_0_out, - WCNT => fifo_wr_level, - RCNT => fifo_rd_level, - EMPTY => open, - FULL => open - ); +port map( + DATA(95 downto 84) => adc_data_7_in, + DATA(83 downto 72) => adc_data_6_in, + DATA(71 downto 60) => adc_data_5_in, + DATA(59 downto 48) => adc_data_4_in, + DATA(47 downto 36) => adc_data_3_in, + DATA(35 downto 24) => adc_data_2_in, + DATA(23 downto 12) => adc_data_1_in, + DATA(11 downto 0) => adc_data_0_in, + WRCLOCK => adc_clk_in, + RDCLOCK => clk_apv_in, + WREN => fifo_wr_ena, + RDEN => fifo_rd_ena, + RESET => reset, -- this is an async clear input! + RPRESET => '0', -- not needed, as OR'ed with RESET + Q(95 downto 84) => apv_data_7_out, + Q(83 downto 72) => apv_data_6_out, + Q(71 downto 60) => apv_data_5_out, + Q(59 downto 48) => apv_data_4_out, + Q(47 downto 36) => apv_data_3_out, + Q(35 downto 24) => apv_data_2_out, + Q(23 downto 12) => apv_data_1_out, + Q(11 downto 0) => apv_data_0_out, + WCNT => fifo_wr_level, + RCNT => fifo_rd_level, + EMPTY => open, + FULL => open +); --------------------------------------------------------------------------- diff --git a/src/adc_data_handler_new.vhd b/src/adc_data_handler_new.vhd index d4b7a17..772a531 100644 --- a/src/adc_data_handler_new.vhd +++ b/src/adc_data_handler_new.vhd @@ -1,239 +1,254 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.adcmv3_components.all; entity adc_data_handler_new is - port( RESET_IN : in std_logic; - ADC_LCLK_IN : in std_logic; -- LCLK from ADC - ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC - ADC_CHNL_IN : in std_logic_vector(7 downto 0); - PLL_CTRL_IN : in std_logic_vector(3 downto 0); - ADC_DATA7_OUT : out std_logic_vector(11 downto 0); - ADC_DATA6_OUT : out std_logic_vector(11 downto 0); - ADC_DATA5_OUT : out std_logic_vector(11 downto 0); - ADC_DATA4_OUT : out std_logic_vector(11 downto 0); - ADC_DATA3_OUT : out std_logic_vector(11 downto 0); - ADC_DATA2_OUT : out std_logic_vector(11 downto 0); - ADC_DATA1_OUT : out std_logic_vector(11 downto 0); - ADC_DATA0_OUT : out std_logic_vector(11 downto 0); - ADC_CE_OUT : out std_logic; - ADC_VALID_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + RESET_IN : in std_logic; + ADC_LCLK_IN : in std_logic; -- LCLK from ADC + ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC + ADC_CHNL_IN : in std_logic_vector(7 downto 0); + PLL_CTRL_IN : in std_logic_vector(3 downto 0); + ADC_DATA7_OUT : out std_logic_vector(11 downto 0); + ADC_DATA6_OUT : out std_logic_vector(11 downto 0); + ADC_DATA5_OUT : out std_logic_vector(11 downto 0); + ADC_DATA4_OUT : out std_logic_vector(11 downto 0); + ADC_DATA3_OUT : out std_logic_vector(11 downto 0); + ADC_DATA2_OUT : out std_logic_vector(11 downto 0); + ADC_DATA1_OUT : out std_logic_vector(11 downto 0); + ADC_DATA0_OUT : out std_logic_vector(11 downto 0); + ADC_CE_OUT : out std_logic; + ADC_VALID_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of adc_data_handler_new is - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of behavioral : architecture is "ADC_DATA_HANDLER_group"; - - -- normal signals - signal adc_adclk_vec : std_logic_vector(0 downto 0); - signal adc_adclk : std_logic_vector(1 downto 0); - - signal adc_ch_7_mux : std_logic_vector(1 downto 0); - signal adc_ch_6_mux : std_logic_vector(1 downto 0); - signal adc_ch_5_mux : std_logic_vector(1 downto 0); - signal adc_ch_4_mux : std_logic_vector(1 downto 0); - signal adc_ch_3_mux : std_logic_vector(1 downto 0); - signal adc_ch_2_mux : std_logic_vector(1 downto 0); - signal adc_ch_1_mux : std_logic_vector(1 downto 0); - signal adc_ch_0_mux : std_logic_vector(1 downto 0); - - signal last_adc_7_ch : std_logic_vector(11 downto 0); - signal last_adc_6_ch : std_logic_vector(11 downto 0); - signal last_adc_5_ch : std_logic_vector(11 downto 0); - signal last_adc_4_ch : std_logic_vector(11 downto 0); - signal last_adc_3_ch : std_logic_vector(11 downto 0); - signal last_adc_2_ch : std_logic_vector(11 downto 0); - signal last_adc_1_ch : std_logic_vector(11 downto 0); - signal last_adc_0_ch : std_logic_vector(11 downto 0); - - signal buf_adc_7_ch : std_logic_vector(11 downto 0); - signal buf_adc_6_ch : std_logic_vector(11 downto 0); - signal buf_adc_5_ch : std_logic_vector(11 downto 0); - signal buf_adc_4_ch : std_logic_vector(11 downto 0); - signal buf_adc_3_ch : std_logic_vector(11 downto 0); - signal buf_adc_2_ch : std_logic_vector(11 downto 0); - signal buf_adc_1_ch : std_logic_vector(11 downto 0); - signal buf_adc_0_ch : std_logic_vector(11 downto 0); - - signal realstore : std_logic_vector(3 downto 0); - signal next_recstore : std_logic; - signal recstore : std_logic_vector(3 downto 0); - - signal reset : std_logic; -- synchronized to 240MHz local clock - - signal input_delay : std_logic_vector(3 downto 0); - - signal bitcounter : std_logic_vector(2 downto 0); - signal synccounter : std_logic_vector(2 downto 0); - signal next_ce_inc : std_logic; - signal ce_inc : std_logic; - signal next_ce_dec : std_logic; - signal ce_dec : std_logic; - signal next_sync_low : std_logic; - signal sync_low : std_logic; - signal next_sync_high : std_logic; - signal sync_high : std_logic; - - signal debug : std_logic_vector(15 downto 0); - -begin +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of behavioral : architecture is "ADC_DATA_HANDLER_group"; + +-- normal signals +signal adc_adclk_vec : std_logic_vector(0 downto 0); +signal adc_adclk : std_logic_vector(1 downto 0); + +signal adc_ch_7_mux : std_logic_vector(1 downto 0); +signal adc_ch_6_mux : std_logic_vector(1 downto 0); +signal adc_ch_5_mux : std_logic_vector(1 downto 0); +signal adc_ch_4_mux : std_logic_vector(1 downto 0); +signal adc_ch_3_mux : std_logic_vector(1 downto 0); +signal adc_ch_2_mux : std_logic_vector(1 downto 0); +signal adc_ch_1_mux : std_logic_vector(1 downto 0); +signal adc_ch_0_mux : std_logic_vector(1 downto 0); + +signal last_adc_7_ch : std_logic_vector(11 downto 0); +signal last_adc_6_ch : std_logic_vector(11 downto 0); +signal last_adc_5_ch : std_logic_vector(11 downto 0); +signal last_adc_4_ch : std_logic_vector(11 downto 0); +signal last_adc_3_ch : std_logic_vector(11 downto 0); +signal last_adc_2_ch : std_logic_vector(11 downto 0); +signal last_adc_1_ch : std_logic_vector(11 downto 0); +signal last_adc_0_ch : std_logic_vector(11 downto 0); + +signal buf_adc_7_ch : std_logic_vector(11 downto 0); +signal buf_adc_6_ch : std_logic_vector(11 downto 0); +signal buf_adc_5_ch : std_logic_vector(11 downto 0); +signal buf_adc_4_ch : std_logic_vector(11 downto 0); +signal buf_adc_3_ch : std_logic_vector(11 downto 0); +signal buf_adc_2_ch : std_logic_vector(11 downto 0); +signal buf_adc_1_ch : std_logic_vector(11 downto 0); +signal buf_adc_0_ch : std_logic_vector(11 downto 0); + +signal realstore : std_logic_vector(3 downto 0); +signal next_recstore : std_logic; +signal recstore : std_logic_vector(3 downto 0); + +signal reset : std_logic; -- synchronized to 240MHz local clock + +signal input_delay : std_logic_vector(3 downto 0); + +signal bitcounter : std_logic_vector(2 downto 0); +signal synccounter : std_logic_vector(2 downto 0); +signal next_ce_inc : std_logic; +signal ce_inc : std_logic; +signal next_ce_dec : std_logic; +signal ce_dec : std_logic; +signal next_sync_low : std_logic; +signal sync_low : std_logic; +signal next_sync_high : std_logic; +signal sync_high : std_logic; + +signal debug : std_logic_vector(15 downto 0); + +begin -- input delay for IDDR, 50ps / unit input_delay <= pll_ctrl_in; --- Reset synchronizer +-- Reset synchronizer THE_RESET_SYNC: state_sync -port map( STATE_A_IN => reset_in, - CLK_B_IN => adc_lclk_in, - RESET_B_IN => '0', - STATE_B_OUT => reset - ); +port map( + STATE_A_IN => reset_in, + CLK_B_IN => adc_lclk_in, + RESET_B_IN => '0', + STATE_B_OUT => reset +); -- We have to reconstruct the ADC word clock (ADCLK). --- Mind the vector! -adc_adclk_vec(0) <= adc_adclk_in; - -THE_ADC_ADCLK_IN: adc_ch_in -port map( DEL => input_delay, - ECLK => adc_lclk_in, - SCLK => adc_lclk_in, - RST => '0', - DATA => adc_adclk_vec, - Q => adc_adclk - ); +-- Mind the vector! +adc_adclk_vec(0) <= adc_adclk_in; + +THE_ADC_ADCLK_IN: adc_ch_in +port map( + DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_adclk_vec, + Q => adc_adclk +); -- First group of channels (0 and 1) -THE_DIN_0: adc_ch_in -port map( DEL => input_delay, - ECLK => adc_lclk_in, - SCLK => adc_lclk_in, - RST => '0', - DATA => adc_chnl_in(0 downto 0), - Q => adc_ch_0_mux - ); -THE_DIN_1: adc_ch_in -port map( DEL => input_delay, - ECLK => adc_lclk_in, - SCLK => adc_lclk_in, - RST => '0', - DATA => adc_chnl_in(1 downto 1), - Q => adc_ch_1_mux - ); +THE_DIN_0: adc_ch_in +port map( + DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(0 downto 0), + Q => adc_ch_0_mux +); +THE_DIN_1: adc_ch_in +port map( + DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(1 downto 1), + Q => adc_ch_1_mux +); THE_ADC_0_1_CH: adc_twochannels -port map( CLK_IN => adc_lclk_in, - RESET_IN => reset, - CLOCK_IN => adc_adclk, - DATA_0_IN => adc_ch_0_mux, - DATA_1_IN => adc_ch_1_mux, - DATA_0_OUT => last_adc_0_ch, - DATA_1_OUT => last_adc_1_ch, - STORE_OUT => realstore(0), - SWAP_OUT => open, - CLOCK_OUT => open, - DEBUG_OUT => open - ); +port map( + CLK_IN => adc_lclk_in, + RESET_IN => reset, + CLOCK_IN => adc_adclk, + DATA_0_IN => adc_ch_0_mux, + DATA_1_IN => adc_ch_1_mux, + DATA_0_OUT => last_adc_0_ch, + DATA_1_OUT => last_adc_1_ch, + STORE_OUT => realstore(0), + SWAP_OUT => open, + CLOCK_OUT => open, + DEBUG_OUT => open +); -- Second group of channels (2 and 3) -THE_DIN_2: adc_ch_in -port map( DEL => input_delay, - ECLK => adc_lclk_in, - SCLK => adc_lclk_in, - RST => '0', - DATA => adc_chnl_in(2 downto 2), - Q => adc_ch_2_mux - ); -THE_DIN_3: adc_ch_in -port map( DEL => input_delay, - ECLK => adc_lclk_in, - SCLK => adc_lclk_in, - RST => '0', - DATA => adc_chnl_in(3 downto 3), - Q => adc_ch_3_mux - ); +THE_DIN_2: adc_ch_in +port map( + DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(2 downto 2), + Q => adc_ch_2_mux +); +THE_DIN_3: adc_ch_in +port map( + DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(3 downto 3), + Q => adc_ch_3_mux +); THE_ADC_2_3_CH: adc_twochannels -port map( CLK_IN => adc_lclk_in, - RESET_IN => reset, - CLOCK_IN => adc_adclk, - DATA_0_IN => adc_ch_2_mux, - DATA_1_IN => adc_ch_3_mux, - DATA_0_OUT => last_adc_2_ch, - DATA_1_OUT => last_adc_3_ch, - STORE_OUT => realstore(1), - SWAP_OUT => open, - CLOCK_OUT => open, - DEBUG_OUT => open - ); +port map( + CLK_IN => adc_lclk_in, + RESET_IN => reset, + CLOCK_IN => adc_adclk, + DATA_0_IN => adc_ch_2_mux, + DATA_1_IN => adc_ch_3_mux, + DATA_0_OUT => last_adc_2_ch, + DATA_1_OUT => last_adc_3_ch, + STORE_OUT => realstore(1), + SWAP_OUT => open, + CLOCK_OUT => open, + DEBUG_OUT => open +); -- Third group of channels (4 and 5) -THE_DIN_4: adc_ch_in -port map( DEL => input_delay, - ECLK => adc_lclk_in, - SCLK => adc_lclk_in, - RST => '0', - DATA => adc_chnl_in(4 downto 4), - Q => adc_ch_4_mux - ); -THE_DIN_5: adc_ch_in -port map( DEL => input_delay, - ECLK => adc_lclk_in, - SCLK => adc_lclk_in, - RST => '0', - DATA => adc_chnl_in(5 downto 5), - Q => adc_ch_5_mux - ); +THE_DIN_4: adc_ch_in +port map( + DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(4 downto 4), + Q => adc_ch_4_mux +); +THE_DIN_5: adc_ch_in +port map( + DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(5 downto 5), + Q => adc_ch_5_mux +); THE_ADC_4_5_CH: adc_twochannels -port map( CLK_IN => adc_lclk_in, - RESET_IN => reset, - CLOCK_IN => adc_adclk, - DATA_0_IN => adc_ch_4_mux, - DATA_1_IN => adc_ch_5_mux, - DATA_0_OUT => last_adc_4_ch, - DATA_1_OUT => last_adc_5_ch, - STORE_OUT => realstore(2), - SWAP_OUT => open, - CLOCK_OUT => open, - DEBUG_OUT => open - ); +port map( + CLK_IN => adc_lclk_in, + RESET_IN => reset, + CLOCK_IN => adc_adclk, + DATA_0_IN => adc_ch_4_mux, + DATA_1_IN => adc_ch_5_mux, + DATA_0_OUT => last_adc_4_ch, + DATA_1_OUT => last_adc_5_ch, + STORE_OUT => realstore(2), + SWAP_OUT => open, + CLOCK_OUT => open, + DEBUG_OUT => open +); -- Fourth group of channels (6 and 7) -THE_DIN_6: adc_ch_in -port map( DEL => input_delay, - ECLK => adc_lclk_in, - SCLK => adc_lclk_in, - RST => '0', - DATA => adc_chnl_in(6 downto 6), - Q => adc_ch_6_mux - ); -THE_DIN_7: adc_ch_in -port map( DEL => input_delay, - ECLK => adc_lclk_in, - SCLK => adc_lclk_in, - RST => '0', - DATA => adc_chnl_in(7 downto 7), - Q => adc_ch_7_mux - ); +THE_DIN_6: adc_ch_in +port map( + DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(6 downto 6), + Q => adc_ch_6_mux +); +THE_DIN_7: adc_ch_in +port map( + DEL => input_delay, + ECLK => adc_lclk_in, + SCLK => adc_lclk_in, + RST => '0', + DATA => adc_chnl_in(7 downto 7), + Q => adc_ch_7_mux +); THE_ADC_6_7_CH: adc_twochannels -port map( CLK_IN => adc_lclk_in, - RESET_IN => reset, - CLOCK_IN => adc_adclk, - DATA_0_IN => adc_ch_6_mux, - DATA_1_IN => adc_ch_7_mux, - DATA_0_OUT => last_adc_6_ch, - DATA_1_OUT => last_adc_7_ch, - STORE_OUT => realstore(3), - SWAP_OUT => open, - CLOCK_OUT => open, - DEBUG_OUT => open - ); +port map( + CLK_IN => adc_lclk_in, + RESET_IN => reset, + CLOCK_IN => adc_adclk, + DATA_0_IN => adc_ch_6_mux, + DATA_1_IN => adc_ch_7_mux, + DATA_0_OUT => last_adc_6_ch, + DATA_1_OUT => last_adc_7_ch, + STORE_OUT => realstore(3), + SWAP_OUT => open, + CLOCK_OUT => open, + DEBUG_OUT => open +); -- Clock reconstruction (will only work if all four units work in perfect alignment) next_recstore <= '1' when ( realstore = b"1111" ) else '0'; @@ -308,18 +323,18 @@ end process THE_DATA_DELAY_PROC; -- output signals -adc_data7_out <= buf_adc_7_ch; -adc_data6_out <= buf_adc_6_ch; -adc_data5_out <= buf_adc_5_ch; -adc_data4_out <= buf_adc_4_ch; -adc_data3_out <= buf_adc_3_ch; -adc_data2_out <= buf_adc_2_ch; -adc_data1_out <= buf_adc_1_ch; -adc_data0_out <= buf_adc_0_ch; +adc_data7_out <= buf_adc_7_ch; +adc_data6_out <= buf_adc_6_ch; +adc_data5_out <= buf_adc_5_ch; +adc_data4_out <= buf_adc_4_ch; +adc_data3_out <= buf_adc_3_ch; +adc_data2_out <= buf_adc_2_ch; +adc_data1_out <= buf_adc_1_ch; +adc_data0_out <= buf_adc_0_ch; adc_ce_out <= recstore(3); adc_valid_out <= sync_high; - -debug_out(15 downto 0) <= debug; - -end behavioral; - \ No newline at end of file + +debug_out(15 downto 0) <= debug; + +end behavioral; + \ No newline at end of file diff --git a/src/adc_twochannels.vhd b/src/adc_twochannels.vhd index f48f729..c54e175 100644 --- a/src/adc_twochannels.vhd +++ b/src/adc_twochannels.vhd @@ -7,45 +7,46 @@ library work; use work.adcmv3_components.all; entity adc_twochannels is - port( CLK_IN : in std_logic; -- DDR bit clock - RESET_IN : in std_logic; - CLOCK_IN : in std_logic_vector(1 downto 0); -- word clock - DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one - DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two - DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one - DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two - STORE_OUT : out std_logic; - SWAP_OUT : out std_logic; - CLOCK_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_IN : in std_logic; -- DDR bit clock + RESET_IN : in std_logic; + CLOCK_IN : in std_logic_vector(1 downto 0); -- word clock + DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one + DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two + DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one + DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two + STORE_OUT : out std_logic; + SWAP_OUT : out std_logic; + CLOCK_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behaviour of adc_twochannels is - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of behaviour : architecture is "TWOCHANNELS_group"; - - type half_data_t is array (0 to 1) of std_logic_vector(5 downto 0); - signal qda : half_data_t; -- serial input data, raising edge - signal qdb : half_data_t; -- serial input data, falling edge - signal parda : half_data_t; -- parallel input data, raising edge - signal pardb : half_data_t; -- parallel input data, falling edge - signal qc : half_data_t; -- serial ADCLK signal, (0) raising edge, (1) falling edge - type full_data_t is array (0 to 1) of std_logic_vector(11 downto 0); - signal muxed : full_data_t; - signal data : full_data_t; - - signal next_store_a : std_logic; - signal store_a : std_logic; -- store serial data A to parallel temp register - signal next_store_b : std_logic; - signal store_b : std_logic; -- store serial data B to parallel temp register - signal check : std_logic; -- auxiliary signal for swapping - signal next_swap : std_logic; - signal swap : std_logic; -- swap half words before assembling - signal store : std_logic; -- assemble full word +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of behaviour : architecture is "TWOCHANNELS_group"; + +type half_data_t is array (0 to 1) of std_logic_vector(5 downto 0); +signal qda : half_data_t; -- serial input data, raising edge +signal qdb : half_data_t; -- serial input data, falling edge +signal parda : half_data_t; -- parallel input data, raising edge +signal pardb : half_data_t; -- parallel input data, falling edge +signal qc : half_data_t; -- serial ADCLK signal, (0) raising edge, (1) falling edge +type full_data_t is array (0 to 1) of std_logic_vector(11 downto 0); +signal muxed : full_data_t; +signal data : full_data_t; + +signal next_store_a : std_logic; +signal store_a : std_logic; -- store serial data A to parallel temp register +signal next_store_b : std_logic; +signal store_b : std_logic; -- store serial data B to parallel temp register +signal check : std_logic; -- auxiliary signal for swapping +signal next_swap : std_logic; +signal swap : std_logic; -- swap half words before assembling +signal store : std_logic; -- assemble full word begin @@ -84,11 +85,11 @@ begin if( store_a = '1' ) then parda(0) <= qda(0); parda(1) <= qda(1); - end if; + end if; if( store_b = '1' ) then pardb(0) <= qdb(0); pardb(1) <= qdb(1); - end if; + end if; end if; end process THE_PARALLEL_STORE_PROC; @@ -115,7 +116,7 @@ next_swap <= '1' when ( (store_a = '1') and (store_b = '0') and (check = '1') ) THE_SWAP_PROC: process( parda, pardb, swap ) begin case swap is - when '1' => -- first channel + when '1' => -- first channel muxed(0)(0) <= pardb(0)(5); muxed(0)(1) <= parda(0)(5); muxed(0)(2) <= pardb(0)(4); @@ -141,7 +142,7 @@ begin muxed(1)(9) <= parda(1)(1); muxed(1)(10) <= pardb(1)(0); muxed(1)(11) <= parda(1)(0); - when '0' => -- first channel + when '0' => -- first channel muxed(0)(0) <= parda(0)(5); muxed(0)(1) <= pardb(0)(5); muxed(0)(2) <= parda(0)(4); @@ -199,13 +200,5 @@ debug_out(13) <= store_b; debug_out(12) <= store_a; debug_out(11 downto 0) <= data(0); ---debug_out(15 downto 15) <= (others => '0'); ---debug_out(14) <= swap; ---debug_out(13) <= store_b; ---debug_out(12) <= store_a; ---debug_out(11 downto 6) <= parda(0); ---debug_out(5 downto 0) <= pardb(0); - - end behaviour; diff --git a/src/adcmv3.vhd b/src/adcmv3.vhd index 83a52c4..7f80ddf 100755 --- a/src/adcmv3.vhd +++ b/src/adcmv3.vhd @@ -7,257 +7,256 @@ use work.trb_net_std.all; use work.adcmv3_components.all; entity adcmv3 is - port( CLK100M : in std_logic; -- OK -- 100MHz LVDS clock - -- trigger inputs - EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers - -- APV stuff - APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock - APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock - APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out - APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out - APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active - APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA - APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL - ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers - APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock - APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock - APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out - APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out - APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active - APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA - APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL - ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers - -- ADC0 stuff - ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL - ADC0_RST : out std_logic; -- OK -- ADC reset signal - ADC0_PD : out std_logic; -- OK -- ADC powerdown signal - ADC0_CS : out std_logic; -- OK -- ADC /CS signal - ADC0_SDI : out std_logic; -- OK -- ADC serial data in - ADC0_SCK : out std_logic; -- OK -- ADC serial clock - ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock - ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock - ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams - -- ADC1 stuff - ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL - ADC1_RST : out std_logic; -- OK -- ADC reset signal - ADC1_PD : out std_logic; -- OK -- ADC powerdown signal - ADC1_CS : out std_logic; -- OK -- ADC /CS signal - ADC1_SDI : out std_logic; -- OK -- ADC serial data in - ADC1_SCK : out std_logic; -- OK -- ADC serial clock - ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock - ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock - ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams - -- uC connections - UC_RESET : in std_logic; -- OK -- uC reset, high active - UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot - -- SerDes pins - HDINN2 : in std_logic; -- highspeed INPUT - HDINP2 : in std_logic; -- - HDOUTN2 : out std_logic; -- highspeed OUTPUT - HDOUTP2 : out std_logic; -- - SD_PRESENT : in std_logic; -- OK -- Present signal from SFP - SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP - SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable - ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM - -- Backplane sense wires - BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane - BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane - BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane - BP_LED : out std_logic; -- OK -- backplane LED - -- LEDs - FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS - FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2) - FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1) - FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0) - FPGA_LED_PLL : out std_logic; -- OK -- PLL locked - FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED - -- 1Wire chips on APV FEs - APV0_1W : inout std_logic_vector(7 downto 0); - APV1_1W : inout std_logic_vector(7 downto 0); - -- SPI FlashROM connections - U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM - U_SPI_SCK : out std_logic; -- OK -- clock - U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM - U_SPI_SDO : in std_logic; -- OK -- connects to SO on the FlashROM - -- Debug connections - DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header - ); +port( CLK100M : in std_logic; -- OK -- 100MHz LVDS clock + -- trigger inputs + EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers + -- APV stuff + APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock + APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock + APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out + APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out + APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active + APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA + APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL + ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers + APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock + APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock + APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out + APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out + APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active + APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA + APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL + ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers + -- ADC0 stuff + ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL + ADC0_RST : out std_logic; -- OK -- ADC reset signal + ADC0_PD : out std_logic; -- OK -- ADC powerdown signal + ADC0_CS : out std_logic; -- OK -- ADC /CS signal + ADC0_SDI : out std_logic; -- OK -- ADC serial data in + ADC0_SCK : out std_logic; -- OK -- ADC serial clock + ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock + ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock + ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams + -- ADC1 stuff + ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL + ADC1_RST : out std_logic; -- OK -- ADC reset signal + ADC1_PD : out std_logic; -- OK -- ADC powerdown signal + ADC1_CS : out std_logic; -- OK -- ADC /CS signal + ADC1_SDI : out std_logic; -- OK -- ADC serial data in + ADC1_SCK : out std_logic; -- OK -- ADC serial clock + ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock + ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock + ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams + -- uC connections + UC_RESET : in std_logic; -- OK -- uC reset, high active + UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot + -- SerDes pins + HDINN2 : in std_logic; -- highspeed INPUT + HDINP2 : in std_logic; -- + HDOUTN2 : out std_logic; -- highspeed OUTPUT + HDOUTP2 : out std_logic; -- + SD_PRESENT : in std_logic; -- OK -- Present signal from SFP + SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP + SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable + ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM + -- Backplane sense wires + BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane + BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane + BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane + BP_LED : out std_logic; -- OK -- backplane LED + -- LEDs + FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS + FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2) + FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1) + FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0) + FPGA_LED_PLL : out std_logic; -- OK -- PLL locked + FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED + -- 1Wire chips on APV FEs + APV0_1W : inout std_logic_vector(7 downto 0); + APV1_1W : inout std_logic_vector(7 downto 0); + -- SPI FlashROM connections + U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM + U_SPI_SCK : out std_logic; -- OK -- clock + U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM + U_SPI_SDO : in std_logic; -- OK -- connects to SO on the FlashROM + -- Debug connections + DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header +); end; architecture adcmv3 of adcmv3 is --- Signals - -- Clock related signals - signal clk100m_locked : std_logic; -- not needed at the moment - signal sysclk : std_logic; -- clean 100MHz for distribution - - signal adc0_ce : std_logic; - signal adc0_valid : std_logic; - signal adc0_reset : std_logic; - signal adc0_powerdown : std_logic; - signal adc1_ce : std_logic; - signal adc1_valid : std_logic; - signal adc1_reset : std_logic; - signal adc1_powerdown : std_logic; - - signal clk_adc : std_logic; -- 40MHz for ADC operation - signal clk_apv : std_logic; -- 40MHz for APV operation (phase shiftable!) - signal clk40m_locked : std_logic; - signal clk40m_reset : std_logic; - - signal async_reset : std_logic; - - -- APV related signals - signal apv_sda_out : std_logic; -- APV SDA - signal apv_sda_in : std_logic; - signal apv_scl_out : std_logic; -- APV SCL - signal apv_scl_in : std_logic; - signal apv_trg : std_logic; -- real APV trigger signal - signal apv_sync : std_logic; -- artificial signal - signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame - signal apv0_reset : std_logic; - signal apv1_reset : std_logic; - signal apv_reset : std_logic; - signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8] - signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8] - - -- Control signals - signal ctrl_pll : std_logic_vector(15 downto 0); -- PLL control register - signal status_pll : std_logic_vector(15 downto 0); -- PLL status register - signal ctrl_trg : std_logic_vector(31 downto 0); -- TRG control register - signal ctrl_lvl : std_logic_vector(31 downto 0); -- LVL control register - - signal ctrl_bitlow : std_logic_vector(11 downto 0); -- BIT_LOW setting for APV digital header - signal ctrl_bithigh : std_logic_vector(11 downto 0); -- BIT_HIGH setting for APV digital header - signal ctrl_flatlow : std_logic_vector(11 downto 0); -- FLAT_LOW setting - signal ctrl_flathigh : std_logic_vector(11 downto 0); -- FLAT_HIGH setting - - signal maximum_trg : std_logic_vector(3 downto 0); - - signal raw_buf_full : std_logic; - signal eds_buf_full : std_logic; - signal eds_buf_level : std_logic_vector(4 downto 0); - - -- regIO data bus - signal regio_addr : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); - signal regio_read_enable : std_logic; - signal regio_write_enable : std_logic; - signal regio_data_wr : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); - signal regio_data_rd : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); - signal regio_dataready : std_logic; - signal regio_no_more_data : std_logic; - signal regio_write_ack : std_logic; - signal regio_unknown_addr : std_logic; - signal regio_timeout : std_logic; - - -- common status / control registers from RegIO - signal common_stat_reg : std_logic_vector(63 downto 0); - signal common_ctrl_reg : std_logic_vector(63 downto 0); - - -- user defined "quick'n'dirty" registers - signal simple_status : std_logic_vector(127 downto 0); - signal simple_control : std_logic_vector(63 downto 0); - - -- debug signals - signal test_reg : std_logic_vector(31 downto 0); - signal trbrich_debug : std_logic_vector(63 downto 0); - signal trgctrl_debug : std_logic_vector(63 downto 0); - signal slave_debug : std_logic_vector(63 downto 0); - signal fifo_debug : std_logic_vector(63 downto 0); - signal raw_buf_debug : std_logic_vector(63 downto 0); - - -- EDS / BUFFER signals (raw buf -> ped corr) - signal eds_data : std_logic_vector(39 downto 0); - signal eds_avail : std_logic; - signal eds_done : std_logic; - signal buf_addr : std_logic_vector(6 downto 0); - signal buf_done : std_logic; - signal buf_tick : std_logic_vector(15 downto 0); - signal buf_start : std_logic_vector(15 downto 0); - signal buf_ready : std_logic_vector(15 downto 0); -- just for debugging! - - type reg_38bit_t is array (0 to 15) of std_logic_vector(37 downto 0); - signal buf_data : reg_38bit_t; - - signal thr_addr : std_logic_vector(6 downto 0); - type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0); - signal thr_data : reg_18bit_t; - signal ped_data : reg_18bit_t; - - -- FIFO / DHDR signals (ped corr -> ipu stage) - signal dhdr_data : std_logic_vector(31 downto 0); - signal dhdr_length : std_logic_vector(15 downto 0); - signal dhdr_store : std_logic; - signal dhdr_buf_full : std_logic; - - signal fifo_start : std_logic; - signal fifo_done : std_logic; - signal fifo_we : std_logic_vector(15 downto 0); - type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0); - signal fifo_data : reg_40bit_t; - - -- APV control / status signals - type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0); - signal adc_ctrl_reg : reg_16bit_t; - signal adc_stat_reg : reg_16bit_t; - - signal debug : std_logic_vector(42 downto 0); - signal debug_q : std_logic_vector(42 downto 0); - signal debug_qq : std_logic_vector(42 downto 0); - signal debug_clk : std_logic; +-- Signals +-- Clock related signals +signal clk100m_locked : std_logic; -- not needed at the moment +signal sysclk : std_logic; -- clean 100MHz for distribution + +signal adc0_ce : std_logic; +signal adc0_valid : std_logic; +signal adc0_reset : std_logic; +signal adc0_powerdown : std_logic; +signal adc1_ce : std_logic; +signal adc1_valid : std_logic; +signal adc1_reset : std_logic; +signal adc1_powerdown : std_logic; + +signal clk_adc : std_logic; -- 40MHz for ADC operation +signal clk_apv : std_logic; -- 40MHz for APV operation (phase shiftable!) +signal clk40m_locked : std_logic; +signal clk40m_reset : std_logic; + +signal async_reset : std_logic; + +-- APV related signals +signal apv_sda_out : std_logic; -- APV SDA +signal apv_sda_in : std_logic; +signal apv_scl_out : std_logic; -- APV SCL +signal apv_scl_in : std_logic; +signal apv_trg : std_logic; -- real APV trigger signal +signal apv_sync : std_logic; -- artificial signal +signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame +signal apv0_reset : std_logic; +signal apv1_reset : std_logic; +signal apv_reset : std_logic; +signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8] +signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8] + +-- Control signals +signal ctrl_pll : std_logic_vector(15 downto 0); -- PLL control register +signal status_pll : std_logic_vector(15 downto 0); -- PLL status register +signal ctrl_trg : std_logic_vector(31 downto 0); -- TRG control register +signal ctrl_lvl : std_logic_vector(31 downto 0); -- LVL control register + +signal ctrl_bitlow : std_logic_vector(11 downto 0); -- BIT_LOW setting for APV digital header +signal ctrl_bithigh : std_logic_vector(11 downto 0); -- BIT_HIGH setting for APV digital header +signal ctrl_flatlow : std_logic_vector(11 downto 0); -- FLAT_LOW setting +signal ctrl_flathigh : std_logic_vector(11 downto 0); -- FLAT_HIGH setting + +signal maximum_trg : std_logic_vector(3 downto 0); + +signal raw_buf_full : std_logic; +signal eds_buf_full : std_logic; +signal eds_buf_level : std_logic_vector(4 downto 0); + +-- regIO data bus +signal regio_addr : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); +signal regio_read_enable : std_logic; +signal regio_write_enable : std_logic; +signal regio_data_wr : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); +signal regio_data_rd : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); +signal regio_dataready : std_logic; +signal regio_no_more_data : std_logic; +signal regio_write_ack : std_logic; +signal regio_unknown_addr : std_logic; +signal regio_timeout : std_logic; + +-- common status / control registers from RegIO +signal common_stat_reg : std_logic_vector(63 downto 0); +signal common_ctrl_reg : std_logic_vector(63 downto 0); + +-- user defined "quick'n'dirty" registers +signal simple_status : std_logic_vector(127 downto 0); +signal simple_control : std_logic_vector(63 downto 0); + +-- debug signals +signal test_reg : std_logic_vector(31 downto 0); +signal trbrich_debug : std_logic_vector(63 downto 0); +signal trgctrl_debug : std_logic_vector(63 downto 0); +signal slave_debug : std_logic_vector(63 downto 0); +signal fifo_debug : std_logic_vector(63 downto 0); +signal raw_buf_debug : std_logic_vector(63 downto 0); + +-- EDS / BUFFER signals (raw buf -> ped corr) +signal eds_data : std_logic_vector(39 downto 0); +signal eds_avail : std_logic; +signal eds_done : std_logic; +signal buf_addr : std_logic_vector(6 downto 0); +signal buf_done : std_logic; +signal buf_tick : std_logic_vector(15 downto 0); +signal buf_start : std_logic_vector(15 downto 0); +signal buf_ready : std_logic_vector(15 downto 0); -- just for debugging! + +type reg_38bit_t is array (0 to 15) of std_logic_vector(37 downto 0); +signal buf_data : reg_38bit_t; + +signal thr_addr : std_logic_vector(6 downto 0); +type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0); +signal thr_data : reg_18bit_t; +signal ped_data : reg_18bit_t; + +-- FIFO / DHDR signals (ped corr -> ipu stage) +signal dhdr_data : std_logic_vector(31 downto 0); +signal dhdr_length : std_logic_vector(15 downto 0); +signal dhdr_store : std_logic; +signal dhdr_buf_full : std_logic; + +signal fifo_start : std_logic; +signal fifo_done : std_logic; +signal fifo_we : std_logic_vector(15 downto 0); +signal fifo_space_req : std_logic_vector(11 downto 0); +type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0); +signal fifo_data : reg_40bit_t; + +-- APV control / status signals +type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0); +signal adc_ctrl_reg : reg_16bit_t; +signal adc_stat_reg : reg_16bit_t; + +signal debug : std_logic_vector(42 downto 0); +signal debug_q : std_logic_vector(42 downto 0); +signal debug_qq : std_logic_vector(42 downto 0); +signal debug_clk : std_logic; - -- LVL1 application interface - signal lvl1_trg_type : std_logic_vector(3 downto 0); - signal lvl1_trg_received : std_logic; - signal lvl1_trg_number : std_logic_vector(15 downto 0); - signal lvl1_trg_code : std_logic_vector(7 downto 0); - signal lvl1_trg_information : std_logic_vector(23 downto 0); - signal lvl1_error_pattern : std_logic_vector(31 downto 0); - signal lvl1_trg_release : std_logic; - signal lvl1_trg_missing : std_logic; - signal timing_trg_found : std_logic; - - -- IPU application interface - signal ipu_number : std_logic_vector(15 downto 0); - signal ipu_information : std_logic_vector(7 downto 0); - signal ipu_start_readout : std_logic; - signal ipu_data : std_logic_vector(31 downto 0); - signal ipu_dataready : std_logic; - signal ipu_readout_finished : std_logic; - signal ipu_read : std_logic; - signal ipu_length : std_logic_vector(15 downto 0); - signal ipu_error_pattern : std_logic_vector(31 downto 0); - - signal local_lvl1_counter : std_logic_vector(15 downto 0); - signal local_lvl2_counter : std_logic_vector(15 downto 0); - - -- ADC signals - type reg_12bit_t is array (0 to 15) of std_logic_vector(11 downto 0); - signal adc_raw_data : reg_12bit_t; -- ADC specific clock domain - signal adc_data : reg_12bit_t; -- common APV clock domain - - signal adc1_testdata : std_logic_vector(11 downto 0); - signal adc0_testdata : std_logic_vector(11 downto 0); - signal adc1_select : std_logic_vector(2 downto 0); - signal adc0_select : std_logic_vector(2 downto 0); - - -- input synchronizing - signal bp_sector_q : std_logic_vector(3 downto 0); - signal bp_sector_qq : std_logic_vector(3 downto 0); - signal bp_module_q : std_logic_vector(3 downto 0); - signal bp_module_qq : std_logic_vector(3 downto 0); - - signal lsm_state_bits : std_logic_vector(3 downto 0); - signal reset_by_trb : std_logic; - signal global_sync_reset : std_logic; - - signal adc0_iodelay : std_logic_vector(3 downto 0); - signal adc1_iodelay : std_logic_vector(3 downto 0); - - - --- Components - -- are now in adcmv2_components.vhd +-- LVL1 application interface +signal lvl1_trg_type : std_logic_vector(3 downto 0); +signal lvl1_trg_received : std_logic; +signal lvl1_trg_number : std_logic_vector(15 downto 0); +signal lvl1_trg_code : std_logic_vector(7 downto 0); +signal lvl1_trg_information : std_logic_vector(23 downto 0); +signal lvl1_error_pattern : std_logic_vector(31 downto 0); +signal lvl1_trg_release : std_logic; +signal lvl1_trg_missing : std_logic; +signal lvl1_int_trg_number : std_logic_vector(15 downto 0); +signal lvl1_int_trg_update : std_logic; +signal timing_trg_found : std_logic; + +-- IPU application interface +signal ipu_number : std_logic_vector(15 downto 0); +signal ipu_information : std_logic_vector(7 downto 0); +signal ipu_start_readout : std_logic; +signal ipu_data : std_logic_vector(31 downto 0); +signal ipu_dataready : std_logic; +signal ipu_readout_finished : std_logic; +signal ipu_read : std_logic; +signal ipu_length : std_logic_vector(15 downto 0); +signal ipu_error_pattern : std_logic_vector(31 downto 0); + +signal local_lvl1_counter : std_logic_vector(15 downto 0); +signal local_lvl2_counter : std_logic_vector(15 downto 0); + +-- ADC signals +type reg_12bit_t is array (0 to 15) of std_logic_vector(11 downto 0); +signal adc_raw_data : reg_12bit_t; -- ADC specific clock domain +signal adc_data : reg_12bit_t; -- common APV clock domain + +signal adc1_testdata : std_logic_vector(11 downto 0); +signal adc0_testdata : std_logic_vector(11 downto 0); +signal adc1_select : std_logic_vector(2 downto 0); +signal adc0_select : std_logic_vector(2 downto 0); + +-- input synchronizing +signal bp_sector_q : std_logic_vector(3 downto 0); +signal bp_sector_qq : std_logic_vector(3 downto 0); +signal bp_module_q : std_logic_vector(3 downto 0); +signal bp_module_qq : std_logic_vector(3 downto 0); + +signal lsm_state_bits : std_logic_vector(3 downto 0); +signal reset_by_trb : std_logic; +signal global_sync_reset : std_logic; + +signal adc0_iodelay : std_logic_vector(3 downto 0); +signal adc1_iodelay : std_logic_vector(3 downto 0); + begin @@ -272,13 +271,14 @@ async_reset <= uc_reset; -- uC reset pin -- Reset handler / spike surpression -- ---------------------------------------- THE_RESET_HANDLER: reset_handler -port map( CLEAR_IN => async_reset, - RESET_IN => '0', - CLK_IN => sysclk, - TRB_RESET_IN => reset_by_trb, - RESET_OUT => global_sync_reset, - DEBUG_OUT => open - ); +port map( + CLEAR_IN => async_reset, + RESET_IN => '0', + CLK_IN => sysclk, + TRB_RESET_IN => reset_by_trb, + RESET_OUT => global_sync_reset, + DEBUG_OUT => open +); ---------------------------------------- @@ -286,96 +286,114 @@ port map( CLEAR_IN => async_reset, ---------------------------------------- -- 100MHz PLL, generating 40MHz and phase shifted 40MHz THE_40M_PLL: PLL_40M -port map( CLK => clk100m, - RESET => clk40m_reset, - DPAMODE => '1', -- dynamic control - DPHASE0 => ctrl_pll(0), - DPHASE1 => ctrl_pll(1), - DPHASE2 => ctrl_pll(2), - DPHASE3 => ctrl_pll(3), - CLKOP => clk_apv, -- fixed phase, used for logic - CLKOS => clk_adc, -- phase adjustable, for ODDRXC only - LOCK => clk40m_locked - ); +port map( + CLK => clk100m, + RESET => clk40m_reset, + DPAMODE => '1', -- dynamic control + DPHASE0 => ctrl_pll(0), + DPHASE1 => ctrl_pll(1), + DPHASE2 => ctrl_pll(2), + DPHASE3 => ctrl_pll(3), + CLKOP => clk_apv, -- fixed phase, used for logic + CLKOS => clk_adc, -- phase adjustable, for ODDRXC only + LOCK => clk40m_locked +); clk40m_reset <= ctrl_pll(7); -- 100MHz DLL, used for clock injection delay removal THE_100M_DLL: dll_100m -port map( CLK => clk100m, - RESETN => '1', - ALUHOLD => '0', - CLKOP => sysclk, - CLKOS => open, - LOCK => clk100m_locked - ); +port map( + CLK => clk100m, + RESETN => '1', + ALUHOLD => '0', + CLKOP => sysclk, + CLKOS => open, + LOCK => clk100m_locked +); ---------------------------------------- -- TRB endpoint -- ---------------------------------------- THE_RICH_TRB: rich_trb -port map( CLK100M_IN => clk100m, -- SerDes exclusive clock - SYSCLK_IN => sysclk, -- fabric clock - RESET_IN => global_sync_reset, - SD_RXD_P_IN => hdinp2, - SD_RXD_N_IN => hdinn2, - SD_TXD_P_OUT => hdoutp2, - SD_TXD_N_OUT => hdoutn2, - SD_PRESENT_IN => sd_present, - SD_TXDIS_OUT => sd_txdis, - SD_LOS_IN => sd_los, - ONEWIRE_INOUT => adcm_onewire, - -- common regIO status / control registers - COMMON_STAT_REG_IN => common_stat_reg, - COMMON_CTRL_REG_OUT => common_ctrl_reg, - -- status register input to regIO / control register output from regIO - CONTROL_OUT => simple_control, - STATUS_IN => simple_status, - -- LVL1 signals - LVL1_TRG_TYPE_OUT => lvl1_trg_type, - LVL1_TRG_RECEIVED_OUT => lvl1_trg_received, - LVL1_TRG_NUMBER_OUT => lvl1_trg_number, - LVL1_TRG_CODE_OUT => lvl1_trg_code, - LVL1_TRG_INFORMATION_OUT => lvl1_trg_information, - LVL1_ERROR_PATTERN_IN => lvl1_error_pattern, - LVL1_TRG_RELEASE_IN => lvl1_trg_release, - TIMING_TRG_FOUND_IN => timing_trg_found, - -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) - IPU_NUMBER_OUT => ipu_number, - IPU_INFORMATION_OUT => ipu_information, - IPU_START_READOUT_OUT => ipu_start_readout, - IPU_DATA_IN => ipu_data, - IPU_DATAREADY_IN => ipu_dataready, - IPU_READOUT_FINISHED_IN => ipu_readout_finished, - IPU_READ_OUT => ipu_read, - IPU_LENGTH_IN => ipu_length, - IPU_ERROR_PATTERN_IN => ipu_error_pattern, - -- regIO bus - REGIO_ADDR_OUT => regio_addr, - REGIO_READ_ENABLE_OUT => regio_read_enable, - REGIO_WRITE_ENABLE_OUT => regio_write_enable, - REGIO_DATA_OUT => regio_data_wr, - REGIO_DATA_IN => regio_data_rd, - REGIO_DATAREADY_IN => regio_dataready, - REGIO_NO_MORE_DATA_IN => regio_no_more_data, - REGIO_WRITE_ACK_IN => regio_write_ack, - REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr, - REGIO_TIMEOUT_OUT => regio_timeout, - -- status LEDs - LED_LINK_STAT => fpga_led_link, - LED_LINK_TXD => fpga_led_txd, - LED_LINK_RXD => fpga_led_rxd, - LINK_BSM_OUT => lsm_state_bits, -- LinkStateMachine bits - RESET_OUT => reset_by_trb, - DEBUG => trbrich_debug --open - ); +port map( + CLK100M_IN => clk100m, -- SerDes exclusive clock + SYSCLK_IN => sysclk, -- fabric clock + RESET_IN => global_sync_reset, + SD_RXD_P_IN => hdinp2, + SD_RXD_N_IN => hdinn2, + SD_TXD_P_OUT => hdoutp2, + SD_TXD_N_OUT => hdoutn2, + SD_PRESENT_IN => sd_present, + SD_TXDIS_OUT => sd_txdis, + SD_LOS_IN => sd_los, + ONEWIRE_INOUT => adcm_onewire, + -- common regIO status / control registers + COMMON_STAT_REG_IN => common_stat_reg, + COMMON_CTRL_REG_OUT => common_ctrl_reg, + -- status register input to regIO / control register output from regIO + CONTROL_OUT => simple_control, + STATUS_IN => simple_status, + -- LVL1 signals + LVL1_TRG_TYPE_OUT => lvl1_trg_type, + LVL1_TRG_RECEIVED_OUT => lvl1_trg_received, + LVL1_TRG_NUMBER_OUT => lvl1_trg_number, + LVL1_TRG_CODE_OUT => lvl1_trg_code, + LVL1_TRG_INFORMATION_OUT => lvl1_trg_information, + LVL1_ERROR_PATTERN_IN => lvl1_error_pattern, + LVL1_TRG_RELEASE_IN => lvl1_trg_release, + LVL1_INT_TRG_NUMBER_OUT => lvl1_int_trg_number, -- internal trigger counter + LVL1_INT_TRG_UPDATE_OUT => lvl1_int_trg_update, -- update on internal trigger counter + TIMING_TRG_FOUND_IN => timing_trg_found, + -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) + IPU_NUMBER_OUT => ipu_number, + IPU_INFORMATION_OUT => ipu_information, + IPU_START_READOUT_OUT => ipu_start_readout, + IPU_DATA_IN => ipu_data, + IPU_DATAREADY_IN => ipu_dataready, + IPU_READOUT_FINISHED_IN => ipu_readout_finished, + IPU_READ_OUT => ipu_read, + IPU_LENGTH_IN => ipu_length, + IPU_ERROR_PATTERN_IN => ipu_error_pattern, + -- regIO bus + REGIO_ADDR_OUT => regio_addr, + REGIO_READ_ENABLE_OUT => regio_read_enable, + REGIO_WRITE_ENABLE_OUT => regio_write_enable, + REGIO_DATA_OUT => regio_data_wr, + REGIO_DATA_IN => regio_data_rd, + REGIO_DATAREADY_IN => regio_dataready, + REGIO_NO_MORE_DATA_IN => regio_no_more_data, + REGIO_WRITE_ACK_IN => regio_write_ack, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr, + REGIO_TIMEOUT_OUT => regio_timeout, + -- status LEDs + LED_LINK_STAT => fpga_led_link, + LED_LINK_TXD => fpga_led_txd, + LED_LINK_RXD => fpga_led_rxd, + LINK_BSM_OUT => lsm_state_bits, -- LinkStateMachine bits + RESET_OUT => reset_by_trb, + DEBUG => trbrich_debug --open +); + +-- common control register bit definitions +-- [31:24] --- +-- [23:16] fake timing trigger +-- [15] reboot FPGA +-- [14:11] --- +-- [10] reset sequence counter +-- [9:4] --- +-- [3] master reset, reset the whole endpoint +-- [2] empty IPU chain, reset IPU logic +-- [1] reset trigger logic +-- [0] reset frontends -- LVL1 error pattern, to be sent back to CTS with each trigger -lvl1_error_pattern(31 downto 22) <= (others => '0'); +lvl1_error_pattern(31 downto 23) <= (others => '0'); +lvl1_error_pattern(22) <= '0'; -- not configured lvl1_error_pattern(21) <= '0'; -- buffers almost full lvl1_error_pattern(20) <= '0'; -- buffers half full lvl1_error_pattern(19 downto 18) <= (others => '0'); -lvl1_error_pattern(17) <= '0'; -- lvl1_trg_missing; -- missing timing trigger +lvl1_error_pattern(17) <= '0'; -- missing timing trigger (done by Jan) lvl1_error_pattern(16) <= '0'; -- LVL1 tag mismatch with local counters (done by Jan) lvl1_error_pattern(15 downto 0) <= (others => '0'); @@ -447,7 +465,7 @@ ena_lvds(4) <= adc_on(6) or lvds_on(6); ena_lvds(5) <= adc_on(1) or lvds_on(1); ena_lvds(6) <= adc_on(7) or lvds_on(7); ena_lvds(7) <= adc_on(0) or lvds_on(0); - + enb_lvds(0) <= adc_on(13) or lvds_on(13); enb_lvds(1) <= adc_on(10) or lvds_on(10); enb_lvds(2) <= adc_on(12) or lvds_on(12); @@ -464,141 +482,142 @@ bp_led <= '1'; -- LED is against GND! -- internal slave bus -> slow control -- ---------------------------------------- THE_SLAVE_BUS: slave_bus -port map( CLK_IN => sysclk, - RESET_IN => global_sync_reset, - -- RegIO signals - REGIO_ADDR_IN => regio_addr, - REGIO_DATA_IN => regio_data_wr, - REGIO_DATA_OUT => regio_data_rd, - REGIO_READ_ENABLE_IN => regio_read_enable, - REGIO_WRITE_ENABLE_IN => regio_write_enable, - REGIO_TIMEOUT_IN => regio_timeout, - REGIO_DATAREADY_OUT => regio_dataready, - REGIO_WRITE_ACK_OUT => regio_write_ack, - REGIO_NO_MORE_DATA_OUT => regio_no_more_data, - REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr, - -- I2C connections - SDA_IN => apv_sda_in, - SDA_OUT => apv_sda_out, - SCL_IN => apv_scl_in, - SCL_OUT => apv_scl_out, - -- 1Wire connections - ONEWIRE_START_IN => '0', -- not used yet - ONEWIRE_INOUT(15 downto 8) => apv1_1w(7 downto 0), - ONEWIRE_INOUT(7 downto 0) => apv0_1w(7 downto 0), - BP_ONEWIRE_INOUT => bp_onewire, - -- SPI connections - SPI_CS_OUT => u_spi_cs, - SPI_SCK_OUT => u_spi_sck, - SPI_SDI_IN => u_spi_sdo, - SPI_SDO_OUT => u_spi_sdi, - -- ADC 0 SPI connections - SPI_ADC0_CS_OUT => adc0_cs, - SPI_ADC0_SCK_OUT => adc0_sck, - SPI_ADC0_SDO_OUT => adc0_sdi, - ADC0_PLL_LOCKED_IN => adc0_valid, - ADC0_PD_OUT => adc0_powerdown, - ADC0_RST_OUT => adc0_reset, - ADC0_DEL_OUT => adc0_iodelay, - ADC0_CLK_IN => clk_apv, - ADC0_DATA_IN => adc0_testdata, - ADC0_SEL_OUT => adc0_select, - APV0_RST_OUT => apv0_reset, - -- ADC 0 SPI connections - SPI_ADC1_CS_OUT => adc1_cs, - SPI_ADC1_SCK_OUT => adc1_sck, - SPI_ADC1_SDO_OUT => adc1_sdi, - ADC1_PLL_LOCKED_IN => adc1_valid, - ADC1_PD_OUT => adc1_powerdown, - ADC1_RST_OUT => adc1_reset, - ADC1_DEL_OUT => adc1_iodelay, - ADC1_CLK_IN => clk_apv, - ADC1_DATA_IN => adc1_testdata, - ADC1_SEL_OUT => adc1_select, - APV1_RST_OUT => apv1_reset, - -- backplane identifier - BACKPLANE_IN => bp_module_qq(2 downto 0), - -- pedestal interface - PED_ADDR_IN => buf_addr, - PED_DATA_0_OUT => ped_data(0), - PED_DATA_1_OUT => ped_data(1), - PED_DATA_2_OUT => ped_data(2), - PED_DATA_3_OUT => ped_data(3), - PED_DATA_4_OUT => ped_data(4), - PED_DATA_5_OUT => ped_data(5), - PED_DATA_6_OUT => ped_data(6), - PED_DATA_7_OUT => ped_data(7), - PED_DATA_8_OUT => ped_data(8), - PED_DATA_9_OUT => ped_data(9), - PED_DATA_10_OUT => ped_data(10), - PED_DATA_11_OUT => ped_data(11), - PED_DATA_12_OUT => ped_data(12), - PED_DATA_13_OUT => ped_data(13), - PED_DATA_14_OUT => ped_data(14), - PED_DATA_15_OUT => ped_data(15), - -- threshold interface - THR_ADDR_IN => thr_addr, - THR_DATA_0_OUT => thr_data(0), - THR_DATA_1_OUT => thr_data(1), - THR_DATA_2_OUT => thr_data(2), - THR_DATA_3_OUT => thr_data(3), - THR_DATA_4_OUT => thr_data(4), - THR_DATA_5_OUT => thr_data(5), - THR_DATA_6_OUT => thr_data(6), - THR_DATA_7_OUT => thr_data(7), - THR_DATA_8_OUT => thr_data(8), - THR_DATA_9_OUT => thr_data(9), - THR_DATA_10_OUT => thr_data(10), - THR_DATA_11_OUT => thr_data(11), - THR_DATA_12_OUT => thr_data(12), - THR_DATA_13_OUT => thr_data(13), - THR_DATA_14_OUT => thr_data(14), - THR_DATA_15_OUT => thr_data(15), - -- APV control / status - CTRL_0_OUT => adc_ctrl_reg(0), - CTRL_1_OUT => adc_ctrl_reg(1), - CTRL_2_OUT => adc_ctrl_reg(2), - CTRL_3_OUT => adc_ctrl_reg(3), - CTRL_4_OUT => adc_ctrl_reg(4), - CTRL_5_OUT => adc_ctrl_reg(5), - CTRL_6_OUT => adc_ctrl_reg(6), - CTRL_7_OUT => adc_ctrl_reg(7), - CTRL_8_OUT => adc_ctrl_reg(8), - CTRL_9_OUT => adc_ctrl_reg(9), - CTRL_10_OUT => adc_ctrl_reg(10), - CTRL_11_OUT => adc_ctrl_reg(11), - CTRL_12_OUT => adc_ctrl_reg(12), - CTRL_13_OUT => adc_ctrl_reg(13), - CTRL_14_OUT => adc_ctrl_reg(14), - CTRL_15_OUT => adc_ctrl_reg(15), - STAT_0_IN => adc_stat_reg(0), - STAT_1_IN => adc_stat_reg(1), - STAT_2_IN => adc_stat_reg(2), - STAT_3_IN => adc_stat_reg(3), - STAT_4_IN => adc_stat_reg(4), - STAT_5_IN => adc_stat_reg(5), - STAT_6_IN => adc_stat_reg(6), - STAT_7_IN => adc_stat_reg(7), - STAT_8_IN => adc_stat_reg(8), - STAT_9_IN => adc_stat_reg(9), - STAT_10_IN => adc_stat_reg(10), - STAT_11_IN => adc_stat_reg(11), - STAT_12_IN => adc_stat_reg(12), - STAT_13_IN => adc_stat_reg(13), - STAT_14_IN => adc_stat_reg(14), - STAT_15_IN => adc_stat_reg(15), - -- some control signals - CTRL_LVL_OUT => ctrl_lvl, - CTRL_TRG_OUT => ctrl_trg, - CTRL_PLL_OUT => ctrl_pll, - STATUS_PLL_IN => status_pll, - -- temporary stuff - TEST_REG_IN => test_reg, -- short cut - TEST_REG_OUT => test_reg, - -- Debug - DEBUG_OUT => slave_debug, --open - STAT => open - ); +port map( + CLK_IN => sysclk, + RESET_IN => global_sync_reset, + -- RegIO signals + REGIO_ADDR_IN => regio_addr, + REGIO_DATA_IN => regio_data_wr, + REGIO_DATA_OUT => regio_data_rd, + REGIO_READ_ENABLE_IN => regio_read_enable, + REGIO_WRITE_ENABLE_IN => regio_write_enable, + REGIO_TIMEOUT_IN => regio_timeout, + REGIO_DATAREADY_OUT => regio_dataready, + REGIO_WRITE_ACK_OUT => regio_write_ack, + REGIO_NO_MORE_DATA_OUT => regio_no_more_data, + REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr, + -- I2C connections + SDA_IN => apv_sda_in, + SDA_OUT => apv_sda_out, + SCL_IN => apv_scl_in, + SCL_OUT => apv_scl_out, + -- 1Wire connections + ONEWIRE_START_IN => '0', -- not used yet + ONEWIRE_INOUT(15 downto 8) => apv1_1w(7 downto 0), + ONEWIRE_INOUT(7 downto 0) => apv0_1w(7 downto 0), + BP_ONEWIRE_INOUT => bp_onewire, + -- SPI connections + SPI_CS_OUT => u_spi_cs, + SPI_SCK_OUT => u_spi_sck, + SPI_SDI_IN => u_spi_sdo, + SPI_SDO_OUT => u_spi_sdi, + -- ADC 0 SPI connections + SPI_ADC0_CS_OUT => adc0_cs, + SPI_ADC0_SCK_OUT => adc0_sck, + SPI_ADC0_SDO_OUT => adc0_sdi, + ADC0_PLL_LOCKED_IN => adc0_valid, + ADC0_PD_OUT => adc0_powerdown, + ADC0_RST_OUT => adc0_reset, + ADC0_DEL_OUT => adc0_iodelay, + ADC0_CLK_IN => clk_apv, + ADC0_DATA_IN => adc0_testdata, + ADC0_SEL_OUT => adc0_select, + APV0_RST_OUT => apv0_reset, + -- ADC 0 SPI connections + SPI_ADC1_CS_OUT => adc1_cs, + SPI_ADC1_SCK_OUT => adc1_sck, + SPI_ADC1_SDO_OUT => adc1_sdi, + ADC1_PLL_LOCKED_IN => adc1_valid, + ADC1_PD_OUT => adc1_powerdown, + ADC1_RST_OUT => adc1_reset, + ADC1_DEL_OUT => adc1_iodelay, + ADC1_CLK_IN => clk_apv, + ADC1_DATA_IN => adc1_testdata, + ADC1_SEL_OUT => adc1_select, + APV1_RST_OUT => apv1_reset, + -- backplane identifier + BACKPLANE_IN => bp_module_qq(2 downto 0), + -- pedestal interface + PED_ADDR_IN => buf_addr, + PED_DATA_0_OUT => ped_data(0), + PED_DATA_1_OUT => ped_data(1), + PED_DATA_2_OUT => ped_data(2), + PED_DATA_3_OUT => ped_data(3), + PED_DATA_4_OUT => ped_data(4), + PED_DATA_5_OUT => ped_data(5), + PED_DATA_6_OUT => ped_data(6), + PED_DATA_7_OUT => ped_data(7), + PED_DATA_8_OUT => ped_data(8), + PED_DATA_9_OUT => ped_data(9), + PED_DATA_10_OUT => ped_data(10), + PED_DATA_11_OUT => ped_data(11), + PED_DATA_12_OUT => ped_data(12), + PED_DATA_13_OUT => ped_data(13), + PED_DATA_14_OUT => ped_data(14), + PED_DATA_15_OUT => ped_data(15), + -- threshold interface + THR_ADDR_IN => thr_addr, + THR_DATA_0_OUT => thr_data(0), + THR_DATA_1_OUT => thr_data(1), + THR_DATA_2_OUT => thr_data(2), + THR_DATA_3_OUT => thr_data(3), + THR_DATA_4_OUT => thr_data(4), + THR_DATA_5_OUT => thr_data(5), + THR_DATA_6_OUT => thr_data(6), + THR_DATA_7_OUT => thr_data(7), + THR_DATA_8_OUT => thr_data(8), + THR_DATA_9_OUT => thr_data(9), + THR_DATA_10_OUT => thr_data(10), + THR_DATA_11_OUT => thr_data(11), + THR_DATA_12_OUT => thr_data(12), + THR_DATA_13_OUT => thr_data(13), + THR_DATA_14_OUT => thr_data(14), + THR_DATA_15_OUT => thr_data(15), + -- APV control / status + CTRL_0_OUT => adc_ctrl_reg(0), + CTRL_1_OUT => adc_ctrl_reg(1), + CTRL_2_OUT => adc_ctrl_reg(2), + CTRL_3_OUT => adc_ctrl_reg(3), + CTRL_4_OUT => adc_ctrl_reg(4), + CTRL_5_OUT => adc_ctrl_reg(5), + CTRL_6_OUT => adc_ctrl_reg(6), + CTRL_7_OUT => adc_ctrl_reg(7), + CTRL_8_OUT => adc_ctrl_reg(8), + CTRL_9_OUT => adc_ctrl_reg(9), + CTRL_10_OUT => adc_ctrl_reg(10), + CTRL_11_OUT => adc_ctrl_reg(11), + CTRL_12_OUT => adc_ctrl_reg(12), + CTRL_13_OUT => adc_ctrl_reg(13), + CTRL_14_OUT => adc_ctrl_reg(14), + CTRL_15_OUT => adc_ctrl_reg(15), + STAT_0_IN => adc_stat_reg(0), + STAT_1_IN => adc_stat_reg(1), + STAT_2_IN => adc_stat_reg(2), + STAT_3_IN => adc_stat_reg(3), + STAT_4_IN => adc_stat_reg(4), + STAT_5_IN => adc_stat_reg(5), + STAT_6_IN => adc_stat_reg(6), + STAT_7_IN => adc_stat_reg(7), + STAT_8_IN => adc_stat_reg(8), + STAT_9_IN => adc_stat_reg(9), + STAT_10_IN => adc_stat_reg(10), + STAT_11_IN => adc_stat_reg(11), + STAT_12_IN => adc_stat_reg(12), + STAT_13_IN => adc_stat_reg(13), + STAT_14_IN => adc_stat_reg(14), + STAT_15_IN => adc_stat_reg(15), + -- some control signals + CTRL_LVL_OUT => ctrl_lvl, + CTRL_TRG_OUT => ctrl_trg, + CTRL_PLL_OUT => ctrl_pll, + STATUS_PLL_IN => status_pll, + -- temporary stuff + TEST_REG_IN => test_reg, -- short cut + TEST_REG_OUT => test_reg, + -- Debug + DEBUG_OUT => slave_debug, --open + STAT => open +); -- PLL status register status_pll(15) <= clk100m_locked; @@ -679,420 +698,434 @@ lvds_on(0) <= adc_ctrl_reg(0)(1); -- IPU endpoint for data transport -- ---------------------------------------- THE_IPU_STAGE: ipu_fifo_stage -port map( CLK_IN => sysclk, - RESET_IN => global_sync_reset, - -- Slow control signals - SECTOR_IN => bp_sector_qq(2 downto 0), - MODULE_IN => bp_module_qq(2 downto 0), - -- IPU channel connections - IPU_NUMBER_IN => ipu_number, - IPU_INFORMATION_IN => ipu_information, - IPU_START_READOUT_IN => ipu_start_readout, - IPU_DATA_OUT => ipu_data, - IPU_DATAREADY_OUT => ipu_dataready, - IPU_READOUT_FINISHED_OUT => ipu_readout_finished, - IPU_READ_IN => ipu_read, - IPU_LENGTH_OUT => ipu_length, - IPU_ERROR_PATTERN_OUT => ipu_error_pattern, - LVL2_COUNTER_OUT => local_lvl2_counter, - -- DHDR buffer input - DHDR_DATA_IN => dhdr_data, - DHDR_LENGTH_IN => dhdr_length, - DHDR_STORE_IN => dhdr_store, - DHDR_BUF_FULL_OUT => dhdr_buf_full, - -- processed data input - FIFO_START_IN => fifo_start, - FIFO_0_DATA_IN => fifo_data(0), - FIFO_1_DATA_IN => fifo_data(1), - FIFO_2_DATA_IN => fifo_data(2), - FIFO_3_DATA_IN => fifo_data(3), - FIFO_4_DATA_IN => fifo_data(4), - FIFO_5_DATA_IN => fifo_data(5), - FIFO_6_DATA_IN => fifo_data(6), - FIFO_7_DATA_IN => fifo_data(7), - FIFO_8_DATA_IN => fifo_data(8), - FIFO_9_DATA_IN => fifo_data(9), - FIFO_10_DATA_IN => fifo_data(10), - FIFO_11_DATA_IN => fifo_data(11), - FIFO_12_DATA_IN => fifo_data(12), - FIFO_13_DATA_IN => fifo_data(13), - FIFO_14_DATA_IN => fifo_data(14), - FIFO_15_DATA_IN => fifo_data(15), - FIFO_WE_IN => fifo_we, - FIFO_DONE_IN => fifo_done, - -- Debug signals - DBG_BSM_OUT => open, - DBG_OUT => fifo_debug --open - ); +port map( + CLK_IN => sysclk, + RESET_IN => global_sync_reset, + -- Slow control signals + SECTOR_IN => bp_sector_qq(2 downto 0), + MODULE_IN => bp_module_qq(2 downto 0), + -- IPU channel connections + IPU_NUMBER_IN => ipu_number, + IPU_INFORMATION_IN => ipu_information, + IPU_START_READOUT_IN => ipu_start_readout, + IPU_DATA_OUT => ipu_data, + IPU_DATAREADY_OUT => ipu_dataready, + IPU_READOUT_FINISHED_OUT => ipu_readout_finished, + IPU_READ_IN => ipu_read, + IPU_LENGTH_OUT => ipu_length, + IPU_ERROR_PATTERN_OUT => ipu_error_pattern, + LVL2_COUNTER_OUT => local_lvl2_counter, + -- DHDR buffer input + DHDR_DATA_IN => dhdr_data, + DHDR_LENGTH_IN => dhdr_length, + DHDR_STORE_IN => dhdr_store, + DHDR_BUF_FULL_OUT => dhdr_buf_full, + -- processed data input + FIFO_SPACE_REQ_IN => fifo_space_req, + FIFO_START_IN => fifo_start, + FIFO_0_DATA_IN => fifo_data(0), + FIFO_1_DATA_IN => fifo_data(1), + FIFO_2_DATA_IN => fifo_data(2), + FIFO_3_DATA_IN => fifo_data(3), + FIFO_4_DATA_IN => fifo_data(4), + FIFO_5_DATA_IN => fifo_data(5), + FIFO_6_DATA_IN => fifo_data(6), + FIFO_7_DATA_IN => fifo_data(7), + FIFO_8_DATA_IN => fifo_data(8), + FIFO_9_DATA_IN => fifo_data(9), + FIFO_10_DATA_IN => fifo_data(10), + FIFO_11_DATA_IN => fifo_data(11), + FIFO_12_DATA_IN => fifo_data(12), + FIFO_13_DATA_IN => fifo_data(13), + FIFO_14_DATA_IN => fifo_data(14), + FIFO_15_DATA_IN => fifo_data(15), + FIFO_WE_IN => fifo_we, + FIFO_DONE_IN => fifo_done, + -- Debug signals + DBG_BSM_OUT => open, + DBG_OUT => fifo_debug --open +); ---------------------------------------- -- Data processing unit -- ---------------------------------------- THE_PED_CORR_STAGE: ped_corr_ctrl -port map( CLK_IN => sysclk, - RESET_IN => global_sync_reset, - EDS_DATA_IN => eds_data, - EDS_AVAIL_IN => eds_avail, - EDS_DONE_OUT => eds_done, - EVT_TYPE_IN => b"000", -- BUG - -- DHDR information -- to next stage - DHDR_DATA_OUT => dhdr_data, - DHDR_LENGTH_OUT => dhdr_length, - DHDR_STORE_OUT => dhdr_store, - DHDR_BUF_FULL_IN => dhdr_buf_full, - -- data buffers -- from raw_buf_stage - BUF_ADDR_OUT => buf_addr, - BUF_DONE_OUT => buf_done, - BUF_TICK_IN => buf_tick, - BUF_START_IN => buf_start, - -- raw data - BUF_0_DATA_IN => buf_data(0), - BUF_1_DATA_IN => buf_data(1), - BUF_2_DATA_IN => buf_data(2), - BUF_3_DATA_IN => buf_data(3), - BUF_4_DATA_IN => buf_data(4), - BUF_5_DATA_IN => buf_data(5), - BUF_6_DATA_IN => buf_data(6), - BUF_7_DATA_IN => buf_data(7), - BUF_8_DATA_IN => buf_data(8), - BUF_9_DATA_IN => buf_data(9), - BUF_10_DATA_IN => buf_data(10), - BUF_11_DATA_IN => buf_data(11), - BUF_12_DATA_IN => buf_data(12), - BUF_13_DATA_IN => buf_data(13), - BUF_14_DATA_IN => buf_data(14), - BUF_15_DATA_IN => buf_data(15), - -- Pedestal data - PED_ADDR_OUT => open, -- BUGBUGBUG - PED_0_DATA_IN => ped_data(0), - PED_1_DATA_IN => ped_data(1), - PED_2_DATA_IN => ped_data(2), - PED_3_DATA_IN => ped_data(3), - PED_4_DATA_IN => ped_data(4), - PED_5_DATA_IN => ped_data(5), - PED_6_DATA_IN => ped_data(6), - PED_7_DATA_IN => ped_data(7), - PED_8_DATA_IN => ped_data(8), - PED_9_DATA_IN => ped_data(9), - PED_10_DATA_IN => ped_data(10), - PED_11_DATA_IN => ped_data(11), - PED_12_DATA_IN => ped_data(12), - PED_13_DATA_IN => ped_data(13), - PED_14_DATA_IN => ped_data(14), - PED_15_DATA_IN => ped_data(15), - -- Threshold data - THR_ADDR_OUT => thr_addr, - THR_0_DATA_IN => thr_data(0), - THR_1_DATA_IN => thr_data(1), - THR_2_DATA_IN => thr_data(2), - THR_3_DATA_IN => thr_data(3), - THR_4_DATA_IN => thr_data(4), - THR_5_DATA_IN => thr_data(5), - THR_6_DATA_IN => thr_data(6), - THR_7_DATA_IN => thr_data(7), - THR_8_DATA_IN => thr_data(8), - THR_9_DATA_IN => thr_data(9), - THR_10_DATA_IN => thr_data(10), - THR_11_DATA_IN => thr_data(11), - THR_12_DATA_IN => thr_data(12), - THR_13_DATA_IN => thr_data(13), - THR_14_DATA_IN => thr_data(14), - THR_15_DATA_IN => thr_data(15), - -- processed data - FIFO_START_OUT => fifo_start, - FIFO_0_DATA_OUT => fifo_data(0), - FIFO_1_DATA_OUT => fifo_data(1), - FIFO_2_DATA_OUT => fifo_data(2), - FIFO_3_DATA_OUT => fifo_data(3), - FIFO_4_DATA_OUT => fifo_data(4), - FIFO_5_DATA_OUT => fifo_data(5), - FIFO_6_DATA_OUT => fifo_data(6), - FIFO_7_DATA_OUT => fifo_data(7), - FIFO_8_DATA_OUT => fifo_data(8), - FIFO_9_DATA_OUT => fifo_data(9), - FIFO_10_DATA_OUT => fifo_data(10), - FIFO_11_DATA_OUT => fifo_data(11), - FIFO_12_DATA_OUT => fifo_data(12), - FIFO_13_DATA_OUT => fifo_data(13), - FIFO_14_DATA_OUT => fifo_data(14), - FIFO_15_DATA_OUT => fifo_data(15), - FIFO_WE_OUT => fifo_we, - FIFO_DONE_OUT => fifo_done, - -- Debug signals - DBG_BSM_OUT => open, - DBG_OUT => open - ); +port map( + CLK_IN => sysclk, + RESET_IN => global_sync_reset, + EDS_DATA_IN => eds_data, + EDS_AVAIL_IN => eds_avail, + EDS_DONE_OUT => eds_done, + -- DHDR information -- to next stage + DHDR_DATA_OUT => dhdr_data, + DHDR_LENGTH_OUT => dhdr_length, + DHDR_STORE_OUT => dhdr_store, + DHDR_BUF_FULL_IN => dhdr_buf_full, + FIFO_SPACE_REQ_OUT => fifo_space_req, + -- data buffers -- from raw_buf_stage + BUF_ADDR_OUT => buf_addr, + BUF_DONE_OUT => buf_done, + BUF_TICK_IN => buf_tick, + BUF_START_IN => buf_start, + -- raw data + BUF_0_DATA_IN => buf_data(0), + BUF_1_DATA_IN => buf_data(1), + BUF_2_DATA_IN => buf_data(2), + BUF_3_DATA_IN => buf_data(3), + BUF_4_DATA_IN => buf_data(4), + BUF_5_DATA_IN => buf_data(5), + BUF_6_DATA_IN => buf_data(6), + BUF_7_DATA_IN => buf_data(7), + BUF_8_DATA_IN => buf_data(8), + BUF_9_DATA_IN => buf_data(9), + BUF_10_DATA_IN => buf_data(10), + BUF_11_DATA_IN => buf_data(11), + BUF_12_DATA_IN => buf_data(12), + BUF_13_DATA_IN => buf_data(13), + BUF_14_DATA_IN => buf_data(14), + BUF_15_DATA_IN => buf_data(15), + -- Pedestal data + PED_ADDR_OUT => open, -- BUGBUGBUG + PED_0_DATA_IN => ped_data(0), + PED_1_DATA_IN => ped_data(1), + PED_2_DATA_IN => ped_data(2), + PED_3_DATA_IN => ped_data(3), + PED_4_DATA_IN => ped_data(4), + PED_5_DATA_IN => ped_data(5), + PED_6_DATA_IN => ped_data(6), + PED_7_DATA_IN => ped_data(7), + PED_8_DATA_IN => ped_data(8), + PED_9_DATA_IN => ped_data(9), + PED_10_DATA_IN => ped_data(10), + PED_11_DATA_IN => ped_data(11), + PED_12_DATA_IN => ped_data(12), + PED_13_DATA_IN => ped_data(13), + PED_14_DATA_IN => ped_data(14), + PED_15_DATA_IN => ped_data(15), + -- Threshold data + THR_ADDR_OUT => thr_addr, + THR_0_DATA_IN => thr_data(0), + THR_1_DATA_IN => thr_data(1), + THR_2_DATA_IN => thr_data(2), + THR_3_DATA_IN => thr_data(3), + THR_4_DATA_IN => thr_data(4), + THR_5_DATA_IN => thr_data(5), + THR_6_DATA_IN => thr_data(6), + THR_7_DATA_IN => thr_data(7), + THR_8_DATA_IN => thr_data(8), + THR_9_DATA_IN => thr_data(9), + THR_10_DATA_IN => thr_data(10), + THR_11_DATA_IN => thr_data(11), + THR_12_DATA_IN => thr_data(12), + THR_13_DATA_IN => thr_data(13), + THR_14_DATA_IN => thr_data(14), + THR_15_DATA_IN => thr_data(15), + -- processed data + FIFO_START_OUT => fifo_start, + FIFO_0_DATA_OUT => fifo_data(0), + FIFO_1_DATA_OUT => fifo_data(1), + FIFO_2_DATA_OUT => fifo_data(2), + FIFO_3_DATA_OUT => fifo_data(3), + FIFO_4_DATA_OUT => fifo_data(4), + FIFO_5_DATA_OUT => fifo_data(5), + FIFO_6_DATA_OUT => fifo_data(6), + FIFO_7_DATA_OUT => fifo_data(7), + FIFO_8_DATA_OUT => fifo_data(8), + FIFO_9_DATA_OUT => fifo_data(9), + FIFO_10_DATA_OUT => fifo_data(10), + FIFO_11_DATA_OUT => fifo_data(11), + FIFO_12_DATA_OUT => fifo_data(12), + FIFO_13_DATA_OUT => fifo_data(13), + FIFO_14_DATA_OUT => fifo_data(14), + FIFO_15_DATA_OUT => fifo_data(15), + FIFO_WE_OUT => fifo_we, + FIFO_DONE_OUT => fifo_done, + -- Debug signals + DBG_BSM_OUT => open, + DBG_OUT => open +); ------------------------------------------ -- Raw data processing and storage unit -- ------------------------------------------ THE_RAW_BUF_STAGE: raw_buf_stage_new -port map( CLK_IN => sysclk, - CLK_APV_IN => clk_apv, - RESET_IN => reset_by_trb, - -- trigger related signals - APV_RESET_IN => apv_reset, -- (100MHz clock) - APV_SYNC_IN => apv_sync, -- (40MHz APV clock) - APV_FRAME_REQD_IN => apv_frame_reqd, -- (100MHz clock) - -- ADC0 signals - ADC0_VALID_IN => adc0_valid, - ADC0_0_DATA_IN => adc_data(0), - ADC0_1_DATA_IN => adc_data(1), - ADC0_2_DATA_IN => adc_data(2), - ADC0_3_DATA_IN => adc_data(3), - ADC0_4_DATA_IN => adc_data(4), - ADC0_5_DATA_IN => adc_data(5), - ADC0_6_DATA_IN => adc_data(6), - ADC0_7_DATA_IN => adc_data(7), - -- ADC1 signals - ADC1_VALID_IN => adc1_valid, - ADC1_0_DATA_IN => adc_data(8), - ADC1_1_DATA_IN => adc_data(9), - ADC1_2_DATA_IN => adc_data(10), - ADC1_3_DATA_IN => adc_data(11), - ADC1_4_DATA_IN => adc_data(12), - ADC1_5_DATA_IN => adc_data(13), - ADC1_6_DATA_IN => adc_data(14), - ADC1_7_DATA_IN => adc_data(15), - -- Slow control registers - MAX_TRG_NUM_IN => maximum_trg, -- automatically determined - BIT_LOW_IN => ctrl_bitlow, -- from slow control - BIT_HIGH_IN => ctrl_bithigh, -- from slow control - FL_LOW_IN => ctrl_flatlow, -- from slow control - FL_HIGH_IN => ctrl_flathigh, -- from slow control - APV_ON_IN => adc_on, - -- 100MHZ synchronous interface - -- APV raw buffers - BUF_FULL_OUT => raw_buf_full, -- NEW NEW NEW - BUF_ADDR_IN => buf_addr, -- from ped_corr_ctrl - BUF_DONE_IN => buf_done, -- from ped_corr_ctrl - BUF_TICK_OUT => buf_tick, - BUF_START_OUT => buf_start, - BUF_READY_OUT => buf_ready, - BUF_0_DATA_OUT => buf_data(0), -- to ped_corr_ctrl - BUF_1_DATA_OUT => buf_data(1), -- to ped_corr_ctrl - BUF_2_DATA_OUT => buf_data(2), -- to ped_corr_ctrl - BUF_3_DATA_OUT => buf_data(3), -- to ped_corr_ctrl - BUF_4_DATA_OUT => buf_data(4), -- to ped_corr_ctrl - BUF_5_DATA_OUT => buf_data(5), -- to ped_corr_ctrl - BUF_6_DATA_OUT => buf_data(6), -- to ped_corr_ctrl - BUF_7_DATA_OUT => buf_data(7), -- to ped_corr_ctrl - BUF_8_DATA_OUT => buf_data(8), -- to ped_corr_ctrl - BUF_9_DATA_OUT => buf_data(9), -- to ped_corr_ctrl - BUF_10_DATA_OUT => buf_data(10), -- to ped_corr_ctrl - BUF_11_DATA_OUT => buf_data(11), -- to ped_corr_ctrl - BUF_12_DATA_OUT => buf_data(12), -- to ped_corr_ctrl - BUF_13_DATA_OUT => buf_data(13), -- to ped_corr_ctrl - BUF_14_DATA_OUT => buf_data(14), -- to ped_corr_ctrl - BUF_15_DATA_OUT => buf_data(15), -- to ped_corr_ctrl - -- Debug signals - DEBUG_OUT => raw_buf_debug --open - ); +port map( + CLK_IN => sysclk, + CLK_APV_IN => clk_apv, + RESET_IN => reset_by_trb, + -- trigger related signals + APV_RESET_IN => apv_reset, -- (100MHz clock) + APV_SYNC_IN => apv_sync, -- (40MHz APV clock) + APV_FRAME_REQD_IN => apv_frame_reqd, -- (100MHz clock) + -- ADC0 signals + ADC0_VALID_IN => adc0_valid, + ADC0_0_DATA_IN => adc_data(0), + ADC0_1_DATA_IN => adc_data(1), + ADC0_2_DATA_IN => adc_data(2), + ADC0_3_DATA_IN => adc_data(3), + ADC0_4_DATA_IN => adc_data(4), + ADC0_5_DATA_IN => adc_data(5), + ADC0_6_DATA_IN => adc_data(6), + ADC0_7_DATA_IN => adc_data(7), + -- ADC1 signals + ADC1_VALID_IN => adc1_valid, + ADC1_0_DATA_IN => adc_data(8), + ADC1_1_DATA_IN => adc_data(9), + ADC1_2_DATA_IN => adc_data(10), + ADC1_3_DATA_IN => adc_data(11), + ADC1_4_DATA_IN => adc_data(12), + ADC1_5_DATA_IN => adc_data(13), + ADC1_6_DATA_IN => adc_data(14), + ADC1_7_DATA_IN => adc_data(15), + -- Slow control registers + MAX_TRG_NUM_IN => maximum_trg, -- automatically determined + BIT_LOW_IN => ctrl_bitlow, -- from slow control + BIT_HIGH_IN => ctrl_bithigh, -- from slow control + FL_LOW_IN => ctrl_flatlow, -- from slow control + FL_HIGH_IN => ctrl_flathigh, -- from slow control + APV_ON_IN => adc_on, + -- 100MHZ synchronous interface + -- APV raw buffers + BUF_FULL_OUT => raw_buf_full, -- NEW NEW NEW + BUF_ADDR_IN => buf_addr, -- from ped_corr_ctrl + BUF_DONE_IN => buf_done, -- from ped_corr_ctrl + BUF_TICK_OUT => buf_tick, + BUF_START_OUT => buf_start, + BUF_READY_OUT => buf_ready, + BUF_0_DATA_OUT => buf_data(0), -- to ped_corr_ctrl + BUF_1_DATA_OUT => buf_data(1), -- to ped_corr_ctrl + BUF_2_DATA_OUT => buf_data(2), -- to ped_corr_ctrl + BUF_3_DATA_OUT => buf_data(3), -- to ped_corr_ctrl + BUF_4_DATA_OUT => buf_data(4), -- to ped_corr_ctrl + BUF_5_DATA_OUT => buf_data(5), -- to ped_corr_ctrl + BUF_6_DATA_OUT => buf_data(6), -- to ped_corr_ctrl + BUF_7_DATA_OUT => buf_data(7), -- to ped_corr_ctrl + BUF_8_DATA_OUT => buf_data(8), -- to ped_corr_ctrl + BUF_9_DATA_OUT => buf_data(9), -- to ped_corr_ctrl + BUF_10_DATA_OUT => buf_data(10), -- to ped_corr_ctrl + BUF_11_DATA_OUT => buf_data(11), -- to ped_corr_ctrl + BUF_12_DATA_OUT => buf_data(12), -- to ped_corr_ctrl + BUF_13_DATA_OUT => buf_data(13), -- to ped_corr_ctrl + BUF_14_DATA_OUT => buf_data(14), -- to ped_corr_ctrl + BUF_15_DATA_OUT => buf_data(15), -- to ped_corr_ctrl + -- Debug signals + DEBUG_OUT => raw_buf_debug --open +); ---------------------------------------- -- ADC1 data handler -- ---------------------------------------- THE_ADC1_HANDLER: adc_data_handler_new -port map( RESET_IN => reset_by_trb, - ADC_LCLK_IN => adc1_lclk, - ADC_ADCLK_IN => adc1_adclk, - ADC_CHNL_IN => adc1_out, - PLL_CTRL_IN => adc1_iodelay, - ADC_DATA7_OUT => adc_raw_data(15), - ADC_DATA6_OUT => adc_raw_data(14), - ADC_DATA5_OUT => adc_raw_data(13), - ADC_DATA4_OUT => adc_raw_data(12), - ADC_DATA3_OUT => adc_raw_data(11), - ADC_DATA2_OUT => adc_raw_data(10), - ADC_DATA1_OUT => adc_raw_data(9), - ADC_DATA0_OUT => adc_raw_data(8), - ADC_CE_OUT => adc1_ce, - ADC_VALID_OUT => adc1_valid, - DEBUG_OUT => open - ); +port map( + RESET_IN => reset_by_trb, + ADC_LCLK_IN => adc1_lclk, + ADC_ADCLK_IN => adc1_adclk, + ADC_CHNL_IN => adc1_out, + PLL_CTRL_IN => adc1_iodelay, + ADC_DATA7_OUT => adc_raw_data(15), + ADC_DATA6_OUT => adc_raw_data(14), + ADC_DATA5_OUT => adc_raw_data(13), + ADC_DATA4_OUT => adc_raw_data(12), + ADC_DATA3_OUT => adc_raw_data(11), + ADC_DATA2_OUT => adc_raw_data(10), + ADC_DATA1_OUT => adc_raw_data(9), + ADC_DATA0_OUT => adc_raw_data(8), + ADC_CE_OUT => adc1_ce, + ADC_VALID_OUT => adc1_valid, + DEBUG_OUT => open +); ---------------------------------------- -- ADC1 clock domain crossover -- ---------------------------------------- -THE_ADC1_CROSSOVER: adc_crossover -port map( CLK_APV_IN => clk_apv, - RESET_IN => global_sync_reset, - -- ADC clock domain signals - ADC_CLK_IN => adc1_lclk, - ADC_CE_IN => adc1_ce, - ADC_DATA_VALID_IN => adc1_valid, - ADC_DATA_7_IN => adc_raw_data(15), - ADC_DATA_6_IN => adc_raw_data(14), - ADC_DATA_5_IN => adc_raw_data(13), - ADC_DATA_4_IN => adc_raw_data(12), - ADC_DATA_3_IN => adc_raw_data(11), - ADC_DATA_2_IN => adc_raw_data(10), - ADC_DATA_1_IN => adc_raw_data(9), - ADC_DATA_0_IN => adc_raw_data(8), - LEVEL_WR_OUT => open, - -- APV clock domain signals - APV_DATA_7_OUT => adc_data(15), - APV_DATA_6_OUT => adc_data(14), - APV_DATA_5_OUT => adc_data(13), - APV_DATA_4_OUT => adc_data(12), - APV_DATA_3_OUT => adc_data(11), - APV_DATA_2_OUT => adc_data(10), - APV_DATA_1_OUT => adc_data(9), - APV_DATA_0_OUT => adc_data(8), - APV_DATA_VALID_OUT => open, - LEVEL_RD_OUT => open, - -- Debug signals - DEBUG_OUT => open - ); +THE_ADC1_CROSSOVER: adc_crossover +port map( + CLK_APV_IN => clk_apv, + RESET_IN => global_sync_reset, + -- ADC clock domain signals + ADC_CLK_IN => adc1_lclk, + ADC_CE_IN => adc1_ce, + ADC_DATA_VALID_IN => adc1_valid, + ADC_DATA_7_IN => adc_raw_data(15), + ADC_DATA_6_IN => adc_raw_data(14), + ADC_DATA_5_IN => adc_raw_data(13), + ADC_DATA_4_IN => adc_raw_data(12), + ADC_DATA_3_IN => adc_raw_data(11), + ADC_DATA_2_IN => adc_raw_data(10), + ADC_DATA_1_IN => adc_raw_data(9), + ADC_DATA_0_IN => adc_raw_data(8), + LEVEL_WR_OUT => open, + -- APV clock domain signals + APV_DATA_7_OUT => adc_data(15), + APV_DATA_6_OUT => adc_data(14), + APV_DATA_5_OUT => adc_data(13), + APV_DATA_4_OUT => adc_data(12), + APV_DATA_3_OUT => adc_data(11), + APV_DATA_2_OUT => adc_data(10), + APV_DATA_1_OUT => adc_data(9), + APV_DATA_0_OUT => adc_data(8), + APV_DATA_VALID_OUT => open, + LEVEL_RD_OUT => open, + -- Debug signals + DEBUG_OUT => open +); ---------------------------------------- -- ADC1 test data multiplexer -- ---------------------------------------- THE_ADC_1_SELECT: adc_channel_select -port map( RESET_IN => reset_by_trb, - ADC_CLK_IN => clk_apv, - ADC_SEL_IN => adc1_select, - ADC_7_IN => adc_data(15), - ADC_6_IN => adc_data(14), - ADC_5_IN => adc_data(13), - ADC_4_IN => adc_data(12), - ADC_3_IN => adc_data(11), - ADC_2_IN => adc_data(10), - ADC_1_IN => adc_data(9), - ADC_0_IN => adc_data(8), - ADC_CH_OUT => adc1_testdata, - DEBUG_OUT => open - ); +port map( + RESET_IN => reset_by_trb, + ADC_CLK_IN => clk_apv, + ADC_SEL_IN => adc1_select, + ADC_7_IN => adc_data(15), + ADC_6_IN => adc_data(14), + ADC_5_IN => adc_data(13), + ADC_4_IN => adc_data(12), + ADC_3_IN => adc_data(11), + ADC_2_IN => adc_data(10), + ADC_1_IN => adc_data(9), + ADC_0_IN => adc_data(8), + ADC_CH_OUT => adc1_testdata, + DEBUG_OUT => open +); ---------------------------------------- -- ADC0 data handler -- ---------------------------------------- THE_ADC0_HANDLER: adc_data_handler_new -port map( RESET_IN => reset_by_trb, - ADC_LCLK_IN => adc0_lclk, - ADC_ADCLK_IN => adc0_adclk, - ADC_CHNL_IN => adc0_out, - PLL_CTRL_IN => adc0_iodelay, - ADC_DATA7_OUT => adc_raw_data(7), - ADC_DATA6_OUT => adc_raw_data(6), - ADC_DATA5_OUT => adc_raw_data(5), - ADC_DATA4_OUT => adc_raw_data(4), - ADC_DATA3_OUT => adc_raw_data(3), - ADC_DATA2_OUT => adc_raw_data(2), - ADC_DATA1_OUT => adc_raw_data(1), - ADC_DATA0_OUT => adc_raw_data(0), - ADC_CE_OUT => adc0_ce, - ADC_VALID_OUT => adc0_valid, - DEBUG_OUT => open - ); +port map( + RESET_IN => reset_by_trb, + ADC_LCLK_IN => adc0_lclk, + ADC_ADCLK_IN => adc0_adclk, + ADC_CHNL_IN => adc0_out, + PLL_CTRL_IN => adc0_iodelay, + ADC_DATA7_OUT => adc_raw_data(7), + ADC_DATA6_OUT => adc_raw_data(6), + ADC_DATA5_OUT => adc_raw_data(5), + ADC_DATA4_OUT => adc_raw_data(4), + ADC_DATA3_OUT => adc_raw_data(3), + ADC_DATA2_OUT => adc_raw_data(2), + ADC_DATA1_OUT => adc_raw_data(1), + ADC_DATA0_OUT => adc_raw_data(0), + ADC_CE_OUT => adc0_ce, + ADC_VALID_OUT => adc0_valid, + DEBUG_OUT => open +); ---------------------------------------- -- ADC0 clock domain crossover -- ---------------------------------------- -THE_ADC0_CROSSOVER: adc_crossover -port map( CLK_APV_IN => clk_apv, - RESET_IN => global_sync_reset, - -- ADC clock domain signals - ADC_CLK_IN => adc0_lclk, - ADC_CE_IN => adc0_ce, - ADC_DATA_VALID_IN => adc0_valid, - ADC_DATA_7_IN => adc_raw_data(7), - ADC_DATA_6_IN => adc_raw_data(6), - ADC_DATA_5_IN => adc_raw_data(5), - ADC_DATA_4_IN => adc_raw_data(4), - ADC_DATA_3_IN => adc_raw_data(3), - ADC_DATA_2_IN => adc_raw_data(2), - ADC_DATA_1_IN => adc_raw_data(1), - ADC_DATA_0_IN => adc_raw_data(0), - LEVEL_WR_OUT => open, - -- APV clock domain signals - APV_DATA_7_OUT => adc_data(7), - APV_DATA_6_OUT => adc_data(6), - APV_DATA_5_OUT => adc_data(5), - APV_DATA_4_OUT => adc_data(4), - APV_DATA_3_OUT => adc_data(3), - APV_DATA_2_OUT => adc_data(2), - APV_DATA_1_OUT => adc_data(1), - APV_DATA_0_OUT => adc_data(0), - APV_DATA_VALID_OUT => open, - LEVEL_RD_OUT => open, - -- Debug signals - DEBUG_OUT => open - ); +THE_ADC0_CROSSOVER: adc_crossover +port map( + CLK_APV_IN => clk_apv, + RESET_IN => global_sync_reset, + -- ADC clock domain signals + ADC_CLK_IN => adc0_lclk, + ADC_CE_IN => adc0_ce, + ADC_DATA_VALID_IN => adc0_valid, + ADC_DATA_7_IN => adc_raw_data(7), + ADC_DATA_6_IN => adc_raw_data(6), + ADC_DATA_5_IN => adc_raw_data(5), + ADC_DATA_4_IN => adc_raw_data(4), + ADC_DATA_3_IN => adc_raw_data(3), + ADC_DATA_2_IN => adc_raw_data(2), + ADC_DATA_1_IN => adc_raw_data(1), + ADC_DATA_0_IN => adc_raw_data(0), + LEVEL_WR_OUT => open, + -- APV clock domain signals + APV_DATA_7_OUT => adc_data(7), + APV_DATA_6_OUT => adc_data(6), + APV_DATA_5_OUT => adc_data(5), + APV_DATA_4_OUT => adc_data(4), + APV_DATA_3_OUT => adc_data(3), + APV_DATA_2_OUT => adc_data(2), + APV_DATA_1_OUT => adc_data(1), + APV_DATA_0_OUT => adc_data(0), + APV_DATA_VALID_OUT => open, + LEVEL_RD_OUT => open, + -- Debug signals + DEBUG_OUT => open +); ---------------------------------------- -- ADC0 test data multiplexer -- ---------------------------------------- THE_ADC_0_SELECT: adc_channel_select -port map( RESET_IN => reset_by_trb, - ADC_CLK_IN => clk_apv, - ADC_SEL_IN => adc0_select, - ADC_7_IN => adc_data(7), - ADC_6_IN => adc_data(6), - ADC_5_IN => adc_data(5), - ADC_4_IN => adc_data(4), - ADC_3_IN => adc_data(3), - ADC_2_IN => adc_data(2), - ADC_1_IN => adc_data(1), - ADC_0_IN => adc_data(0), - ADC_CH_OUT => adc0_testdata, - DEBUG_OUT => open - ); +port map( + RESET_IN => reset_by_trb, + ADC_CLK_IN => clk_apv, + ADC_SEL_IN => adc0_select, + ADC_7_IN => adc_data(7), + ADC_6_IN => adc_data(6), + ADC_5_IN => adc_data(5), + ADC_4_IN => adc_data(4), + ADC_3_IN => adc_data(3), + ADC_2_IN => adc_data(2), + ADC_1_IN => adc_data(1), + ADC_0_IN => adc_data(0), + ADC_CH_OUT => adc0_testdata, + DEBUG_OUT => open +); ---------------------------------------- -- Trigger handler (APV specific) -- ---------------------------------------- THE_APV_TRGCTRL: apv_trgctrl -port map( CLK_IN => sysclk, - RESET_IN => global_sync_reset, - CLK_APV_IN => clk_apv, - -- Triggers - SYNC_TRG_IN => common_ctrl_reg(31), -- slow control pulse - TIME_TRG_IN => ext_in, -- external trigger inputs - TRB_TRG_IN => common_ctrl_reg(19 downto 16), -- slow control triggers - STILL_BUSY_IN => raw_buf_full, -- if no more frames are free in first stage buffer we must cease triggers. - TRG_FOUND_OUT => timing_trg_found, -- to TRB LVL1 endpoint - -- slow control settings - TRG_MAX_OUT => maximum_trg, - TRG_3_TODO_IN => ctrl_trg(31 downto 28), -- from slow control - TRG_3_DELAY_IN => ctrl_trg(27 downto 24), -- from slow control - TRG_2_TODO_IN => ctrl_trg(23 downto 20), -- from slow control - TRG_2_DELAY_IN => ctrl_trg(19 downto 16), -- from slow control - TRG_1_TODO_IN => ctrl_trg(15 downto 12), -- from slow control - TRG_1_DELAY_IN => ctrl_trg(11 downto 8), -- from slow control - TRG_0_TODO_IN => ctrl_trg(7 downto 4), -- from slow control - TRG_0_DELAY_IN => ctrl_trg(3 downto 0), -- from slow control - TRG_SETUP_IN => ctrl_pll(15 downto 8), -- from slow control - -- TRB LVL1 signals - TRB_TTAG_IN => lvl1_trg_number, -- from TRB LVL1 endpoint - TRB_TRND_IN => lvl1_trg_code, -- from TRB LVL1 endpoint - TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint - TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint - TRB_MISSING_OUT => lvl1_trg_missing, - TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint - TRB_RST_COUNTER_IN => common_ctrl_reg(30), -- depreciated! - TRB_COUNTER_OUT => local_lvl1_counter, - -- EDS signals - EDS_DATA_OUT => eds_data, -- to ped_corr_stage - EDS_AVAIL_OUT => eds_avail, -- to ped_corr_stage - EDS_DONE_IN => eds_done, -- from ped_corr_stage - EDS_FULL_OUT => eds_buf_full, - EDS_LEVEL_OUT => eds_buf_level, - FRM_REQD_OUT => apv_frame_reqd, -- to raw_buf_stage (100MHz clock) - -- APV signals - APV_TRG_OUT => apv_trg, -- to APV frontends (40MHz APV clock) - APV_SYNC_OUT => apv_sync, -- to raw_buf_stage (40MHz APV clock) - DEBUG_OUT => trgctrl_debug - ); +port map( + CLK_IN => sysclk, + RESET_IN => global_sync_reset, + CLK_APV_IN => clk_apv, + -- Triggers + SYNC_TRG_IN => common_ctrl_reg(31), -- slow control pulse + TIME_TRG_IN => ext_in, -- external trigger inputs + TRB_TRG_IN => common_ctrl_reg(19 downto 16), -- slow control triggers + STILL_BUSY_IN => raw_buf_full, -- if no more frames are free in first stage buffer we must cease triggers. + TRG_FOUND_OUT => timing_trg_found, -- to TRB LVL1 endpoint + SECTOR_IN => bp_sector_qq(2 downto 0), + -- slow control settings + TRG_MAX_OUT => maximum_trg, + TRG_3_TODO_IN => ctrl_trg(31 downto 28), -- from slow control + TRG_3_DELAY_IN => ctrl_trg(27 downto 24), -- from slow control + TRG_2_TODO_IN => ctrl_trg(23 downto 20), -- from slow control + TRG_2_DELAY_IN => ctrl_trg(19 downto 16), -- from slow control + TRG_1_TODO_IN => ctrl_trg(15 downto 12), -- from slow control + TRG_1_DELAY_IN => ctrl_trg(11 downto 8), -- from slow control + TRG_0_TODO_IN => ctrl_trg(7 downto 4), -- from slow control + TRG_0_DELAY_IN => ctrl_trg(3 downto 0), -- from slow control + TRG_SETUP_IN => ctrl_pll(15 downto 8), -- from slow control + -- TRB LVL1 signals + TRB_TTAG_IN => lvl1_trg_number, -- from TRB LVL1 endpoint + TRB_TRND_IN => lvl1_trg_code, -- from TRB LVL1 endpoint + TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint + TRB_TINFO_IN => lvl1_trg_information, -- from TRB LVL1 endpoint + TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint + TRB_MISSING_OUT => lvl1_trg_missing, + TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint + TRB_COUNTER_OUT => local_lvl1_counter, -- own trigger counter + TRB_COUNTER_IN => lvl1_int_trg_number, -- official TRB trigger counter + TRB_LD_COUNTER_IN => lvl1_int_trg_update, -- load TRB counter value + -- EDS signals + EDS_DATA_OUT => eds_data, -- to ped_corr_stage + EDS_AVAIL_OUT => eds_avail, -- to ped_corr_stage + EDS_DONE_IN => eds_done, -- from ped_corr_stage + EDS_FULL_OUT => eds_buf_full, + EDS_LEVEL_OUT => eds_buf_level, + FRM_REQD_OUT => apv_frame_reqd, -- to raw_buf_stage (100MHz clock) + -- APV signals + APV_TRG_OUT => apv_trg, -- to APV frontends (40MHz APV clock) + APV_SYNC_OUT => apv_sync, -- to raw_buf_stage (40MHz APV clock) + DEBUG_OUT => trgctrl_debug +); ---------------------------------------- @@ -1102,23 +1135,25 @@ adc1_rst <= adc1_reset; adc1_pd <= adc1_powerdown; THE_ADC1CLK_OUT: ODDRXC -port map( DA => '1', - DB => '0', - CLK => clk_adc, - RST => '0', - Q => adc1_clk - ); +port map( + DA => '1', + DB => '0', + CLK => clk_adc, + RST => '0', + Q => adc1_clk +); adc0_rst <= adc0_reset; adc0_pd <= adc0_powerdown; THE_ADC0CLK_OUT: ODDRXC -port map( DA => '1', - DB => '0', - CLK => clk_adc, - RST => '0', - Q => adc0_clk - ); +port map( + DA => '1', + DB => '0', + CLK => clk_adc, + RST => '0', + Q => adc0_clk +); ---------------------------------------- @@ -1143,65 +1178,73 @@ apv1_rst <= not apv_reset; -- CLK and TRG signal -- CLK is shifted to meet timing constraints of APV THE_APV0ACLK_OUT: ODDRXC -port map( DA => '0', - DB => '1', - CLK => clk_apv, - RST => '0', - Q => apv0a_clk - ); +port map( + DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv0a_clk +); THE_APV0BCLK_OUT: ODDRXC -port map( DA => '0', - DB => '1', - CLK => clk_apv, - RST => '0', - Q => apv0b_clk - ); +port map( + DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv0b_clk +); THE_APV1ACLK_OUT: ODDRXC -port map( DA => '0', - DB => '1', - CLK => clk_apv, - RST => '0', - Q => apv1a_clk - ); +port map( + DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv1a_clk +); THE_APV1BCLK_OUT: ODDRXC -port map( DA => '0', - DB => '1', - CLK => clk_apv, - RST => '0', - Q => apv1b_clk - ); +port map( + DA => '0', + DB => '1', + CLK => clk_apv, + RST => '0', + Q => apv1b_clk +); THE_APV0ATRG_OUT: ODDRXC -port map( DA => apv_trg, - DB => apv_trg, - CLK => clk_apv, - RST => '0', - Q => apv0a_trg - ); +port map( + DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv0a_trg +); THE_APV0BTRG_OUT: ODDRXC -port map( DA => apv_trg, - DB => apv_trg, - CLK => clk_apv, - RST => '0', - Q => apv0b_trg - ); +port map( + DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv0b_trg +); THE_APV1ATRG_OUT: ODDRXC -port map( DA => apv_trg, - DB => apv_trg, - CLK => clk_apv, - RST => '0', - Q => apv1a_trg - ); +port map( + DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv1a_trg +); THE_APV1BTRG_OUT: ODDRXC -port map( DA => apv_trg, - DB => apv_trg, - CLK => clk_apv, - RST => '0', - Q => apv1b_trg - ); +port map( + DA => apv_trg, + DB => apv_trg, + CLK => clk_apv, + RST => '0', + Q => apv1b_trg +); ---------------------------------------- @@ -1223,24 +1266,26 @@ end process THE_BP_SYNC_PROC; -- Reboot handler (pulse triggered) -- ---------------------------------------- THE_REBOOT_HANDLER: reboot_handler -port map( RESET_IN => reset_by_trb, - CLK_IN => sysclk, - START_IN => common_ctrl_reg(15), - REBOOT_OUT => uc_reboot, - DEBUG_OUT => open - ); +port map( + RESET_IN => reset_by_trb, + CLK_IN => sysclk, + START_IN => common_ctrl_reg(15), + REBOOT_OUT => uc_reboot, + DEBUG_OUT => open +); ---------------------------------------- -- FPGA debug header driver -- ---------------------------------------- THE_DBG_CLK_OUT: ODDRXC -port map( DA => '1', - DB => '0', - CLK => debug_clk, - RST => '0', - Q => dbg_exp(43) - ); +port map( + DA => '1', + DB => '0', + CLK => debug_clk, + RST => '0', + Q => dbg_exp(43) +); THE_DEBUG_REG_PROC: process( debug_clk ) begin diff --git a/src/adcmv3_components.vhd b/src/adcmv3_components.vhd index f09bf78..136d0b1 100755 --- a/src/adcmv3_components.vhd +++ b/src/adcmv3_components.vhd @@ -8,1580 +8,1694 @@ use IEEE.std_logic_UNSIGNED.ALL; package adcmv3_components is - component raw_buf_stage_new is - port( CLK_IN : in std_logic; -- 100MHz local clock - CLK_APV_IN : in std_logic; -- 40MHz APV clock - RESET_IN : in std_logic; -- general reset (100MHz) - -- trigger related signals - APV_RESET_IN : in std_logic; -- APV reset signal (100MHz) - APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz) - APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz) - -- ADC0 signals - ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid - ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0 - ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1 - ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2 - ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3 - ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4 - ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5 - ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6 - ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7 - -- ADC1 signals - ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid - ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0 - ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1 - ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2 - ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3 - ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4 - ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5 - ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6 - ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7 - -- Slow control registers - MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event - BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold - BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold - FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold - FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold - APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control - -- 100MHZ synchronous interface - -- APV raw buffers - BUF_FULL_OUT : out std_logic; - BUF_ADDR_IN : in std_logic_vector(6 downto 0); - BUF_DONE_IN : in std_logic; - BUF_TICK_OUT : out std_logic_vector(15 downto 0); - BUF_START_OUT : out std_logic_vector(15 downto 0); - BUF_READY_OUT : out std_logic_vector(15 downto 0); - BUF_0_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_1_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_2_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_3_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_4_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_5_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_6_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_7_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_8_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_9_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_10_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_11_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_12_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_13_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_14_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_15_DATA_OUT : out std_logic_vector(37 downto 0); - -- Debug signals - DEBUG_OUT : out std_logic_vector(63 downto 0) - ); - end component raw_buf_stage_new; - - component adc_data_handler_new is - port( RESET_IN : in std_logic; - ADC_LCLK_IN : in std_logic; -- LCLK from ADC - ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC - ADC_CHNL_IN : in std_logic_vector(7 downto 0); - PLL_CTRL_IN : in std_logic_vector(3 downto 0); - ADC_DATA7_OUT : out std_logic_vector(11 downto 0); - ADC_DATA6_OUT : out std_logic_vector(11 downto 0); - ADC_DATA5_OUT : out std_logic_vector(11 downto 0); - ADC_DATA4_OUT : out std_logic_vector(11 downto 0); - ADC_DATA3_OUT : out std_logic_vector(11 downto 0); - ADC_DATA2_OUT : out std_logic_vector(11 downto 0); - ADC_DATA1_OUT : out std_logic_vector(11 downto 0); - ADC_DATA0_OUT : out std_logic_vector(11 downto 0); - ADC_CE_OUT : out std_logic; - ADC_VALID_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component adc_data_handler_new; - - component adc_crossover is - port( CLK_APV_IN : in std_logic; -- APV 40MHz local clock - RESET_IN : in std_logic; -- general reset (100MHz) - -- ADC clock domain signals - ADC_CLK_IN : in std_logic; - ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse... - ADC_DATA_VALID_IN : in std_logic; - ADC_DATA_7_IN : in std_logic_vector(11 downto 0); - ADC_DATA_6_IN : in std_logic_vector(11 downto 0); - ADC_DATA_5_IN : in std_logic_vector(11 downto 0); - ADC_DATA_4_IN : in std_logic_vector(11 downto 0); - ADC_DATA_3_IN : in std_logic_vector(11 downto 0); - ADC_DATA_2_IN : in std_logic_vector(11 downto 0); - ADC_DATA_1_IN : in std_logic_vector(11 downto 0); - ADC_DATA_0_IN : in std_logic_vector(11 downto 0); - LEVEL_WR_OUT : out std_logic_vector(4 downto 0); - -- APV clock domain signals - APV_DATA_7_OUT : out std_logic_vector(11 downto 0); - APV_DATA_6_OUT : out std_logic_vector(11 downto 0); - APV_DATA_5_OUT : out std_logic_vector(11 downto 0); - APV_DATA_4_OUT : out std_logic_vector(11 downto 0); - APV_DATA_3_OUT : out std_logic_vector(11 downto 0); - APV_DATA_2_OUT : out std_logic_vector(11 downto 0); - APV_DATA_1_OUT : out std_logic_vector(11 downto 0); - APV_DATA_0_OUT : out std_logic_vector(11 downto 0); - APV_DATA_VALID_OUT : out std_logic; - LEVEL_RD_OUT : out std_logic_vector(4 downto 0); - -- Debug signals - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); - end component adc_crossover; - - component crossover is - port( DATA : in std_logic_vector(95 downto 0); - WRCLOCK : in std_logic; - RDCLOCK : in std_logic; - WREN : in std_logic; - RDEN : in std_logic; - RESET : in std_logic; -- asynchronous reset! - RPRESET : in std_logic; - Q : out std_logic_vector(95 downto 0); - WCNT : out std_logic_vector(4 downto 0); - RCNT : out std_logic_vector(4 downto 0); - EMPTY : out std_logic; - FULL : out std_logic - ); - end component crossover; - - component slv_adc_la is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(9 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from - ADC_CLK_IN : in std_logic; -- ADC reconstructed clock - ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component slv_adc_la; +component raw_buf_stage_new is +port( + CLK_IN : in std_logic; -- 100MHz local clock + CLK_APV_IN : in std_logic; -- 40MHz APV clock + RESET_IN : in std_logic; -- general reset (100MHz) + -- trigger related signals + APV_RESET_IN : in std_logic; -- APV reset signal (100MHz) + APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz) + APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz) + -- ADC0 signals + ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid + ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0 + ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1 + ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2 + ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3 + ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4 + ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5 + ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6 + ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7 + -- ADC1 signals + ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid + ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0 + ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1 + ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2 + ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3 + ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4 + ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5 + ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6 + ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7 + -- Slow control registers + MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event + BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold + BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold + FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold + FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold + APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control + -- 100MHZ synchronous interface + -- APV raw buffers + BUF_FULL_OUT : out std_logic; + BUF_ADDR_IN : in std_logic_vector(6 downto 0); + BUF_DONE_IN : in std_logic; + BUF_TICK_OUT : out std_logic_vector(15 downto 0); + BUF_START_OUT : out std_logic_vector(15 downto 0); + BUF_READY_OUT : out std_logic_vector(15 downto 0); + BUF_0_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_1_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_2_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_3_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_4_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_5_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_6_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_7_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_8_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_9_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_10_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_11_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_12_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_13_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_14_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_15_DATA_OUT : out std_logic_vector(37 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component raw_buf_stage_new; + +component adc_data_handler_new is +port( + RESET_IN : in std_logic; + ADC_LCLK_IN : in std_logic; -- LCLK from ADC + ADC_ADCLK_IN : in std_logic; -- ADCLK from ADC + ADC_CHNL_IN : in std_logic_vector(7 downto 0); + PLL_CTRL_IN : in std_logic_vector(3 downto 0); + ADC_DATA7_OUT : out std_logic_vector(11 downto 0); + ADC_DATA6_OUT : out std_logic_vector(11 downto 0); + ADC_DATA5_OUT : out std_logic_vector(11 downto 0); + ADC_DATA4_OUT : out std_logic_vector(11 downto 0); + ADC_DATA3_OUT : out std_logic_vector(11 downto 0); + ADC_DATA2_OUT : out std_logic_vector(11 downto 0); + ADC_DATA1_OUT : out std_logic_vector(11 downto 0); + ADC_DATA0_OUT : out std_logic_vector(11 downto 0); + ADC_CE_OUT : out std_logic; + ADC_VALID_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component adc_data_handler_new; + +component adc_crossover is +port( + CLK_APV_IN : in std_logic; -- APV 40MHz local clock + RESET_IN : in std_logic; -- general reset (100MHz) + -- ADC clock domain signals + ADC_CLK_IN : in std_logic; + ADC_CE_IN : in std_logic; -- in case we use 240MHz + write pulse... + ADC_DATA_VALID_IN : in std_logic; + ADC_DATA_7_IN : in std_logic_vector(11 downto 0); + ADC_DATA_6_IN : in std_logic_vector(11 downto 0); + ADC_DATA_5_IN : in std_logic_vector(11 downto 0); + ADC_DATA_4_IN : in std_logic_vector(11 downto 0); + ADC_DATA_3_IN : in std_logic_vector(11 downto 0); + ADC_DATA_2_IN : in std_logic_vector(11 downto 0); + ADC_DATA_1_IN : in std_logic_vector(11 downto 0); + ADC_DATA_0_IN : in std_logic_vector(11 downto 0); + LEVEL_WR_OUT : out std_logic_vector(4 downto 0); + -- APV clock domain signals + APV_DATA_7_OUT : out std_logic_vector(11 downto 0); + APV_DATA_6_OUT : out std_logic_vector(11 downto 0); + APV_DATA_5_OUT : out std_logic_vector(11 downto 0); + APV_DATA_4_OUT : out std_logic_vector(11 downto 0); + APV_DATA_3_OUT : out std_logic_vector(11 downto 0); + APV_DATA_2_OUT : out std_logic_vector(11 downto 0); + APV_DATA_1_OUT : out std_logic_vector(11 downto 0); + APV_DATA_0_OUT : out std_logic_vector(11 downto 0); + APV_DATA_VALID_OUT : out std_logic; + LEVEL_RD_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end component adc_crossover; + +component crossover is +port( + DATA : in std_logic_vector(95 downto 0); + WRCLOCK : in std_logic; + RDCLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; -- asynchronous reset! + RPRESET : in std_logic; + Q : out std_logic_vector(95 downto 0); + WCNT : out std_logic_vector(4 downto 0); + RCNT : out std_logic_vector(4 downto 0); + EMPTY : out std_logic; + FULL : out std_logic +); +end component crossover; + +component slv_adc_la is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(9 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from + ADC_CLK_IN : in std_logic; -- ADC reconstructed clock + ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component slv_adc_la; -- NOT USED YET - component logic_analyzer is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- control signals - ARM_IN : in std_logic; -- arm the machine - TRG_IN : in std_logic; -- trigger the data acquisition - MAX_SAMPLE_IN : in std_logic_vector(9 downto 0); - -- status signals - SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses - SM_CE_OUT : out std_logic; - SM_WE_OUT : out std_logic; -- write enable for sample RAM - CLEAR_OUT : out std_logic; -- sample memory is being cleared - RUN_OUT : out std_logic; -- ready for trigger - SAMPLE_OUT : out std_logic; -- data acquisition running - READY_OUT : out std_logic; -- data acquisition is finished - LAST_OUT : out std_logic; -- last data word of sampling - -- Status lines - BSM_OUT : out std_logic_vector(3 downto 0); - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component logic_analyzer; - - component onewire_spare_one is - port( ADDRESS : in std_logic_vector(2 downto 0); - Q : out std_logic_vector(3 downto 0) - ); - end component onewire_spare_one; - - component adc_onewire_map_mem is - port( ADDRESS : in std_logic_vector(6 downto 0); - Q : out std_logic_vector(3 downto 0) - ); - end component adc_onewire_map_mem; - - component adc_channel_select is - port( RESET_IN : in std_logic; - ADC_CLK_IN : in std_logic; - ADC_SEL_IN : in std_logic_vector(2 downto 0); - ADC_7_IN : in std_logic_vector(11 downto 0); - ADC_6_IN : in std_logic_vector(11 downto 0); - ADC_5_IN : in std_logic_vector(11 downto 0); - ADC_4_IN : in std_logic_vector(11 downto 0); - ADC_3_IN : in std_logic_vector(11 downto 0); - ADC_2_IN : in std_logic_vector(11 downto 0); - ADC_1_IN : in std_logic_vector(11 downto 0); - ADC_0_IN : in std_logic_vector(11 downto 0); - ADC_CH_OUT : out std_logic_vector(11 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component slv_adc_snoop is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(9 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from - ADC_CLK_IN : in std_logic; -- ADC reconstructed clock - ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; - - component adc_snoop_mem is - port( WRADDRESS : in std_logic_vector(9 downto 0); - RDADDRESS : in std_logic_vector(9 downto 0); - DATA : in std_logic_vector(15 downto 0); - WE : in std_logic; - RDCLOCK : in std_logic; - RDCLOCKEN : in std_logic; - RESET : in std_logic; - WRCLOCK : in std_logic; - WRCLOCKEN : in std_logic; - Q : out std_logic_vector(15 downto 0) - ); - end component; - - - component max_data is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - TODO_3_IN : in std_logic_vector(3 downto 0); - TODO_2_IN : in std_logic_vector(3 downto 0); - TODO_1_IN : in std_logic_vector(3 downto 0); - TODO_0_IN : in std_logic_vector(3 downto 0); - TODO_MAX_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component comp4bit is - port( DATAA : in std_logic_vector(3 downto 0); - DATAB : in std_logic_vector(3 downto 0); - AGTB : out std_logic - ); - end component; - - component slv_register_bank is - generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0001" ); - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(3 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - BACKPLANE_IN : in std_logic_vector(2 downto 0); - CTRL_0_OUT : out std_logic_vector(15 downto 0); - CTRL_1_OUT : out std_logic_vector(15 downto 0); - CTRL_2_OUT : out std_logic_vector(15 downto 0); - CTRL_3_OUT : out std_logic_vector(15 downto 0); - CTRL_4_OUT : out std_logic_vector(15 downto 0); - CTRL_5_OUT : out std_logic_vector(15 downto 0); - CTRL_6_OUT : out std_logic_vector(15 downto 0); - CTRL_7_OUT : out std_logic_vector(15 downto 0); - CTRL_8_OUT : out std_logic_vector(15 downto 0); - CTRL_9_OUT : out std_logic_vector(15 downto 0); - CTRL_10_OUT : out std_logic_vector(15 downto 0); - CTRL_11_OUT : out std_logic_vector(15 downto 0); - CTRL_12_OUT : out std_logic_vector(15 downto 0); - CTRL_13_OUT : out std_logic_vector(15 downto 0); - CTRL_14_OUT : out std_logic_vector(15 downto 0); - CTRL_15_OUT : out std_logic_vector(15 downto 0); - STAT_0_IN : in std_logic_vector(15 downto 0); - STAT_1_IN : in std_logic_vector(15 downto 0); - STAT_2_IN : in std_logic_vector(15 downto 0); - STAT_3_IN : in std_logic_vector(15 downto 0); - STAT_4_IN : in std_logic_vector(15 downto 0); - STAT_5_IN : in std_logic_vector(15 downto 0); - STAT_6_IN : in std_logic_vector(15 downto 0); - STAT_7_IN : in std_logic_vector(15 downto 0); - STAT_8_IN : in std_logic_vector(15 downto 0); - STAT_9_IN : in std_logic_vector(15 downto 0); - STAT_10_IN : in std_logic_vector(15 downto 0); - STAT_11_IN : in std_logic_vector(15 downto 0); - STAT_12_IN : in std_logic_vector(15 downto 0); - STAT_13_IN : in std_logic_vector(15 downto 0); - STAT_14_IN : in std_logic_vector(15 downto 0); - STAT_15_IN : in std_logic_vector(15 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; - - component pulse_stretch is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - START_IN : in std_logic; - PULSE_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component apv_adc_map_mem is - port( ADDRESS : in std_logic_vector(6 downto 0); - Q : out std_logic_vector(3 downto 0) - ); - end component; - - component adc_apv_map_mem is - port( ADDRESS : in std_logic_vector(6 downto 0); - Q : out std_logic_vector(3 downto 0) - ); - end component; - - - component ped_thr_true is - port( DATAINA : in std_logic_vector(17 downto 0); - DATAINB : in std_logic_vector(17 downto 0); - ADDRESSA : in std_logic_vector(6 downto 0); - ADDRESSB : in std_logic_vector(6 downto 0); - CLOCKA : in std_logic; - CLOCKB : in std_logic; - CLOCKENA : in std_logic; - CLOCKENB : in std_logic; - WRA : in std_logic; - WRB : in std_logic; - RESETA : in std_logic; - RESETB : in std_logic; - QA : out std_logic_vector(17 downto 0); - QB : out std_logic_vector(17 downto 0) - ); - end component; - - component slv_ped_thr_mem is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(10 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- backplane identifier - BACKPLANE_IN : in std_logic_vector(2 downto 0); - -- I/O to the backend - MEM_CLK_IN : in std_logic; - MEM_ADDR_IN : in std_logic_vector(6 downto 0); - MEM_0_D_OUT : out std_logic_vector(17 downto 0); - MEM_1_D_OUT : out std_logic_vector(17 downto 0); - MEM_2_D_OUT : out std_logic_vector(17 downto 0); - MEM_3_D_OUT : out std_logic_vector(17 downto 0); - MEM_4_D_OUT : out std_logic_vector(17 downto 0); - MEM_5_D_OUT : out std_logic_vector(17 downto 0); - MEM_6_D_OUT : out std_logic_vector(17 downto 0); - MEM_7_D_OUT : out std_logic_vector(17 downto 0); - MEM_8_D_OUT : out std_logic_vector(17 downto 0); - MEM_9_D_OUT : out std_logic_vector(17 downto 0); - MEM_10_D_OUT : out std_logic_vector(17 downto 0); - MEM_11_D_OUT : out std_logic_vector(17 downto 0); - MEM_12_D_OUT : out std_logic_vector(17 downto 0); - MEM_13_D_OUT : out std_logic_vector(17 downto 0); - MEM_14_D_OUT : out std_logic_vector(17 downto 0); - MEM_15_D_OUT : out std_logic_vector(17 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; - - component reset_handler is - port( CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0') - RESET_IN : in std_logic; -- for testing, if not needed, set to '0' - CLK_IN : in std_logic; - TRB_RESET_IN : in std_logic; - RESET_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component pll_40m is - port( CLK : in std_logic; - RESET : in std_logic; - DPAMODE : in std_logic; - DPHASE0 : in std_logic; - DPHASE1 : in std_logic; - DPHASE2 : in std_logic; - DPHASE3 : in std_logic; - CLKOP : out std_logic; - CLKOS : out std_logic; - LOCK : out std_logic - ); - end component; - - component dll_100m is - port( CLK : in std_logic; - RESETN : in std_logic; - ALUHOLD : in std_logic; - CLKOP : out std_logic; - CLKOS : out std_logic; - LOCK : out std_logic - ); - end component; - - component state_sync is - port( STATE_A_IN : in std_logic; - CLK_B_IN : in std_logic; - RESET_B_IN : in std_logic; - STATE_B_OUT : out std_logic - ); - end component; - - component pulse_sync is - port( CLK_A_IN : in std_logic; - RESET_A_IN : in std_logic; - PULSE_A_IN : in std_logic; - CLK_B_IN : in std_logic; - RESET_B_IN : in std_logic; - PULSE_B_OUT : out std_logic - ); - end component; - - component rich_trb is - port( CLK100M_IN : in std_logic; - SYSCLK_IN : in std_logic; - RESET_IN : in std_logic; - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_PRESENT_IN : in std_logic; - SD_TXDIS_OUT : out std_logic; - SD_LOS_IN : in std_logic; - ONEWIRE_INOUT : inout std_logic; - -- common regIO status / control registers --- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI - COMMON_STAT_REG_IN : in std_logic_vector(2*32-1 downto 0); -- common status register, bit definitions like in WIKI --- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI - COMMON_CTRL_REG_OUT : out std_logic_vector(2*32-1 downto 0); -- common control register, bit definitions like in WIKI - -- status register input to regIO / control register output from regIO - CONTROL_OUT : out std_logic_vector(63 downto 0); - STATUS_IN : in std_logic_vector(127 downto 0); - -- LVL1 signals - LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); - LVL1_TRG_RECEIVED_OUT : out std_logic; - LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); - LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); - LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); - LVL1_TRG_RELEASE_IN : in std_logic; - TIMING_TRG_FOUND_IN : in std_logic; - -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) - IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag - IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information - IPU_START_READOUT_OUT : out std_logic; -- gimme data! - IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR - IPU_DATAREADY_IN : in std_logic; -- data is valid - IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM - IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle - IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) - IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern - -- regIO bus --- REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); - REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); - REGIO_READ_ENABLE_OUT : out std_logic; - REGIO_WRITE_ENABLE_OUT : out std_logic; --- REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); - REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); --- REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); - REGIO_DATA_IN : in std_logic_vector(32-1 downto 0); - REGIO_DATAREADY_IN : in std_logic; - REGIO_NO_MORE_DATA_IN : in std_logic; - REGIO_WRITE_ACK_IN : in std_logic; - REGIO_UNKNOWN_ADDR_IN : in std_logic; - REGIO_TIMEOUT_OUT : out std_logic; - -- status LEDs - LED_LINK_STAT : out std_logic; - LED_LINK_TXD : out std_logic; - LED_LINK_RXD : out std_logic; - LINK_BSM_OUT : out std_logic_vector(3 downto 0); - RESET_OUT : out std_logic; - -- Debug - DEBUG : out std_logic_vector(63 downto 0) - ); - end component; - - component slave_bus is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- RegIO signals - REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus - REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint - REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint - REGIO_READ_ENABLE_IN : in std_logic; -- read pulse - REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse - REGIO_TIMEOUT_IN : in std_logic; -- access timed out - REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested - REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted - REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now - REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request - -- I2C connections - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; - -- 1Wire connections - ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse) - ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); -- 1Wire ID on APV FEs - BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane - -- SPI connections - SPI_CS_OUT : out std_logic; - SPI_SCK_OUT : out std_logic; - SPI_SDI_IN : in std_logic; - SPI_SDO_OUT : out std_logic; - -- ADC 0 SPI connections - SPI_ADC0_CS_OUT : out std_logic; - SPI_ADC0_SCK_OUT : out std_logic; - SPI_ADC0_SDO_OUT : out std_logic; - ADC0_PLL_LOCKED_IN : in std_logic; - ADC0_PD_OUT : out std_logic; - ADC0_RST_OUT : out std_logic; - ADC0_DEL_OUT : out std_logic_vector(3 downto 0); - ADC0_CLK_IN : in std_logic; - ADC0_DATA_IN : in std_logic_vector(11 downto 0); - ADC0_SEL_OUT : out std_logic_vector(2 downto 0); - APV0_RST_OUT : out std_logic; - -- ADC 0 SPI connections - SPI_ADC1_CS_OUT : out std_logic; - SPI_ADC1_SCK_OUT : out std_logic; - SPI_ADC1_SDO_OUT : out std_logic; - ADC1_PLL_LOCKED_IN : in std_logic; - ADC1_PD_OUT : out std_logic; - ADC1_RST_OUT : out std_logic; - ADC1_DEL_OUT : out std_logic_vector(3 downto 0); - ADC1_CLK_IN : in std_logic; - ADC1_DATA_IN : in std_logic_vector(11 downto 0); - ADC1_SEL_OUT : out std_logic_vector(2 downto 0); - APV1_RST_OUT : out std_logic; - -- User specific inputs / outputs - BACKPLANE_IN : in std_logic_vector(2 downto 0); - -- pedestal interface - PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers - PED_DATA_0_OUT : out std_logic_vector(17 downto 0); - PED_DATA_1_OUT : out std_logic_vector(17 downto 0); - PED_DATA_2_OUT : out std_logic_vector(17 downto 0); - PED_DATA_3_OUT : out std_logic_vector(17 downto 0); - PED_DATA_4_OUT : out std_logic_vector(17 downto 0); - PED_DATA_5_OUT : out std_logic_vector(17 downto 0); - PED_DATA_6_OUT : out std_logic_vector(17 downto 0); - PED_DATA_7_OUT : out std_logic_vector(17 downto 0); - PED_DATA_8_OUT : out std_logic_vector(17 downto 0); - PED_DATA_9_OUT : out std_logic_vector(17 downto 0); - PED_DATA_10_OUT : out std_logic_vector(17 downto 0); - PED_DATA_11_OUT : out std_logic_vector(17 downto 0); - PED_DATA_12_OUT : out std_logic_vector(17 downto 0); - PED_DATA_13_OUT : out std_logic_vector(17 downto 0); - PED_DATA_14_OUT : out std_logic_vector(17 downto 0); - PED_DATA_15_OUT : out std_logic_vector(17 downto 0); - -- threshold interface - THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers - THR_DATA_0_OUT : out std_logic_vector(17 downto 0); - THR_DATA_1_OUT : out std_logic_vector(17 downto 0); - THR_DATA_2_OUT : out std_logic_vector(17 downto 0); - THR_DATA_3_OUT : out std_logic_vector(17 downto 0); - THR_DATA_4_OUT : out std_logic_vector(17 downto 0); - THR_DATA_5_OUT : out std_logic_vector(17 downto 0); - THR_DATA_6_OUT : out std_logic_vector(17 downto 0); - THR_DATA_7_OUT : out std_logic_vector(17 downto 0); - THR_DATA_8_OUT : out std_logic_vector(17 downto 0); - THR_DATA_9_OUT : out std_logic_vector(17 downto 0); - THR_DATA_10_OUT : out std_logic_vector(17 downto 0); - THR_DATA_11_OUT : out std_logic_vector(17 downto 0); - THR_DATA_12_OUT : out std_logic_vector(17 downto 0); - THR_DATA_13_OUT : out std_logic_vector(17 downto 0); - THR_DATA_14_OUT : out std_logic_vector(17 downto 0); - THR_DATA_15_OUT : out std_logic_vector(17 downto 0); - -- APV control / status - CTRL_0_OUT : out std_logic_vector(15 downto 0); - CTRL_1_OUT : out std_logic_vector(15 downto 0); - CTRL_2_OUT : out std_logic_vector(15 downto 0); - CTRL_3_OUT : out std_logic_vector(15 downto 0); - CTRL_4_OUT : out std_logic_vector(15 downto 0); - CTRL_5_OUT : out std_logic_vector(15 downto 0); - CTRL_6_OUT : out std_logic_vector(15 downto 0); - CTRL_7_OUT : out std_logic_vector(15 downto 0); - CTRL_8_OUT : out std_logic_vector(15 downto 0); - CTRL_9_OUT : out std_logic_vector(15 downto 0); - CTRL_10_OUT : out std_logic_vector(15 downto 0); - CTRL_11_OUT : out std_logic_vector(15 downto 0); - CTRL_12_OUT : out std_logic_vector(15 downto 0); - CTRL_13_OUT : out std_logic_vector(15 downto 0); - CTRL_14_OUT : out std_logic_vector(15 downto 0); - CTRL_15_OUT : out std_logic_vector(15 downto 0); - STAT_0_IN : in std_logic_vector(15 downto 0); - STAT_1_IN : in std_logic_vector(15 downto 0); - STAT_2_IN : in std_logic_vector(15 downto 0); - STAT_3_IN : in std_logic_vector(15 downto 0); - STAT_4_IN : in std_logic_vector(15 downto 0); - STAT_5_IN : in std_logic_vector(15 downto 0); - STAT_6_IN : in std_logic_vector(15 downto 0); - STAT_7_IN : in std_logic_vector(15 downto 0); - STAT_8_IN : in std_logic_vector(15 downto 0); - STAT_9_IN : in std_logic_vector(15 downto 0); - STAT_10_IN : in std_logic_vector(15 downto 0); - STAT_11_IN : in std_logic_vector(15 downto 0); - STAT_12_IN : in std_logic_vector(15 downto 0); - STAT_13_IN : in std_logic_vector(15 downto 0); - STAT_14_IN : in std_logic_vector(15 downto 0); - STAT_15_IN : in std_logic_vector(15 downto 0); - -- some control signals - CTRL_LVL_OUT : out std_logic_vector(31 downto 0); - CTRL_TRG_OUT : out std_logic_vector(31 downto 0); - CTRL_PLL_OUT : out std_logic_vector(15 downto 0); - STATUS_PLL_IN : in std_logic_vector(15 downto 0); - -- temporary stuff - TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing! - TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing! - -- Debug - DEBUG_OUT : out std_logic_vector(63 downto 0); - STAT : out std_logic_vector(31 downto 0) - ); - end component; - - component oddrxc is - port( DA : in std_logic; - DB : in std_logic; - CLK : in std_logic; - RST : in std_logic; - Q : out std_logic - ); - end component; - - component apv_trgctrl is - port( CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; - CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock - -- Triggers - SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs - TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs - TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs - STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow - TRG_FOUND_OUT : out std_logic; -- trigger found - -- slow control settings - TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event - TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 - TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers - TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 - TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers - TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 - TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers - TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 - TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers - TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers - -- TRB LVL1 signals - TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag - TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag - TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type - TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received - TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger - TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel - TRB_RST_COUNTER_IN : in std_logic; -- reset timing trigger counter - TRB_COUNTER_OUT : out std_logic_vector(15 downto 0); - -- EDS signals - EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word - EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done - EDS_DONE_IN : in std_logic; -- release current EDS buffer - EDS_FULL_OUT : out std_logic; -- EDS buffer is full - EDS_LEVEL_OUT : out std_logic_vector(4 downto 0); - FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement) - -- APV signals - APV_TRG_OUT : out std_logic; - APV_SYNC_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) - ); - end component; - - component ped_corr_ctrl is - port( CLK_IN : in std_logic; -- 100MHz local clock - RESET_IN : in std_logic; -- synchronous reset - -- Slow control registers - -- EDS buffer -- back to previous source stage - EDS_DATA_IN : in std_logic_vector(39 downto 0); - EDS_AVAIL_IN : in std_logic; - EDS_DONE_OUT : out std_logic; - EVT_TYPE_IN : in std_logic_vector(2 downto 0); - -- DHDR information -- to next stage - DHDR_DATA_OUT : out std_logic_vector(31 downto 0); - DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0); - DHDR_STORE_OUT : out std_logic; - DHDR_BUF_FULL_IN : in std_logic; - -- data buffers -- from raw_buf_stage - BUF_ADDR_OUT : out std_logic_vector(6 downto 0); - BUF_DONE_OUT : out std_logic; - BUF_TICK_IN : in std_logic_vector(15 downto 0); - BUF_START_IN : in std_logic_vector(15 downto 0); - -- raw data - BUF_0_DATA_IN : in std_logic_vector(37 downto 0); - BUF_1_DATA_IN : in std_logic_vector(37 downto 0); - BUF_2_DATA_IN : in std_logic_vector(37 downto 0); - BUF_3_DATA_IN : in std_logic_vector(37 downto 0); - BUF_4_DATA_IN : in std_logic_vector(37 downto 0); - BUF_5_DATA_IN : in std_logic_vector(37 downto 0); - BUF_6_DATA_IN : in std_logic_vector(37 downto 0); - BUF_7_DATA_IN : in std_logic_vector(37 downto 0); - BUF_8_DATA_IN : in std_logic_vector(37 downto 0); - BUF_9_DATA_IN : in std_logic_vector(37 downto 0); - BUF_10_DATA_IN : in std_logic_vector(37 downto 0); - BUF_11_DATA_IN : in std_logic_vector(37 downto 0); - BUF_12_DATA_IN : in std_logic_vector(37 downto 0); - BUF_13_DATA_IN : in std_logic_vector(37 downto 0); - BUF_14_DATA_IN : in std_logic_vector(37 downto 0); - BUF_15_DATA_IN : in std_logic_vector(37 downto 0); - -- Pedestal data - PED_ADDR_OUT : out std_logic_vector(6 downto 0); - PED_0_DATA_IN : in std_logic_vector(17 downto 0); - PED_1_DATA_IN : in std_logic_vector(17 downto 0); - PED_2_DATA_IN : in std_logic_vector(17 downto 0); - PED_3_DATA_IN : in std_logic_vector(17 downto 0); - PED_4_DATA_IN : in std_logic_vector(17 downto 0); - PED_5_DATA_IN : in std_logic_vector(17 downto 0); - PED_6_DATA_IN : in std_logic_vector(17 downto 0); - PED_7_DATA_IN : in std_logic_vector(17 downto 0); - PED_8_DATA_IN : in std_logic_vector(17 downto 0); - PED_9_DATA_IN : in std_logic_vector(17 downto 0); - PED_10_DATA_IN : in std_logic_vector(17 downto 0); - PED_11_DATA_IN : in std_logic_vector(17 downto 0); - PED_12_DATA_IN : in std_logic_vector(17 downto 0); - PED_13_DATA_IN : in std_logic_vector(17 downto 0); - PED_14_DATA_IN : in std_logic_vector(17 downto 0); - PED_15_DATA_IN : in std_logic_vector(17 downto 0); - -- Threshold data - THR_ADDR_OUT : out std_logic_vector(6 downto 0); - THR_0_DATA_IN : in std_logic_vector(17 downto 0); - THR_1_DATA_IN : in std_logic_vector(17 downto 0); - THR_2_DATA_IN : in std_logic_vector(17 downto 0); - THR_3_DATA_IN : in std_logic_vector(17 downto 0); - THR_4_DATA_IN : in std_logic_vector(17 downto 0); - THR_5_DATA_IN : in std_logic_vector(17 downto 0); - THR_6_DATA_IN : in std_logic_vector(17 downto 0); - THR_7_DATA_IN : in std_logic_vector(17 downto 0); - THR_8_DATA_IN : in std_logic_vector(17 downto 0); - THR_9_DATA_IN : in std_logic_vector(17 downto 0); - THR_10_DATA_IN : in std_logic_vector(17 downto 0); - THR_11_DATA_IN : in std_logic_vector(17 downto 0); - THR_12_DATA_IN : in std_logic_vector(17 downto 0); - THR_13_DATA_IN : in std_logic_vector(17 downto 0); - THR_14_DATA_IN : in std_logic_vector(17 downto 0); - THR_15_DATA_IN : in std_logic_vector(17 downto 0); - -- processed data - FIFO_START_OUT : out std_logic; - FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_WE_OUT : out std_logic_vector(15 downto 0); - FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs - -- Debug signals - DBG_BSM_OUT : out std_logic_vector(7 downto 0); - DBG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component ipu_fifo_stage is - port( CLK_IN : in std_logic; -- 100MHz local clock - RESET_IN : in std_logic; -- synchronous reset - -- Slow control signals - SECTOR_IN : in std_logic_vector(2 downto 0); - MODULE_IN : in std_logic_vector(2 downto 0); - -- IPU channel connections - IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag - IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information - IPU_START_READOUT_IN : in std_logic; -- gimme data! - IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR - IPU_DATAREADY_OUT : out std_logic; -- data is valid - IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM - IPU_READ_IN : in std_logic; -- read strobe, low every second cycle - IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) - IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern - LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter - -- DHDR buffer input - DHDR_DATA_IN : in std_logic_vector(31 downto 0); - DHDR_LENGTH_IN : in std_logic_vector(15 downto 0); - DHDR_STORE_IN : in std_logic; - DHDR_BUF_FULL_OUT : out std_logic; - -- processed data input - FIFO_START_IN : in std_logic; - FIFO_0_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_1_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_2_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_3_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_4_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_5_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_6_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_7_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_8_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_9_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_10_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_11_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_12_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_13_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_14_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_15_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_WE_IN : in std_logic_vector(15 downto 0); - FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs - -- Debug signals - DBG_BSM_OUT : out std_logic_vector(7 downto 0); - DBG_OUT : out std_logic_vector(63 downto 0) - ); - end component; - - component ipu_dummy is - port( CLK_IN : in std_logic; -- 100MHz local clock - RESET_IN : in std_logic; -- synchronous reset - -- Slow control signals - MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value - MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value - CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control - -- IPU channel connections - IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag - IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information - IPU_START_READOUT_IN : in std_logic; -- gimme data! - IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR - IPU_DATAREADY_OUT : out std_logic; -- data is valid - IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM - IPU_READ_IN : in std_logic; -- read strobe, low every second cycle - IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) - IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern - -- DHDR buffer - LVL1_FIFO_RD_OUT : out std_logic; - LVL1_FIFO_EMPTY_IN : in std_logic; - LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0); - LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0); - -- Debug signals - DBG_BSM_OUT : out std_logic_vector(7 downto 0); - DBG_OUT : out std_logic_vector(63 downto 0) - ); - end component; - - component reboot_handler is - port( RESET_IN : in std_logic; - CLK_IN : in std_logic; - START_IN : in std_logic; - REBOOT_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component real_trg_handler is - port( CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; - TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs - TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs - APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse) - TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 - TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 - TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 - TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 - TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers - TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint - TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag - TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number - TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type - TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB - TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger - RST_LVL1_COUNTER_IN : in std_logic; -- reset LVL1 counter - LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); -- LVL1 counter - BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator - APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine - APV_TRGSTART_OUT : out std_logic; -- start one APV trigger state machine - EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data - EDS_WE_OUT : out std_logic; -- EDS write enable (general interface) - EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level - EDS_READY_OUT : out std_logic; -- APV trigger sequence done, TERMinate the TRB LVL1 trigger - DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself - BSM_OUT : out std_logic_vector(7 downto 0); - DEBUG_OUT : out std_logic_vector(63 downto 0) - ); - end component; - - component apv_trg_handler is - port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock - RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) - CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; -- synced reset signal (100MHz) - APV_TRGSTART_IN : in std_logic; -- start signal for one sequence - APV_TRGSEL_IN : in std_logic; -- select signal for one sequence - APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers - APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers - APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished - APV_TRG_OUT : out std_logic; - APV_TRGSENT_OUT : out std_logic; - BSM_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component apv_sync_handler is - port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock - RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) - CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; -- synced reset signal (100MHz) - APV_TRGSTART_IN : in std_logic; -- start signal for one sequence - APV_TRGSEL_IN : in std_logic; -- select signal for one sequence - APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished - APV_TRG_OUT : out std_logic; - APV_SYNC_OUT : out std_logic; -- signal for statemachines - BSM_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component eds_buf is - port( CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; - -- EDS input, all synced to CLK_IN - EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input - EDS_WE_IN : in std_logic; -- EDS write enable - EDS_DONE_IN : in std_logic; -- release EDS - EDS_DATA_OUT : out std_logic_vector(39 downto 0); - EDS_AVAILABLE_OUT : out std_logic; - -- trigger busy information - BUF_FULL_OUT : out std_logic; - BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); - -- Debug signals - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component adc_pll is - port( CLK : in std_logic; - RESET : in std_logic; - CLKOP : out std_logic; - LOCK : out std_logic - ); - end component; - - component adc_ch_in is - port( DEL : in std_logic_vector(3 downto 0); - ECLK : in std_logic; - SCLK : in std_logic; - RST : in std_logic; - DATA : in std_logic_vector(0 downto 0); - Q : out std_logic_vector(1 downto 0) - ); - end component; - - component adc_twochannels is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - CLOCK_IN : in std_logic_vector(1 downto 0); -- DDR bit clock - DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one - DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two - DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one - DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two - STORE_OUT : out std_logic; - SWAP_OUT : out std_logic; - CLOCK_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component apv_locker is - port( CLK_APV_IN : in std_logic; - RESET_IN : in std_logic; - ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to ADC_CLK_IN - ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid - SYNC_IN : in std_logic; -- sync trigger input - APV_ON_IN : in std_logic; -- this APV channel is switched on - BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0' - BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1' - FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline - FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline - STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off) - STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet - STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid - STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully - STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong - STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully - STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected - STATUS_TICKMARK_OUT : out std_logic; - FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header - FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header - FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?) - FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow - FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow - FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames - APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID - APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high - APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low - APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data - APV_ANALOG_OUT : out std_logic; -- APV analog data is valid - APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer - APV_LAST_OUT : out std_logic; -- last APV channel of dataframe - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component apv_raw_buffer is - port( CLK_APV_IN : in std_logic; -- write clock from APV handling stage - RESET_IN : in std_logic; - FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV - MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event - ADC_ANALOG_IN : in std_logic; -- write enable for ADC data - ADC_START_IN : in std_logic; -- data frame detected, block the buffer page - ADC_LAST_IN : in std_logic; -- last channel signal - ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID - ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR - ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV - ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame - BUF_CLK_IN : in std_logic; -- read clock - BUF_RESET_IN : in std_logic; -- 100MHz reset - BUF_START_OUT : out std_logic; -- one block starts writing - BUF_READY_OUT : out std_logic; -- one block has been written - BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer - BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer) - BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer - BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output - BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output - BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation - BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation - BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off - BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer - BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler - BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set! - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component slv_register is - generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" ); - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - BUSY_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - REG_DATA_IN : in std_logic_vector(31 downto 0); - REG_DATA_OUT : out std_logic_vector(31 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; - - component slv_half_register is - generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" ); - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - STATUS_REG_IN : in std_logic_vector(15 downto 0); - CTRL_REG_OUT : out std_logic_vector(15 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; - - component i2c_master is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I2C connections - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; - - component slv_onewire_memory is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(5 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- backplane identifier - BACKPLANE_IN : in std_logic_vector(2 downto 0); - -- 1Wire lines - ONEWIRE_START_IN : in std_logic; - ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); - BP_ONEWIRE_INOUT : inout std_logic; - -- Status lines - STAT : out std_logic_vector(63 downto 0) -- DEBUG - ); - end component; - - component spi_real_slim is - port( SYSCLK : in std_logic; -- 100MHz sysclock - RESET : in std_logic; -- synchronous reset - -- Command interface - START_IN : in std_logic; -- one start pulse - BUSY_OUT : out std_logic; -- SPI transactions are ongoing - CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte - -- SPI interface - SPI_SCK_OUT : out std_logic; - SPI_CS_OUT : out std_logic; - SPI_SDO_OUT : out std_logic; - -- DEBUG - CLK_EN_OUT : out std_logic; - BSM_OUT : out std_logic_vector(7 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); - end component; - - component spi_adc_master is - generic( RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" ); - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- SPI connections - SPI_CS_OUT : out std_logic; - SPI_SDO_OUT : out std_logic; - SPI_SCK_OUT : out std_logic; - -- ADC connections - ADC_LOCKED_IN : in std_logic; - ADC_PD_OUT : out std_logic; - ADC_RST_OUT : out std_logic; - ADC_DEL_OUT : out std_logic_vector(3 downto 0); - -- APV connections - APV_RST_OUT : out std_logic; - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; - - component i2c_slim is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- I2C command / setup - I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions - ACTION_IN : in std_logic; -- '0' -> write, '1' -> read - I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined) - I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored) - I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte) - I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command - I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command - STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits - I2C_BUSY_OUT : out std_logic; - -- I2C connections - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; - -- Debug - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); - end component; - - component i2c_gstart is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - START_IN : in std_logic; - DOSTART_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector(7 downto 0); - SDONE_OUT : out std_logic; - SOK_OUT : out std_logic; - SDA_IN : in std_logic; - SCL_IN : in std_logic; - R_SCL_OUT : out std_logic; - S_SCL_OUT : out std_logic; - R_SDA_OUT : out std_logic; - S_SDA_OUT : out std_logic; - BSM_OUT : out std_logic_vector(3 downto 0) - ); - end component; - - component i2c_sendb is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - DOBYTE_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector(7 downto 0); - I2C_BYTE_IN : in std_logic_vector(8 downto 0); - I2C_BACK_OUT : out std_logic_vector(8 downto 0); - SDA_IN : in std_logic; - R_SDA_OUT : out std_logic; - S_SDA_OUT : out std_logic; --- SCL_IN : in std_logic; - R_SCL_OUT : out std_logic; - S_SCL_OUT : out std_logic; - BDONE_OUT : out std_logic; - BOK_OUT : out std_logic; - BSM_OUT : out std_logic_vector(3 downto 0) - ); - end component; - - component onewire_master is - generic( CLK_PERIOD : integer := 10 ); -- clock perion in nanoseconds - port( CLK : in std_logic; - RESET : in std_logic; - READOUT_ENABLE_IN : in std_logic; - -- connection to 1-wire interface (16 APV FEs) - ONEWIRE : inout std_logic_vector(15 downto 0); - BP_ONEWIRE : inout std_logic; - -- connection to external DPRAM for slow control readout - BP_DATA_OUT : out std_logic_vector(15 downto 0); - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(6 downto 0); - WRITE_OUT : out std_logic; - BUSY_OUT : out std_logic; - -- debug - BSM_OUT : out std_logic_vector(7 downto 0); - STAT : out std_logic_vector(15 downto 0) - ); - end component; - - component slv_onewire_dpram - port( WRADDRESS : in std_logic_vector(6 downto 0); - RDADDRESS : in std_logic_vector(5 downto 0); - DATA : in std_logic_vector(15 downto 0); - WE : in std_logic; - RDCLOCK : in std_logic; - RDCLOCKEN : in std_logic; - RESET : in std_logic; - WRCLOCK : in std_logic; - WRCLOCKEN : in std_logic; - Q : out std_logic_vector(31 downto 0) - ); - end component; - - component dhdr_buf is - port( CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; - -- DHDR information block - DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input - DHDR_WE_IN : in std_logic; -- EDS write enable - DHDR_DONE_IN : in std_logic; -- release EDS - DHDR_DATA_OUT : out std_logic_vector(47 downto 0); - DHDR_AVAILABLE_OUT : out std_logic; - -- trigger busy information - BUF_FULL_OUT : out std_logic; - BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); - -- Debug signals - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component fifo_2kx27 is - port( DATA : in std_logic_vector(26 downto 0); - CLOCK : in std_logic; - WREN : in std_logic; - RDEN : in std_logic; - RESET : in std_logic; - Q : out std_logic_vector(26 downto 0); - WCNT : out std_logic_vector(11 downto 0); - EMPTY : out std_logic; - FULL : out std_logic - ); - end component fifo_2kx27; - - component fifo_16x11 is - port( DATA : in std_logic_vector(10 downto 0); - CLOCK : in std_logic; - WREN : in std_logic; - RDEN : in std_logic; - RESET : in std_logic; - Q : out std_logic_vector(10 downto 0); - WCNT : out std_logic_vector(4 downto 0); - EMPTY : out std_logic; - FULL : out std_logic - ); - end component fifo_16x11; - - component dhdr_buffer_dpram is - port( WRADDRESS : in std_logic_vector(3 downto 0); - DATA : in std_logic_vector(47 downto 0); - WRCLOCK : in std_logic; - WE : in std_logic; - WRCLOCKEN : in std_logic; - RDADDRESS : in std_logic_vector(3 downto 0); - RDCLOCK : in std_logic; - RDCLOCKEN : in std_logic; - RESET : in std_logic; - Q : out std_logic_vector(47 downto 0) - ); - end component; - - component decoder_8bit is - port( ADDRESS : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(3 downto 0) - ); - end component decoder_8bit; - - component adder_5bit is - port( DATAA : in std_logic_vector(4 downto 0); - DATAB : in std_logic_vector(4 downto 0); - CLOCK : in std_logic; - RESET : in std_logic; - CLOCKEN : in std_logic; - RESULT : out std_logic_vector(4 downto 0) - ); - end component adder_5bit; - - component adder_16bit is - port( DATAA : in std_logic_vector(15 downto 0); - DATAB : in std_logic_vector(15 downto 0); - CLOCK : in std_logic; - RESET : in std_logic; - CLOCKEN : in std_logic; - RESULT : out std_logic_vector(15 downto 0) - ); - end component adder_16bit; - - component suber_12bit is - port( DATAA : in std_logic_vector(11 downto 0); - DATAB : in std_logic_vector(11 downto 0); - CLOCK : in std_logic; - RESET : in std_logic; - CLOCKEN : in std_logic; - RESULT : out std_logic_vector(11 downto 0) - ); - end component suber_12bit; - - - component buf_toc is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - BUF_TICK_IN : in std_logic; -- tickmark from raw buffer - BUF_START_IN : in std_logic; -- start of frame from raw buffer - WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode - FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS - BUF_LVL_IN : in std_logic_vector(7 downto 0); - GOODDATA_OUT : out std_logic; - BADDATA_OUT : out std_logic; - NODATA_OUT : out std_logic; - READY_OUT : out std_logic; - BSM_OUT : out std_logic_vector(7 downto 0); - DBG_OUT : out std_logic_vector(15 downto 0) - ); - end component buf_toc; - - component ref_row_sel is - port( CLK_IN : in std_logic; - READY_IN : in std_logic_vector(15 downto 0); - GOODDATA_IN : in std_logic_vector(15 downto 0); - FRAME_0_IN : in std_logic_vector(11 downto 0); - FRAME_1_IN : in std_logic_vector(11 downto 0); - FRAME_2_IN : in std_logic_vector(11 downto 0); - FRAME_3_IN : in std_logic_vector(11 downto 0); - FRAME_4_IN : in std_logic_vector(11 downto 0); - FRAME_5_IN : in std_logic_vector(11 downto 0); - FRAME_6_IN : in std_logic_vector(11 downto 0); - FRAME_7_IN : in std_logic_vector(11 downto 0); - FRAME_8_IN : in std_logic_vector(11 downto 0); - FRAME_9_IN : in std_logic_vector(11 downto 0); - FRAME_10_IN : in std_logic_vector(11 downto 0); - FRAME_11_IN : in std_logic_vector(11 downto 0); - FRAME_12_IN : in std_logic_vector(11 downto 0); - FRAME_13_IN : in std_logic_vector(11 downto 0); - FRAME_14_IN : in std_logic_vector(11 downto 0); - FRAME_15_IN : in std_logic_vector(11 downto 0); - VALID_BUFS_OUT : out std_logic; - READY_OUT : out std_logic; - ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong - APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit - APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0); - REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row - DBG_OUT : out std_logic_vector(15 downto 0) - ); - end component ref_row_sel; - - component frmctr_check is - port( CLK_IN : in std_logic; - GOODDATA_IN : in std_logic_vector(15 downto 0); - FRAMECOUNTER_IN : in std_logic_vector(3 downto 0); - FRM_NR_0_IN : in std_logic_vector(3 downto 0); - FRM_NR_1_IN : in std_logic_vector(3 downto 0); - FRM_NR_2_IN : in std_logic_vector(3 downto 0); - FRM_NR_3_IN : in std_logic_vector(3 downto 0); - FRM_NR_4_IN : in std_logic_vector(3 downto 0); - FRM_NR_5_IN : in std_logic_vector(3 downto 0); - FRM_NR_6_IN : in std_logic_vector(3 downto 0); - FRM_NR_7_IN : in std_logic_vector(3 downto 0); - FRM_NR_8_IN : in std_logic_vector(3 downto 0); - FRM_NR_9_IN : in std_logic_vector(3 downto 0); - FRM_NR_10_IN : in std_logic_vector(3 downto 0); - FRM_NR_11_IN : in std_logic_vector(3 downto 0); - FRM_NR_12_IN : in std_logic_vector(3 downto 0); - FRM_NR_13_IN : in std_logic_vector(3 downto 0); - FRM_NR_14_IN : in std_logic_vector(3 downto 0); - FRM_NR_15_IN : in std_logic_vector(3 downto 0); - FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong - DBG_OUT : out std_logic_vector(15 downto 0) - ); - end component frmctr_check; - - component apv_pc_nc_alu is - port( CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; - START_IN : in std_logic; - MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested - CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number - LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG - EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG - BUF_GOOD_IN : in std_logic; - BUF_BAD_IN : in std_logic; - BUF_IGNORE_IN : in std_logic; - ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers - DO_HEADER_IN : in std_logic; - DO_ERROR_IN : in std_logic; - EVT_TYPE_IN : in std_logic_vector(2 downto 0); - RAW_ADDR_IN : in std_logic_vector(6 downto 0); - RAW_DATA_IN : in std_logic_vector(37 downto 0); - PED_DATA_IN : in std_logic_vector(17 downto 0); - THR_DATA_IN : in std_logic_vector(17 downto 0); - FRAME_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0] - WE_OUT : out std_logic; - COUNT_OUT : out std_logic_vector(9 downto 0); - ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout - DBG_OUT : out std_logic_vector(15 downto 0) - ); - end component apv_pc_nc_alu; - - component comp14bit is - port( DATAA : in std_logic_vector(13 downto 0); - DATAB : in std_logic_vector(13 downto 0); - CLOCK : in std_logic; - CLOCKEN : in std_logic; - ACLR : in std_logic; - AGEB : out std_logic - ); - end component; - - component input_bram is - port( WRADDRESS : in std_logic_vector(10 downto 0); - RDADDRESS : in std_logic_vector(10 downto 0); - DATA : in std_logic_vector(17 downto 0); - WE : in std_logic; - RDCLOCK : in std_logic; - RDCLOCKEN : in std_logic; - RESET : in std_logic; - WRCLOCK : in std_logic; - WRCLOCKEN : in std_logic; - Q : out std_logic_vector(17 downto 0) - ); - end component; - - component frame_status_mem is - port( WRADDRESS : in std_logic_vector(3 downto 0); - DATA : in std_logic_vector(11 downto 0); - WRCLOCK : in std_logic; - WE : in std_logic; - WRCLOCKEN : in std_logic; - RDADDRESS : in std_logic_vector(3 downto 0); - RDCLOCK : in std_logic; - RDCLOCKEN : in std_logic; - RESET : in std_logic; - Q : out std_logic_vector(11 downto 0) - ); - end component; - - component adder_6bit is - port( DATAA : in std_logic_vector(5 downto 0); - DATAB : in std_logic_vector(5 downto 0); - CLOCK : in std_logic; - RESET : in std_logic; - CLOCKEN : in std_logic; - RESULT : out std_logic_vector(5 downto 0) - ); - end component; - - component apv_lock_sm is - port( CLK_APV_IN : in std_logic; - RESET_IN : in std_logic; - SYNC_IN : in std_logic; -- start APV synchronisation - ADC_VALID_IN : in std_logic; -- ADC delivers valid data - TIMED_IN : in std_logic; -- synchronisation timeout - MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter - LOCKED_IN : in std_logic; -- enough good tickmarks - TICK_IN : in std_logic; -- tickmark from digital parser - HEADER_IN : in std_logic; -- header from digital parser - FLATLINE_IN : in std_logic; -- flatline from digital parser - RST_PC_OUT : out std_logic; -- reset period counter - RST_TC_OUT : out std_logic; -- reset timeout counter - INC_TC_OUT : out std_logic; - RST_LC_OUT : out std_logic; -- reset lock counter - INC_LC_OUT : out std_logic; - UNKNOWN_OUT : out std_logic; - BADADC_OUT : out std_logic; -- ADC data invalid - LOCKED_OUT : out std_logic; - LOST_OUT : out std_logic; - NOSYNC_OUT : out std_logic; - NOAPV_OUT : out std_logic; - BSM_OUT : out std_logic_vector(7 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); - end component; - - component apv_digital is - port( CLK_APV_IN : in std_logic; - RESET_IN : in std_logic; - ADC_RAW_IN : in std_logic_vector(11 downto 0); - BIT_LOW_IN : in std_logic_vector(11 downto 0); - BIT_HIGH_IN : in std_logic_vector(11 downto 0); - FL_LOW_IN : in std_logic_vector(11 downto 0); - FL_HIGH_IN : in std_logic_vector(11 downto 0); - BIT_DATA_OUT : out std_logic_vector(11 downto 0); - BIT_VALID_OUT : out std_logic_vector(11 downto 0); - BIT_HIGH_OUT : out std_logic; - BIT_LOW_OUT : out std_logic; - TICKMARK_OUT : out std_logic; - HEADER_OUT : out std_logic; - FLAT_LINE_OUT : out std_logic - ); - end component; - - component eds_buffer_dpram is - port( WRADDRESS : in std_logic_vector(3 downto 0); - DATA : in std_logic_vector(39 downto 0); - WRCLOCK : in std_logic; - WE : in std_logic; - WRCLOCKEN : in std_logic; - RDADDRESS : in std_logic_vector(3 downto 0); - RDCLOCK : in std_logic; - RDCLOCKEN : in std_logic; - RESET : in std_logic; - Q : out std_logic_vector(39 downto 0) - ); - end component; +component logic_analyzer is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- control signals + ARM_IN : in std_logic; -- arm the machine + TRG_IN : in std_logic; -- trigger the data acquisition + MAX_SAMPLE_IN : in std_logic_vector(9 downto 0); + -- status signals + SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses + SM_CE_OUT : out std_logic; + SM_WE_OUT : out std_logic; -- write enable for sample RAM + CLEAR_OUT : out std_logic; -- sample memory is being cleared + RUN_OUT : out std_logic; -- ready for trigger + SAMPLE_OUT : out std_logic; -- data acquisition running + READY_OUT : out std_logic; -- data acquisition is finished + LAST_OUT : out std_logic; -- last data word of sampling + -- Status lines + BSM_OUT : out std_logic_vector(3 downto 0); + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component logic_analyzer; + +component onewire_spare_one is +port( + ADDRESS : in std_logic_vector(2 downto 0); + Q : out std_logic_vector(3 downto 0) +); +end component onewire_spare_one; + +component adc_onewire_map_mem is +port( + ADDRESS : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) +); +end component adc_onewire_map_mem; + +component adc_channel_select is +port( + RESET_IN : in std_logic; + ADC_CLK_IN : in std_logic; + ADC_SEL_IN : in std_logic_vector(2 downto 0); + ADC_7_IN : in std_logic_vector(11 downto 0); + ADC_6_IN : in std_logic_vector(11 downto 0); + ADC_5_IN : in std_logic_vector(11 downto 0); + ADC_4_IN : in std_logic_vector(11 downto 0); + ADC_3_IN : in std_logic_vector(11 downto 0); + ADC_2_IN : in std_logic_vector(11 downto 0); + ADC_1_IN : in std_logic_vector(11 downto 0); + ADC_0_IN : in std_logic_vector(11 downto 0); + ADC_CH_OUT : out std_logic_vector(11 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component adc_channel_select; + +component slv_adc_snoop is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(9 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from + ADC_CLK_IN : in std_logic; -- ADC reconstructed clock + ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component slv_adc_snoop; + +component adc_snoop_mem is +port( + WRADDRESS : in std_logic_vector(9 downto 0); + RDADDRESS : in std_logic_vector(9 downto 0); + DATA : in std_logic_vector(15 downto 0); + WE : in std_logic; + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + WRCLOCK : in std_logic; + WRCLOCKEN : in std_logic; + Q : out std_logic_vector(15 downto 0) +); +end component adc_snoop_mem; + +component max_data is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TODO_3_IN : in std_logic_vector(3 downto 0); + TODO_2_IN : in std_logic_vector(3 downto 0); + TODO_1_IN : in std_logic_vector(3 downto 0); + TODO_0_IN : in std_logic_vector(3 downto 0); + TODO_MAX_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component max_data; + +component comp4bit is +port( + DATAA : in std_logic_vector(3 downto 0); + DATAB : in std_logic_vector(3 downto 0); + AGTB : out std_logic +); +end component comp4bit; + +component slv_register_bank is +generic( + RESET_VALUE : std_logic_vector(15 downto 0) := x"0001" +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(3 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + BACKPLANE_IN : in std_logic_vector(2 downto 0); + CTRL_0_OUT : out std_logic_vector(15 downto 0); + CTRL_1_OUT : out std_logic_vector(15 downto 0); + CTRL_2_OUT : out std_logic_vector(15 downto 0); + CTRL_3_OUT : out std_logic_vector(15 downto 0); + CTRL_4_OUT : out std_logic_vector(15 downto 0); + CTRL_5_OUT : out std_logic_vector(15 downto 0); + CTRL_6_OUT : out std_logic_vector(15 downto 0); + CTRL_7_OUT : out std_logic_vector(15 downto 0); + CTRL_8_OUT : out std_logic_vector(15 downto 0); + CTRL_9_OUT : out std_logic_vector(15 downto 0); + CTRL_10_OUT : out std_logic_vector(15 downto 0); + CTRL_11_OUT : out std_logic_vector(15 downto 0); + CTRL_12_OUT : out std_logic_vector(15 downto 0); + CTRL_13_OUT : out std_logic_vector(15 downto 0); + CTRL_14_OUT : out std_logic_vector(15 downto 0); + CTRL_15_OUT : out std_logic_vector(15 downto 0); + STAT_0_IN : in std_logic_vector(15 downto 0); + STAT_1_IN : in std_logic_vector(15 downto 0); + STAT_2_IN : in std_logic_vector(15 downto 0); + STAT_3_IN : in std_logic_vector(15 downto 0); + STAT_4_IN : in std_logic_vector(15 downto 0); + STAT_5_IN : in std_logic_vector(15 downto 0); + STAT_6_IN : in std_logic_vector(15 downto 0); + STAT_7_IN : in std_logic_vector(15 downto 0); + STAT_8_IN : in std_logic_vector(15 downto 0); + STAT_9_IN : in std_logic_vector(15 downto 0); + STAT_10_IN : in std_logic_vector(15 downto 0); + STAT_11_IN : in std_logic_vector(15 downto 0); + STAT_12_IN : in std_logic_vector(15 downto 0); + STAT_13_IN : in std_logic_vector(15 downto 0); + STAT_14_IN : in std_logic_vector(15 downto 0); + STAT_15_IN : in std_logic_vector(15 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component slv_register_bank; + +component pulse_stretch is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + PULSE_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component pulse_stretch; + +component apv_adc_map_mem is +port( + ADDRESS : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) +); +end component apv_adc_map_mem; + +component adc_apv_map_mem is +port( + ADDRESS : in std_logic_vector(6 downto 0); + Q : out std_logic_vector(3 downto 0) +); +end component adc_apv_map_mem; + +component ped_thr_true is +port( + DATAINA : in std_logic_vector(17 downto 0); + DATAINB : in std_logic_vector(17 downto 0); + ADDRESSA : in std_logic_vector(6 downto 0); + ADDRESSB : in std_logic_vector(6 downto 0); + CLOCKA : in std_logic; + CLOCKB : in std_logic; + CLOCKENA : in std_logic; + CLOCKENB : in std_logic; + WRA : in std_logic; + WRB : in std_logic; + RESETA : in std_logic; + RESETB : in std_logic; + QA : out std_logic_vector(17 downto 0); + QB : out std_logic_vector(17 downto 0) +); +end component ped_thr_true; + +component slv_ped_thr_mem is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(10 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- backplane identifier + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(6 downto 0); + MEM_0_D_OUT : out std_logic_vector(17 downto 0); + MEM_1_D_OUT : out std_logic_vector(17 downto 0); + MEM_2_D_OUT : out std_logic_vector(17 downto 0); + MEM_3_D_OUT : out std_logic_vector(17 downto 0); + MEM_4_D_OUT : out std_logic_vector(17 downto 0); + MEM_5_D_OUT : out std_logic_vector(17 downto 0); + MEM_6_D_OUT : out std_logic_vector(17 downto 0); + MEM_7_D_OUT : out std_logic_vector(17 downto 0); + MEM_8_D_OUT : out std_logic_vector(17 downto 0); + MEM_9_D_OUT : out std_logic_vector(17 downto 0); + MEM_10_D_OUT : out std_logic_vector(17 downto 0); + MEM_11_D_OUT : out std_logic_vector(17 downto 0); + MEM_12_D_OUT : out std_logic_vector(17 downto 0); + MEM_13_D_OUT : out std_logic_vector(17 downto 0); + MEM_14_D_OUT : out std_logic_vector(17 downto 0); + MEM_15_D_OUT : out std_logic_vector(17 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component slv_ped_thr_mem; + +component reset_handler is +port( + CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0') + RESET_IN : in std_logic; -- for testing, if not needed, set to '0' + CLK_IN : in std_logic; + TRB_RESET_IN : in std_logic; + RESET_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component reset_handler; + +component pll_40m is +port( + CLK : in std_logic; + RESET : in std_logic; + DPAMODE : in std_logic; + DPHASE0 : in std_logic; + DPHASE1 : in std_logic; + DPHASE2 : in std_logic; + DPHASE3 : in std_logic; + CLKOP : out std_logic; + CLKOS : out std_logic; + LOCK : out std_logic +); +end component pll_40m; + +component dll_100m is +port( + CLK : in std_logic; + RESETN : in std_logic; + ALUHOLD : in std_logic; + CLKOP : out std_logic; + CLKOS : out std_logic; + LOCK : out std_logic +); +end component dll_100m; + +component state_sync is +port( + STATE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + STATE_B_OUT : out std_logic + ); +end component state_sync; + +component pulse_sync is +port( + CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic +); +end component pulse_sync; + +component rich_trb is +port( + CLK100M_IN : in std_logic; + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_PRESENT_IN : in std_logic; + SD_TXDIS_OUT : out std_logic; + SD_LOS_IN : in std_logic; + ONEWIRE_INOUT : inout std_logic; + -- common regIO status / control registers +-- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI + COMMON_STAT_REG_IN : in std_logic_vector(2*32-1 downto 0); -- common status register, bit definitions like in WIKI +-- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI + COMMON_CTRL_REG_OUT : out std_logic_vector(2*32-1 downto 0); -- common control register, bit definitions like in WIKI + -- status register input to regIO / control register output from regIO + CONTROL_OUT : out std_logic_vector(63 downto 0); + STATUS_IN : in std_logic_vector(127 downto 0); + -- LVL1 signals + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_RECEIVED_OUT : out std_logic; + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_IN : in std_logic; + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_INT_TRG_UPDATE_OUT : out std_logic; + TIMING_TRG_FOUND_IN : in std_logic; + -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) + IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_OUT : out std_logic; -- gimme data! + IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_IN : in std_logic; -- data is valid + IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM + IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle + IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern + -- regIO bus +-- REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; +-- REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); +-- REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0); + REGIO_DATAREADY_IN : in std_logic; + REGIO_NO_MORE_DATA_IN : in std_logic; + REGIO_WRITE_ACK_IN : in std_logic; + REGIO_UNKNOWN_ADDR_IN : in std_logic; + REGIO_TIMEOUT_OUT : out std_logic; + -- status LEDs + LED_LINK_STAT : out std_logic; + LED_LINK_TXD : out std_logic; + LED_LINK_RXD : out std_logic; + LINK_BSM_OUT : out std_logic_vector(3 downto 0); + RESET_OUT : out std_logic; + -- Debug + DEBUG : out std_logic_vector(63 downto 0) +); +end component rich_trb; + +component slave_bus is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- RegIO signals + REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus + REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint + REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint + REGIO_READ_ENABLE_IN : in std_logic; -- read pulse + REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse + REGIO_TIMEOUT_IN : in std_logic; -- access timed out + REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested + REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted + REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now + REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- 1Wire connections + ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse) + ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); -- 1Wire ID on APV FEs + BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + -- ADC 0 SPI connections + SPI_ADC0_CS_OUT : out std_logic; + SPI_ADC0_SCK_OUT : out std_logic; + SPI_ADC0_SDO_OUT : out std_logic; + ADC0_PLL_LOCKED_IN : in std_logic; + ADC0_PD_OUT : out std_logic; + ADC0_RST_OUT : out std_logic; + ADC0_DEL_OUT : out std_logic_vector(3 downto 0); + ADC0_CLK_IN : in std_logic; + ADC0_DATA_IN : in std_logic_vector(11 downto 0); + ADC0_SEL_OUT : out std_logic_vector(2 downto 0); + APV0_RST_OUT : out std_logic; + -- ADC 0 SPI connections + SPI_ADC1_CS_OUT : out std_logic; + SPI_ADC1_SCK_OUT : out std_logic; + SPI_ADC1_SDO_OUT : out std_logic; + ADC1_PLL_LOCKED_IN : in std_logic; + ADC1_PD_OUT : out std_logic; + ADC1_RST_OUT : out std_logic; + ADC1_DEL_OUT : out std_logic_vector(3 downto 0); + ADC1_CLK_IN : in std_logic; + ADC1_DATA_IN : in std_logic_vector(11 downto 0); + ADC1_SEL_OUT : out std_logic_vector(2 downto 0); + APV1_RST_OUT : out std_logic; + -- User specific inputs / outputs + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- pedestal interface + PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers + PED_DATA_0_OUT : out std_logic_vector(17 downto 0); + PED_DATA_1_OUT : out std_logic_vector(17 downto 0); + PED_DATA_2_OUT : out std_logic_vector(17 downto 0); + PED_DATA_3_OUT : out std_logic_vector(17 downto 0); + PED_DATA_4_OUT : out std_logic_vector(17 downto 0); + PED_DATA_5_OUT : out std_logic_vector(17 downto 0); + PED_DATA_6_OUT : out std_logic_vector(17 downto 0); + PED_DATA_7_OUT : out std_logic_vector(17 downto 0); + PED_DATA_8_OUT : out std_logic_vector(17 downto 0); + PED_DATA_9_OUT : out std_logic_vector(17 downto 0); + PED_DATA_10_OUT : out std_logic_vector(17 downto 0); + PED_DATA_11_OUT : out std_logic_vector(17 downto 0); + PED_DATA_12_OUT : out std_logic_vector(17 downto 0); + PED_DATA_13_OUT : out std_logic_vector(17 downto 0); + PED_DATA_14_OUT : out std_logic_vector(17 downto 0); + PED_DATA_15_OUT : out std_logic_vector(17 downto 0); + -- threshold interface + THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers + THR_DATA_0_OUT : out std_logic_vector(17 downto 0); + THR_DATA_1_OUT : out std_logic_vector(17 downto 0); + THR_DATA_2_OUT : out std_logic_vector(17 downto 0); + THR_DATA_3_OUT : out std_logic_vector(17 downto 0); + THR_DATA_4_OUT : out std_logic_vector(17 downto 0); + THR_DATA_5_OUT : out std_logic_vector(17 downto 0); + THR_DATA_6_OUT : out std_logic_vector(17 downto 0); + THR_DATA_7_OUT : out std_logic_vector(17 downto 0); + THR_DATA_8_OUT : out std_logic_vector(17 downto 0); + THR_DATA_9_OUT : out std_logic_vector(17 downto 0); + THR_DATA_10_OUT : out std_logic_vector(17 downto 0); + THR_DATA_11_OUT : out std_logic_vector(17 downto 0); + THR_DATA_12_OUT : out std_logic_vector(17 downto 0); + THR_DATA_13_OUT : out std_logic_vector(17 downto 0); + THR_DATA_14_OUT : out std_logic_vector(17 downto 0); + THR_DATA_15_OUT : out std_logic_vector(17 downto 0); + -- APV control / status + CTRL_0_OUT : out std_logic_vector(15 downto 0); + CTRL_1_OUT : out std_logic_vector(15 downto 0); + CTRL_2_OUT : out std_logic_vector(15 downto 0); + CTRL_3_OUT : out std_logic_vector(15 downto 0); + CTRL_4_OUT : out std_logic_vector(15 downto 0); + CTRL_5_OUT : out std_logic_vector(15 downto 0); + CTRL_6_OUT : out std_logic_vector(15 downto 0); + CTRL_7_OUT : out std_logic_vector(15 downto 0); + CTRL_8_OUT : out std_logic_vector(15 downto 0); + CTRL_9_OUT : out std_logic_vector(15 downto 0); + CTRL_10_OUT : out std_logic_vector(15 downto 0); + CTRL_11_OUT : out std_logic_vector(15 downto 0); + CTRL_12_OUT : out std_logic_vector(15 downto 0); + CTRL_13_OUT : out std_logic_vector(15 downto 0); + CTRL_14_OUT : out std_logic_vector(15 downto 0); + CTRL_15_OUT : out std_logic_vector(15 downto 0); + STAT_0_IN : in std_logic_vector(15 downto 0); + STAT_1_IN : in std_logic_vector(15 downto 0); + STAT_2_IN : in std_logic_vector(15 downto 0); + STAT_3_IN : in std_logic_vector(15 downto 0); + STAT_4_IN : in std_logic_vector(15 downto 0); + STAT_5_IN : in std_logic_vector(15 downto 0); + STAT_6_IN : in std_logic_vector(15 downto 0); + STAT_7_IN : in std_logic_vector(15 downto 0); + STAT_8_IN : in std_logic_vector(15 downto 0); + STAT_9_IN : in std_logic_vector(15 downto 0); + STAT_10_IN : in std_logic_vector(15 downto 0); + STAT_11_IN : in std_logic_vector(15 downto 0); + STAT_12_IN : in std_logic_vector(15 downto 0); + STAT_13_IN : in std_logic_vector(15 downto 0); + STAT_14_IN : in std_logic_vector(15 downto 0); + STAT_15_IN : in std_logic_vector(15 downto 0); + -- some control signals + CTRL_LVL_OUT : out std_logic_vector(31 downto 0); + CTRL_TRG_OUT : out std_logic_vector(31 downto 0); + CTRL_PLL_OUT : out std_logic_vector(15 downto 0); + STATUS_PLL_IN : in std_logic_vector(15 downto 0); + -- temporary stuff + TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing! + TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing! + -- Debug + DEBUG_OUT : out std_logic_vector(63 downto 0); + STAT : out std_logic_vector(31 downto 0) +); +end component slave_bus; + +component oddrxc is +port( + DA : in std_logic; + DB : in std_logic; + CLK : in std_logic; + RST : in std_logic; + Q : out std_logic +); +end component oddrxc; + +component apv_trgctrl is +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + -- Triggers + SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs + TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs + TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs + STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow + TRG_FOUND_OUT : out std_logic; -- trigger found + SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number + -- slow control settings + TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event + TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 + TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 + TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 + TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 + TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers + -- TRB LVL1 signals + TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag + TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag + TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type + TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- TRB LVL1 trigger information + TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received + TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger + TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel + TRB_COUNTER_OUT : out std_logic_vector(15 downto 0); + TRB_COUNTER_IN : in std_logic_vector(15 downto 0); + TRB_LD_COUNTER_IN : in std_logic; + -- EDS signals + EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word + EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done + EDS_DONE_IN : in std_logic; -- release current EDS buffer + EDS_FULL_OUT : out std_logic; -- EDS buffer is full + EDS_LEVEL_OUT : out std_logic_vector(4 downto 0); + FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement) + -- APV signals + APV_TRG_OUT : out std_logic; + APV_SYNC_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component apv_trgctrl; + +component ped_corr_ctrl is +port( + CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control registers + -- EDS buffer -- back to previous source stage + EDS_DATA_IN : in std_logic_vector(39 downto 0); + EDS_AVAIL_IN : in std_logic; + EDS_DONE_OUT : out std_logic; + -- DHDR information -- to next stage + DHDR_DATA_OUT : out std_logic_vector(31 downto 0); + DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0); + DHDR_STORE_OUT : out std_logic; + DHDR_BUF_FULL_IN : in std_logic; + FIFO_SPACE_REQ_OUT : out std_logic_vector(11 downto 0); + -- data buffers -- from raw_buf_stage + BUF_ADDR_OUT : out std_logic_vector(6 downto 0); + BUF_DONE_OUT : out std_logic; + BUF_TICK_IN : in std_logic_vector(15 downto 0); + BUF_START_IN : in std_logic_vector(15 downto 0); + -- raw data + BUF_0_DATA_IN : in std_logic_vector(37 downto 0); + BUF_1_DATA_IN : in std_logic_vector(37 downto 0); + BUF_2_DATA_IN : in std_logic_vector(37 downto 0); + BUF_3_DATA_IN : in std_logic_vector(37 downto 0); + BUF_4_DATA_IN : in std_logic_vector(37 downto 0); + BUF_5_DATA_IN : in std_logic_vector(37 downto 0); + BUF_6_DATA_IN : in std_logic_vector(37 downto 0); + BUF_7_DATA_IN : in std_logic_vector(37 downto 0); + BUF_8_DATA_IN : in std_logic_vector(37 downto 0); + BUF_9_DATA_IN : in std_logic_vector(37 downto 0); + BUF_10_DATA_IN : in std_logic_vector(37 downto 0); + BUF_11_DATA_IN : in std_logic_vector(37 downto 0); + BUF_12_DATA_IN : in std_logic_vector(37 downto 0); + BUF_13_DATA_IN : in std_logic_vector(37 downto 0); + BUF_14_DATA_IN : in std_logic_vector(37 downto 0); + BUF_15_DATA_IN : in std_logic_vector(37 downto 0); + -- Pedestal data + PED_ADDR_OUT : out std_logic_vector(6 downto 0); + PED_0_DATA_IN : in std_logic_vector(17 downto 0); + PED_1_DATA_IN : in std_logic_vector(17 downto 0); + PED_2_DATA_IN : in std_logic_vector(17 downto 0); + PED_3_DATA_IN : in std_logic_vector(17 downto 0); + PED_4_DATA_IN : in std_logic_vector(17 downto 0); + PED_5_DATA_IN : in std_logic_vector(17 downto 0); + PED_6_DATA_IN : in std_logic_vector(17 downto 0); + PED_7_DATA_IN : in std_logic_vector(17 downto 0); + PED_8_DATA_IN : in std_logic_vector(17 downto 0); + PED_9_DATA_IN : in std_logic_vector(17 downto 0); + PED_10_DATA_IN : in std_logic_vector(17 downto 0); + PED_11_DATA_IN : in std_logic_vector(17 downto 0); + PED_12_DATA_IN : in std_logic_vector(17 downto 0); + PED_13_DATA_IN : in std_logic_vector(17 downto 0); + PED_14_DATA_IN : in std_logic_vector(17 downto 0); + PED_15_DATA_IN : in std_logic_vector(17 downto 0); + -- Threshold data + THR_ADDR_OUT : out std_logic_vector(6 downto 0); + THR_0_DATA_IN : in std_logic_vector(17 downto 0); + THR_1_DATA_IN : in std_logic_vector(17 downto 0); + THR_2_DATA_IN : in std_logic_vector(17 downto 0); + THR_3_DATA_IN : in std_logic_vector(17 downto 0); + THR_4_DATA_IN : in std_logic_vector(17 downto 0); + THR_5_DATA_IN : in std_logic_vector(17 downto 0); + THR_6_DATA_IN : in std_logic_vector(17 downto 0); + THR_7_DATA_IN : in std_logic_vector(17 downto 0); + THR_8_DATA_IN : in std_logic_vector(17 downto 0); + THR_9_DATA_IN : in std_logic_vector(17 downto 0); + THR_10_DATA_IN : in std_logic_vector(17 downto 0); + THR_11_DATA_IN : in std_logic_vector(17 downto 0); + THR_12_DATA_IN : in std_logic_vector(17 downto 0); + THR_13_DATA_IN : in std_logic_vector(17 downto 0); + THR_14_DATA_IN : in std_logic_vector(17 downto 0); + THR_15_DATA_IN : in std_logic_vector(17 downto 0); + -- processed data + FIFO_START_OUT : out std_logic; + FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_WE_OUT : out std_logic_vector(15 downto 0); + FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component ped_corr_ctrl; + +component ipu_fifo_stage is +port( + CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control signals + SECTOR_IN : in std_logic_vector(2 downto 0); + MODULE_IN : in std_logic_vector(2 downto 0); + -- IPU channel connections + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_IN : in std_logic; -- gimme data! + IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_OUT : out std_logic; -- data is valid + IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM + IPU_READ_IN : in std_logic; -- read strobe, low every second cycle + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern + LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter + -- DHDR buffer input + DHDR_DATA_IN : in std_logic_vector(31 downto 0); + DHDR_LENGTH_IN : in std_logic_vector(15 downto 0); + DHDR_STORE_IN : in std_logic; + DHDR_BUF_FULL_OUT : out std_logic; + -- processed data input + FIFO_SPACE_REQ_IN : in std_logic_vector(11 downto 0); + FIFO_START_IN : in std_logic; + FIFO_0_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_1_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_2_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_3_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_4_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_5_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_6_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_7_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_8_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_9_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_10_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_11_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_12_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_13_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_14_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_15_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_WE_IN : in std_logic_vector(15 downto 0); + FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(63 downto 0) +); +end component ipu_fifo_stage; + +component ipu_dummy is +port( + CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control signals + MIN_COUNT_IN : in std_logic_vector(15 downto 0); -- minimum counter value + MAX_COUNT_IN : in std_logic_vector(15 downto 0); -- maximum counter value + CTRL_IN : in std_logic_vector(7 downto 0); -- control bits from slow control + -- IPU channel connections + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_IN : in std_logic; -- gimme data! + IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_OUT : out std_logic; -- data is valid + IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM + IPU_READ_IN : in std_logic; -- read strobe, low every second cycle + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern + -- DHDR buffer + LVL1_FIFO_RD_OUT : out std_logic; + LVL1_FIFO_EMPTY_IN : in std_logic; + LVL1_FIFO_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_FIFO_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_FIFO_INFORMATION_IN : in std_logic_vector(7 downto 0); + LVL1_FIFO_TYPE_IN : in std_logic_vector(3 downto 0); + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(63 downto 0) +); +end component ipu_dummy; + +component reboot_handler is +port( + RESET_IN : in std_logic; + CLK_IN : in std_logic; + START_IN : in std_logic; + REBOOT_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component reboot_handler; + +component real_trg_handler is +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs + TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs + APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse) + TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 + TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 + TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 + TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 + TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers + TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint + SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number + TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag + TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number + TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type + TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- LVL1 24bit trigger information + TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB + TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger + LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); -- LVL1 counter + LVL1_COUNTER_IN : in std_logic_vector(15 downto 0); + LVL1_LD_COUNTER_IN : in std_logic; + BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator + APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine + APV_TRGSTART_OUT : out std_logic; -- start one APV trigger state machine + EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data + EDS_WE_OUT : out std_logic; -- EDS write enable (general interface) + EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level + EDS_READY_OUT : out std_logic; -- APV trigger sequence done, TERMinate the TRB LVL1 trigger + DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(63 downto 0) +); +end component real_trg_handler; + +component apv_trg_handler is +port( + CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; -- synced reset signal (100MHz) + APV_TRGSTART_IN : in std_logic; -- start signal for one sequence + APV_TRGSEL_IN : in std_logic; -- select signal for one sequence + APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers + APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers + APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished + APV_TRG_OUT : out std_logic; + APV_TRGSENT_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_trg_handler; + +component apv_sync_handler is +port( + CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; -- synced reset signal (100MHz) + APV_TRGSTART_IN : in std_logic; -- start signal for one sequence + APV_TRGSEL_IN : in std_logic; -- select signal for one sequence + APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished + APV_TRG_OUT : out std_logic; + APV_SYNC_OUT : out std_logic; -- signal for statemachines + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_sync_handler; + +component eds_buf is +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + -- EDS input, all synced to CLK_IN + EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input + EDS_WE_IN : in std_logic; -- EDS write enable + EDS_DONE_IN : in std_logic; -- release EDS + EDS_DATA_OUT : out std_logic_vector(39 downto 0); + EDS_AVAILABLE_OUT : out std_logic; + -- trigger busy information + BUF_FULL_OUT : out std_logic; + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component eds_buf; + +component adc_pll is +port( + CLK : in std_logic; + RESET : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic +); +end component adc_pll; + +component adc_ch_in is +port( + DEL : in std_logic_vector(3 downto 0); + ECLK : in std_logic; + SCLK : in std_logic; + RST : in std_logic; + DATA : in std_logic_vector(0 downto 0); + Q : out std_logic_vector(1 downto 0) +); +End component adc_ch_in; + +component adc_twochannels is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + CLOCK_IN : in std_logic_vector(1 downto 0); -- DDR bit clock + DATA_0_IN : in std_logic_vector(1 downto 0); -- ADC channel one + DATA_1_IN : in std_logic_vector(1 downto 0); -- ADC channel two + DATA_0_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel one + DATA_1_OUT : out std_logic_vector(11 downto 0); -- demultiplexed ADC channel two + STORE_OUT : out std_logic; + SWAP_OUT : out std_logic; + CLOCK_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component adc_twochannels; + +component apv_locker is +port( + CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to ADC_CLK_IN + ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid + SYNC_IN : in std_logic; -- sync trigger input + APV_ON_IN : in std_logic; -- this APV channel is switched on + BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0' + BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1' + FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline + FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline + STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off) + STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet + STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid + STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully + STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong + STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully + STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected + STATUS_TICKMARK_OUT : out std_logic; + FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header + FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header + FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?) + FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow + FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow + FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames + APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID + APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high + APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low + APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data + APV_ANALOG_OUT : out std_logic; -- APV analog data is valid + APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer + APV_LAST_OUT : out std_logic; -- last APV channel of dataframe + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_locker; + +component apv_raw_buffer is +port( + CLK_APV_IN : in std_logic; -- write clock from APV handling stage + RESET_IN : in std_logic; + FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV + MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event + ADC_ANALOG_IN : in std_logic; -- write enable for ADC data + ADC_START_IN : in std_logic; -- data frame detected, block the buffer page + ADC_LAST_IN : in std_logic; -- last channel signal + ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID + ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR + ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV + ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame + BUF_CLK_IN : in std_logic; -- read clock + BUF_RESET_IN : in std_logic; -- 100MHz reset + BUF_START_OUT : out std_logic; -- one block starts writing + BUF_READY_OUT : out std_logic; -- one block has been written + BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer + BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer) + BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer + BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output + BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output + BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation + BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation + BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer + BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler + BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set! + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_raw_buffer; + +-- moved to trb_net_components.vhd +-- +--component slv_register is +--generic( +-- RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" +--); +--port( +-- CLK_IN : in std_logic; +-- RESET_IN : in std_logic; +-- BUSY_IN : in std_logic; +-- -- Slave bus +-- SLV_READ_IN : in std_logic; +-- SLV_WRITE_IN : in std_logic; +-- SLV_BUSY_OUT : out std_logic; +-- SLV_ACK_OUT : out std_logic; +-- SLV_DATA_IN : in std_logic_vector(31 downto 0); +-- SLV_DATA_OUT : out std_logic_vector(31 downto 0); +-- -- I/O to the backend +-- REG_DATA_IN : in std_logic_vector(31 downto 0); +-- REG_DATA_OUT : out std_logic_vector(31 downto 0); +-- -- Status lines +-- STAT : out std_logic_vector(31 downto 0) -- DEBUG +--); +--end component slv_register; + +component slv_half_register is +generic( + RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + STATUS_REG_IN : in std_logic_vector(15 downto 0); + CTRL_REG_OUT : out std_logic_vector(15 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component slv_half_register; + +component i2c_master is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component i2c_master; + +component slv_onewire_memory is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(5 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- backplane identifier + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- 1Wire lines + ONEWIRE_START_IN : in std_logic; + ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); + BP_ONEWIRE_INOUT : inout std_logic; + -- Status lines + STAT : out std_logic_vector(63 downto 0) -- DEBUG +); +end component slv_onewire_memory; + +component spi_real_slim is +port( + SYSCLK : in std_logic; -- 100MHz sysclock + RESET : in std_logic; -- synchronous reset + -- Command interface + START_IN : in std_logic; -- one start pulse + BUSY_OUT : out std_logic; -- SPI transactions are ongoing + CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte + -- SPI interface + SPI_SCK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; + -- DEBUG + CLK_EN_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) +); +end component spi_real_slim; + +component spi_adc_master is +generic( + RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + -- ADC connections + ADC_LOCKED_IN : in std_logic; + ADC_PD_OUT : out std_logic; + ADC_RST_OUT : out std_logic; + ADC_DEL_OUT : out std_logic_vector(3 downto 0); + -- APV connections + APV_RST_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component spi_adc_master; + +component i2c_slim is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- I2C command / setup + I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions + ACTION_IN : in std_logic; -- '0' -> write, '1' -> read + I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined) + I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte) + I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command + I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command + STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits + I2C_BUSY_OUT : out std_logic; + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- Debug + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end component i2c_slim; + +component i2c_gstart is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + DOSTART_IN : in std_logic; + I2C_SPEED_IN : in std_logic_vector(7 downto 0); + SDONE_OUT : out std_logic; + SOK_OUT : out std_logic; + SDA_IN : in std_logic; + SCL_IN : in std_logic; + R_SCL_OUT : out std_logic; + S_SCL_OUT : out std_logic; + R_SDA_OUT : out std_logic; + S_SDA_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0) +); +end component i2c_gstart; + +component i2c_sendb is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + DOBYTE_IN : in std_logic; + I2C_SPEED_IN : in std_logic_vector(7 downto 0); + I2C_BYTE_IN : in std_logic_vector(8 downto 0); + I2C_BACK_OUT : out std_logic_vector(8 downto 0); + SDA_IN : in std_logic; + R_SDA_OUT : out std_logic; + S_SDA_OUT : out std_logic; +-- SCL_IN : in std_logic; + R_SCL_OUT : out std_logic; + S_SCL_OUT : out std_logic; + BDONE_OUT : out std_logic; + BOK_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0) +); +end component i2c_sendb; + +component onewire_master is +generic( + CLK_PERIOD : integer := 10 -- clock perion in nanoseconds +); +port( + CLK : in std_logic; + RESET : in std_logic; + READOUT_ENABLE_IN : in std_logic; + -- connection to 1-wire interface (16 APV FEs) + ONEWIRE : inout std_logic_vector(15 downto 0); + BP_ONEWIRE : inout std_logic; + -- connection to external DPRAM for slow control readout + BP_DATA_OUT : out std_logic_vector(15 downto 0); + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(6 downto 0); + WRITE_OUT : out std_logic; + BUSY_OUT : out std_logic; + -- debug + BSM_OUT : out std_logic_vector(7 downto 0); + STAT : out std_logic_vector(15 downto 0) +); +end component onewire_master; + +component slv_onewire_dpram +port( + WRADDRESS : in std_logic_vector(6 downto 0); + RDADDRESS : in std_logic_vector(5 downto 0); + DATA : in std_logic_vector(15 downto 0); + WE : in std_logic; + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + WRCLOCK : in std_logic; + WRCLOCKEN : in std_logic; + Q : out std_logic_vector(31 downto 0) +); +end component slv_onewire_dpram; + +component fifo_2kx27 is +port( + DATA : in std_logic_vector(26 downto 0); + CLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(26 downto 0); + WCNT : out std_logic_vector(11 downto 0); + EMPTY : out std_logic; + FULL : out std_logic +); +end component fifo_2kx27; + +component fifo_1kx18 is +port( + DATA : in std_logic_vector(17 downto 0); + CLOCK : in std_logic; + WREN : in std_logic; + RDEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(17 downto 0); + WCNT : out std_logic_vector(10 downto 0); + EMPTY : out std_logic; + FULL : out std_logic +); +end component fifo_1kx18; + +component decoder_8bit is +port( + ADDRESS : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(3 downto 0) +); +end component decoder_8bit; + +component adder_5bit is +port( + DATAA : in std_logic_vector(4 downto 0); + DATAB : in std_logic_vector(4 downto 0); + CLOCK : in std_logic; + RESET : in std_logic; + CLOCKEN : in std_logic; + RESULT : out std_logic_vector(4 downto 0) +); +end component adder_5bit; + +component adder_16bit is +port( + DATAA : in std_logic_vector(15 downto 0); + DATAB : in std_logic_vector(15 downto 0); + CLOCK : in std_logic; + RESET : in std_logic; + CLOCKEN : in std_logic; + RESULT : out std_logic_vector(15 downto 0) +); +end component adder_16bit; + +component suber_12bit is +port( + DATAA : in std_logic_vector(11 downto 0); + DATAB : in std_logic_vector(11 downto 0); + CLOCK : in std_logic; + RESET : in std_logic; + CLOCKEN : in std_logic; + RESULT : out std_logic_vector(11 downto 0) +); +end component suber_12bit; + +component comp_12bit is +port( + DATAA : in std_logic_vector(11 downto 0); + DATAB : in std_logic_vector(11 downto 0); + CLOCK : in std_logic; + CLOCKEN : in std_logic; + ACLR : in std_logic; + AGTB : out std_logic +); +end component comp_12bit; + +component buf_toc is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUF_TICK_IN : in std_logic; -- tickmark from raw buffer + BUF_START_IN : in std_logic; -- start of frame from raw buffer + WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode + FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS + BUF_LVL_IN : in std_logic_vector(7 downto 0); + GOODDATA_OUT : out std_logic; + BADDATA_OUT : out std_logic; + NODATA_OUT : out std_logic; + READY_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component buf_toc; + +component ref_row_sel is +port( + CLK_IN : in std_logic; + READY_IN : in std_logic_vector(15 downto 0); + GOODDATA_IN : in std_logic_vector(15 downto 0); + FRAME_0_IN : in std_logic_vector(11 downto 0); + FRAME_1_IN : in std_logic_vector(11 downto 0); + FRAME_2_IN : in std_logic_vector(11 downto 0); + FRAME_3_IN : in std_logic_vector(11 downto 0); + FRAME_4_IN : in std_logic_vector(11 downto 0); + FRAME_5_IN : in std_logic_vector(11 downto 0); + FRAME_6_IN : in std_logic_vector(11 downto 0); + FRAME_7_IN : in std_logic_vector(11 downto 0); + FRAME_8_IN : in std_logic_vector(11 downto 0); + FRAME_9_IN : in std_logic_vector(11 downto 0); + FRAME_10_IN : in std_logic_vector(11 downto 0); + FRAME_11_IN : in std_logic_vector(11 downto 0); + FRAME_12_IN : in std_logic_vector(11 downto 0); + FRAME_13_IN : in std_logic_vector(11 downto 0); + FRAME_14_IN : in std_logic_vector(11 downto 0); + FRAME_15_IN : in std_logic_vector(11 downto 0); + VALID_BUFS_OUT : out std_logic; + READY_OUT : out std_logic; + ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong + APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit + APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0); + REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component ref_row_sel; + +component frmctr_check is +port( + CLK_IN : in std_logic; + GOODDATA_IN : in std_logic_vector(15 downto 0); + FRAMECOUNTER_IN : in std_logic_vector(3 downto 0); + FRM_NR_0_IN : in std_logic_vector(3 downto 0); + FRM_NR_1_IN : in std_logic_vector(3 downto 0); + FRM_NR_2_IN : in std_logic_vector(3 downto 0); + FRM_NR_3_IN : in std_logic_vector(3 downto 0); + FRM_NR_4_IN : in std_logic_vector(3 downto 0); + FRM_NR_5_IN : in std_logic_vector(3 downto 0); + FRM_NR_6_IN : in std_logic_vector(3 downto 0); + FRM_NR_7_IN : in std_logic_vector(3 downto 0); + FRM_NR_8_IN : in std_logic_vector(3 downto 0); + FRM_NR_9_IN : in std_logic_vector(3 downto 0); + FRM_NR_10_IN : in std_logic_vector(3 downto 0); + FRM_NR_11_IN : in std_logic_vector(3 downto 0); + FRM_NR_12_IN : in std_logic_vector(3 downto 0); + FRM_NR_13_IN : in std_logic_vector(3 downto 0); + FRM_NR_14_IN : in std_logic_vector(3 downto 0); + FRM_NR_15_IN : in std_logic_vector(3 downto 0); + FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component frmctr_check; + +component apv_pc_nc_alu is +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + START_IN : in std_logic; + MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested + CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number + LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG + EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG + BUF_GOOD_IN : in std_logic; + BUF_BAD_IN : in std_logic; + BUF_IGNORE_IN : in std_logic; + ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers + DO_HEADER_IN : in std_logic; + DO_ERROR_IN : in std_logic; + SUPPRESS_IN : in std_logic; + EVT_TYPE_IN : in std_logic_vector(2 downto 0); + RAW_ADDR_IN : in std_logic_vector(6 downto 0); + RAW_DATA_IN : in std_logic_vector(37 downto 0); + PED_DATA_IN : in std_logic_vector(17 downto 0); + THR_DATA_IN : in std_logic_vector(17 downto 0); + FRAME_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0] + WE_OUT : out std_logic; + COUNT_OUT : out std_logic_vector(9 downto 0); + ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_pc_nc_alu; + +component comp14bit is +port( + DATAA : in std_logic_vector(13 downto 0); + DATAB : in std_logic_vector(13 downto 0); + CLOCK : in std_logic; + CLOCKEN : in std_logic; + ACLR : in std_logic; + AGEB : out std_logic +); +end component comp14bit; + +component input_bram is +port( + WRADDRESS : in std_logic_vector(10 downto 0); + RDADDRESS : in std_logic_vector(10 downto 0); + DATA : in std_logic_vector(17 downto 0); + WE : in std_logic; + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + WRCLOCK : in std_logic; + WRCLOCKEN : in std_logic; + Q : out std_logic_vector(17 downto 0) +); +end component input_bram; + +component frame_status_mem is +port( + WRADDRESS : in std_logic_vector(3 downto 0); + DATA : in std_logic_vector(11 downto 0); + WRCLOCK : in std_logic; + WE : in std_logic; + WRCLOCKEN : in std_logic; + RDADDRESS : in std_logic_vector(3 downto 0); + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(11 downto 0) +); +end component frame_status_mem; + +component adder_6bit is +port( + DATAA : in std_logic_vector(5 downto 0); + DATAB : in std_logic_vector(5 downto 0); + CLOCK : in std_logic; + RESET : in std_logic; + CLOCKEN : in std_logic; + RESULT : out std_logic_vector(5 downto 0) +); +end component adder_6bit; + +component apv_lock_sm is +port( + CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + SYNC_IN : in std_logic; -- start APV synchronisation + ADC_VALID_IN : in std_logic; -- ADC delivers valid data + TIMED_IN : in std_logic; -- synchronisation timeout + MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter + LOCKED_IN : in std_logic; -- enough good tickmarks + TICK_IN : in std_logic; -- tickmark from digital parser + HEADER_IN : in std_logic; -- header from digital parser + FLATLINE_IN : in std_logic; -- flatline from digital parser + RST_PC_OUT : out std_logic; -- reset period counter + RST_TC_OUT : out std_logic; -- reset timeout counter + INC_TC_OUT : out std_logic; + RST_LC_OUT : out std_logic; -- reset lock counter + INC_LC_OUT : out std_logic; + UNKNOWN_OUT : out std_logic; + BADADC_OUT : out std_logic; -- ADC data invalid + LOCKED_OUT : out std_logic; + LOST_OUT : out std_logic; + NOSYNC_OUT : out std_logic; + NOAPV_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component apv_lock_sm; + +component apv_digital is +port( + CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + ADC_RAW_IN : in std_logic_vector(11 downto 0); + BIT_LOW_IN : in std_logic_vector(11 downto 0); + BIT_HIGH_IN : in std_logic_vector(11 downto 0); + FL_LOW_IN : in std_logic_vector(11 downto 0); + FL_HIGH_IN : in std_logic_vector(11 downto 0); + BIT_DATA_OUT : out std_logic_vector(11 downto 0); + BIT_VALID_OUT : out std_logic_vector(11 downto 0); + BIT_HIGH_OUT : out std_logic; + BIT_LOW_OUT : out std_logic; + TICKMARK_OUT : out std_logic; + HEADER_OUT : out std_logic; + FLAT_LINE_OUT : out std_logic +); +end component apv_digital; + +component eds_buffer_dpram is +port( + WRADDRESS : in std_logic_vector(3 downto 0); + DATA : in std_logic_vector(39 downto 0); + WRCLOCK : in std_logic; + WE : in std_logic; + WRCLOCKEN : in std_logic; + RDADDRESS : in std_logic_vector(3 downto 0); + RDCLOCK : in std_logic; + RDCLOCKEN : in std_logic; + RESET : in std_logic; + Q : out std_logic_vector(39 downto 0) +); +end component eds_buffer_dpram; end package; -- Down in the Dumps... +--component fifo_16x11 is +--port( +-- DATA : in std_logic_vector(10 downto 0); +-- CLOCK : in std_logic; +-- WREN : in std_logic; +-- RDEN : in std_logic; +-- RESET : in std_logic; +-- Q : out std_logic_vector(10 downto 0); +-- WCNT : out std_logic_vector(4 downto 0); +-- EMPTY : out std_logic; +-- FULL : out std_logic +--); +--end component fifo_16x11; + +--component dhdr_buf is +--port( +-- CLK_IN : in std_logic; -- 100MHz master clock +-- RESET_IN : in std_logic; +-- -- DHDR information block +-- DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input +-- DHDR_WE_IN : in std_logic; -- EDS write enable +-- DHDR_DONE_IN : in std_logic; -- release EDS +-- DHDR_DATA_OUT : out std_logic_vector(47 downto 0); +-- DHDR_AVAILABLE_OUT : out std_logic; +-- -- trigger busy information +-- BUF_FULL_OUT : out std_logic; +-- BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); +-- -- Debug signals +-- DEBUG_OUT : out std_logic_vector(15 downto 0) +--); +--end component dhdr_buf; + +--component dhdr_buffer_dpram is +--port( +-- WRADDRESS : in std_logic_vector(3 downto 0); +-- DATA : in std_logic_vector(47 downto 0); +-- WRCLOCK : in std_logic; +-- WE : in std_logic; +-- WRCLOCKEN : in std_logic; +-- RDADDRESS : in std_logic_vector(3 downto 0); +-- RDCLOCK : in std_logic; +-- RDCLOCKEN : in std_logic; +-- RESET : in std_logic; +-- Q : out std_logic_vector(47 downto 0) +--); +--end component; diff --git a/src/apv_digital.vhd b/src/apv_digital.vhd index a7dedc7..5b33a8b 100755 --- a/src/apv_digital.vhd +++ b/src/apv_digital.vhd @@ -7,52 +7,53 @@ library work; use work.adcmv3_components.all; entity apv_digital is - port( CLK_APV_IN : in std_logic; - RESET_IN : in std_logic; - ADC_RAW_IN : in std_logic_vector(11 downto 0); - BIT_LOW_IN : in std_logic_vector(11 downto 0); - BIT_HIGH_IN : in std_logic_vector(11 downto 0); - FL_LOW_IN : in std_logic_vector(11 downto 0); - FL_HIGH_IN : in std_logic_vector(11 downto 0); - BIT_DATA_OUT : out std_logic_vector(11 downto 0); - BIT_VALID_OUT : out std_logic_vector(11 downto 0); - BIT_HIGH_OUT : out std_logic; - BIT_LOW_OUT : out std_logic; - TICKMARK_OUT : out std_logic; - HEADER_OUT : out std_logic; - FLAT_LINE_OUT : out std_logic - ); +port( + CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + ADC_RAW_IN : in std_logic_vector(11 downto 0); + BIT_LOW_IN : in std_logic_vector(11 downto 0); + BIT_HIGH_IN : in std_logic_vector(11 downto 0); + FL_LOW_IN : in std_logic_vector(11 downto 0); + FL_HIGH_IN : in std_logic_vector(11 downto 0); + BIT_DATA_OUT : out std_logic_vector(11 downto 0); + BIT_VALID_OUT : out std_logic_vector(11 downto 0); + BIT_HIGH_OUT : out std_logic; + BIT_LOW_OUT : out std_logic; + TICKMARK_OUT : out std_logic; + HEADER_OUT : out std_logic; + FLAT_LINE_OUT : out std_logic + ); end; architecture behavioral of apv_digital is - signal next_bit_low : std_logic; - signal bit_low : std_logic; - signal next_bit_high : std_logic; - signal bit_high : std_logic; - signal next_bit_data : std_logic; - signal bit_data : std_logic_vector(11 downto 0); - signal next_bit_valid : std_logic; - signal bit_valid : std_logic_vector(11 downto 0); - signal next_fl_low : std_logic; - signal fl_low : std_logic; - signal next_fl_high : std_logic; - signal fl_high : std_logic; - signal next_fl_found : std_logic; - signal fl_found : std_logic_vector(2 downto 0); - signal next_flat_line : std_logic; - signal flat_line : std_logic; - signal next_tickmark : std_logic; - signal tickmark : std_logic; - signal next_header : std_logic; - signal header : std_logic; - +signal next_bit_low : std_logic; +signal bit_low : std_logic; +signal next_bit_high : std_logic; +signal bit_high : std_logic; +signal next_bit_data : std_logic; +signal bit_data : std_logic_vector(11 downto 0); +signal next_bit_valid : std_logic; +signal bit_valid : std_logic_vector(11 downto 0); +signal next_fl_low : std_logic; +signal fl_low : std_logic; +signal next_fl_high : std_logic; +signal fl_high : std_logic; +signal next_fl_found : std_logic; +signal fl_found : std_logic_vector(2 downto 0); +signal next_flat_line : std_logic; +signal flat_line : std_logic; +signal next_tickmark : std_logic; +signal tickmark : std_logic; +signal next_header : std_logic; +signal header : std_logic; + begin -- ADC data is registered already, so we can operate on the inputs directly. -------------------------------------------------------------------------------------- --- compare ADC raw data against "bit low" threshold, +-- compare ADC raw data against "bit low" threshold, -- generate combinatorial "low" bit THE_BL_COMP: process( adc_raw_in, bit_low_in ) begin @@ -63,7 +64,7 @@ begin end if; end process THE_BL_COMP; --- compare ADC raw data against "bit high" threshold, +-- compare ADC raw data against "bit high" threshold, --generate combinatorial "high" bit THE_BH_COMP: process( adc_raw_in, bit_high_in ) begin diff --git a/src/apv_lock_sm.vhd b/src/apv_lock_sm.vhd index 57b56f7..c4b5f54 100755 --- a/src/apv_lock_sm.vhd +++ b/src/apv_lock_sm.vhd @@ -7,99 +7,100 @@ library work; use work.adcmv3_components.all; entity apv_lock_sm is - port( CLK_APV_IN : in std_logic; - RESET_IN : in std_logic; - SYNC_IN : in std_logic; -- start APV synchronisation - ADC_VALID_IN : in std_logic; -- ADC delivers valid data - TIMED_IN : in std_logic; -- synchronisation timeout - MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter - LOCKED_IN : in std_logic; -- enough good tickmarks - TICK_IN : in std_logic; -- tickmark from digital parser - HEADER_IN : in std_logic; -- header from digital parser - FLATLINE_IN : in std_logic; -- flatline from digital parser - RST_PC_OUT : out std_logic; -- reset period counter - RST_TC_OUT : out std_logic; -- reset timeout counter - INC_TC_OUT : out std_logic; - RST_LC_OUT : out std_logic; -- reset lock counter - INC_LC_OUT : out std_logic; - UNKNOWN_OUT : out std_logic; -- status unknown - BADADC_OUT : out std_logic; -- ADC data invalid - LOCKED_OUT : out std_logic; -- APV locked successfully - LOST_OUT : out std_logic; -- APV sync is lost - NOSYNC_OUT : out std_logic; -- APV sync failed - NOAPV_OUT : out std_logic; -- no APV connected - BSM_OUT : out std_logic_vector(7 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + SYNC_IN : in std_logic; -- start APV synchronisation + ADC_VALID_IN : in std_logic; -- ADC delivers valid data + TIMED_IN : in std_logic; -- synchronisation timeout + MATCH_IN : in std_logic; -- artifical tickmark from synchronized counter + LOCKED_IN : in std_logic; -- enough good tickmarks + TICK_IN : in std_logic; -- tickmark from digital parser + HEADER_IN : in std_logic; -- header from digital parser + FLATLINE_IN : in std_logic; -- flatline from digital parser + RST_PC_OUT : out std_logic; -- reset period counter + RST_TC_OUT : out std_logic; -- reset timeout counter + INC_TC_OUT : out std_logic; + RST_LC_OUT : out std_logic; -- reset lock counter + INC_LC_OUT : out std_logic; + UNKNOWN_OUT : out std_logic; -- status unknown + BADADC_OUT : out std_logic; -- ADC data invalid + LOCKED_OUT : out std_logic; -- APV locked successfully + LOST_OUT : out std_logic; -- APV sync is lost + NOSYNC_OUT : out std_logic; -- APV sync failed + NOAPV_OUT : out std_logic; -- no APV connected + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); end; architecture behavioral of apv_lock_sm is - -- State definition - -- SLEEP : initial reset state - -- CLEAR : clear counters and registers - -- UWSYNC : wait for SYNC_IN to deassert - -- USYNC : teaching phase, not synchronized yet - -- U_BADM : tickmark found, but local counter mismatch - -- U_BADP : local counter match, but no tickmark found - -- U_GOOD : local counter and tickmark match - -- U_TIME : locking timed out - -- U_FLAT : no APV connected (open input) - -- U_ADC : ADC data is marked invaled (ser2par failed) - -- SYNCED : APV is locked, normal operation state - -- S_BADM : spurious tickmark found => fatal - -- S_BADM : missing tickmark => fatal - -- S_BADD : spurious data frame found, or bad tickmark after dataframe => fatal - -- S_GOOD : local counter and tickmark match - -- S_DATA : data frame header found at correct position - -- S_FR0 : first tickmark period of data frame - -- S_FR1 : second tickmark period of data frame - -- S_FR2 : third tickmark period of data frame - -- S_FR3 : fourth tickmark period of data frame - -- S_ADC : ADC data is marked invalid (ser2par failed) - -- S_LOST : lock lost in normal operation => fatal +-- State definition +-- SLEEP : initial reset state +-- CLEAR : clear counters and registers +-- UWSYNC : wait for SYNC_IN to deassert +-- USYNC : teaching phase, not synchronized yet +-- U_BADM : tickmark found, but local counter mismatch +-- U_BADP : local counter match, but no tickmark found +-- U_GOOD : local counter and tickmark match +-- U_TIME : locking timed out +-- U_FLAT : no APV connected (open input) +-- U_ADC : ADC data is marked invaled (ser2par failed) +-- SYNCED : APV is locked, normal operation state +-- S_BADM : spurious tickmark found => fatal +-- S_BADM : missing tickmark => fatal +-- S_BADD : spurious data frame found, or bad tickmark after dataframe => fatal +-- S_GOOD : local counter and tickmark match +-- S_DATA : data frame header found at correct position +-- S_FR0 : first tickmark period of data frame +-- S_FR1 : second tickmark period of data frame +-- S_FR2 : third tickmark period of data frame +-- S_FR3 : fourth tickmark period of data frame +-- S_ADC : ADC data is marked invalid (ser2par failed) +-- S_LOST : lock lost in normal operation => fatal - -- state machine signals - type STATES is (SLEEP, CLEAR, USYNC, UWSYNC, U_BADM, U_BADP, U_GOOD, U_TIME, U_FLAT, U_ADC, - SYNCED, S_BADP, S_BADM, S_GOOD, S_DATA, S_FR0, S_FR1, S_FR2, S_FR3, - S_BADD, S_LOST, S_ADC); - signal CURRENT_STATE, NEXT_STATE: STATES; +-- state machine signals +type STATES is (SLEEP, CLEAR, USYNC, UWSYNC, U_BADM, U_BADP, U_GOOD, U_TIME, U_FLAT, U_ADC, + SYNCED, S_BADP, S_BADM, S_GOOD, S_DATA, S_FR0, S_FR1, S_FR2, S_FR3, + S_BADD, S_LOST, S_ADC); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- normal signals +signal bsm : std_logic_vector(7 downto 0); +signal debug : std_logic_vector(15 downto 0); +signal next_rst_tc : std_logic; +signal rst_tc : std_logic; +signal next_inc_tc : std_logic; +signal inc_tc : std_logic; +signal next_rst_lc : std_logic; +signal rst_lc : std_logic; +signal next_inc_lc : std_logic; +signal inc_lc : std_logic; +signal next_rst_pc : std_logic; +signal rst_pc : std_logic; +signal next_unknown : std_logic; +signal unknown : std_logic; +signal next_badadc : std_logic; +signal badadc : std_logic; +signal next_locked : std_logic; +signal locked : std_logic; +signal next_lost : std_logic; +signal lost : std_logic; +signal next_nosync : std_logic; +signal nosync : std_logic; +signal next_noapv : std_logic; +signal noapv : std_logic; +signal next_dataframe : std_logic; +signal dataframe : std_logic; - -- normal signals - signal bsm : std_logic_vector(7 downto 0); - signal debug : std_logic_vector(15 downto 0); - signal next_rst_tc : std_logic; - signal rst_tc : std_logic; - signal next_inc_tc : std_logic; - signal inc_tc : std_logic; - signal next_rst_lc : std_logic; - signal rst_lc : std_logic; - signal next_inc_lc : std_logic; - signal inc_lc : std_logic; - signal next_rst_pc : std_logic; - signal rst_pc : std_logic; - signal next_unknown : std_logic; - signal unknown : std_logic; - signal next_badadc : std_logic; - signal badadc : std_logic; - signal next_locked : std_logic; - signal locked : std_logic; - signal next_lost : std_logic; - signal lost : std_logic; - signal next_nosync : std_logic; - signal nosync : std_logic; - signal next_noapv : std_logic; - signal noapv : std_logic; - signal next_dataframe : std_logic; - signal dataframe : std_logic; - begin debug <= (others => '0'); -- state machine for handling synchronisation -- state registers -STATE_MEM: process( clk_apv_in ) +STATE_MEM: process( clk_apv_in ) begin if( rising_edge(clk_apv_in) ) then if( reset_in = '1' ) then @@ -138,10 +139,10 @@ end process STATE_MEM; STATE_TRANSFORM: process( CURRENT_STATE, sync_in, match_in, tick_in, header_in, timed_in, locked_in, flatline_in, adc_valid_in ) begin NEXT_STATE <= SLEEP; -- avoid latches - next_rst_pc <= '0'; - next_rst_lc <= '0'; + next_rst_pc <= '0'; + next_rst_lc <= '0'; next_inc_lc <= '0'; - next_rst_tc <= '0'; + next_rst_tc <= '0'; next_inc_tc <= '0'; next_unknown <= '0'; next_badadc <= '0'; @@ -151,7 +152,7 @@ begin next_noapv <= '0'; next_dataframe <= '0'; case CURRENT_STATE is - when SLEEP => if( sync_in = '1' ) then + when SLEEP => if( sync_in = '1' ) then NEXT_STATE <= CLEAR; -- start synchronisation next_rst_pc <= '1'; next_rst_lc <= '1'; @@ -161,9 +162,9 @@ begin NEXT_STATE <= SLEEP; next_unknown <= '1'; end if; - when CLEAR => NEXT_STATE <= UWSYNC; + when CLEAR => NEXT_STATE <= UWSYNC; next_unknown <= '1'; - when UWSYNC => if ( (sync_in = '0') and (adc_valid_in = '1') ) then + when UWSYNC => if ( (sync_in = '0') and (adc_valid_in = '1') ) then NEXT_STATE <= USYNC; next_unknown <= '1'; elsif( (sync_in = '0') and (adc_valid_in = '0') ) then @@ -173,7 +174,7 @@ begin NEXT_STATE <= UWSYNC; next_unknown <= '1'; end if; - when USYNC => if ( (timed_in = '0') and (tick_in = '1') and (match_in = '0') ) then + when USYNC => if ( (timed_in = '0') and (tick_in = '1') and (match_in = '0') ) then NEXT_STATE <= U_BADM; -- local timer not correct next_rst_pc <= '1'; next_inc_tc <= '1'; @@ -202,13 +203,13 @@ begin NEXT_STATE <= USYNC; -- wait for events next_unknown <= '1'; end if; - when U_BADM => NEXT_STATE <= USYNC; + when U_BADM => NEXT_STATE <= USYNC; next_unknown <= '1'; - when U_BADP => NEXT_STATE <= USYNC; + when U_BADP => NEXT_STATE <= USYNC; next_unknown <= '1'; - when U_GOOD => NEXT_STATE <= USYNC; + when U_GOOD => NEXT_STATE <= USYNC; next_unknown <= '1'; - when U_FLAT => if( sync_in = '1' ) then + when U_FLAT => if( sync_in = '1' ) then NEXT_STATE <= CLEAR; -- next try next_rst_pc <= '1'; next_rst_lc <= '1'; @@ -222,7 +223,7 @@ begin NEXT_STATE <= U_FLAT; next_noapv <= '1'; end if; - when U_TIME => if( sync_in = '1' ) then + when U_TIME => if( sync_in = '1' ) then NEXT_STATE <= CLEAR; -- next try next_rst_pc <= '1'; next_rst_lc <= '1'; @@ -236,7 +237,7 @@ begin NEXT_STATE <= U_TIME; next_nosync <= '1'; end if; - when U_ADC => if( sync_in = '1' ) then + when U_ADC => if( sync_in = '1' ) then NEXT_STATE <= CLEAR; -- next try next_rst_pc <= '1'; next_rst_lc <= '1'; @@ -250,7 +251,7 @@ begin NEXT_STATE <= U_ADC; next_badadc <= '1'; end if; - when SYNCED => if ( sync_in = '1' ) then + when SYNCED => if ( sync_in = '1' ) then NEXT_STATE <= CLEAR; next_rst_pc <= '1'; next_rst_lc <= '1'; @@ -282,9 +283,9 @@ begin NEXT_STATE <= SYNCED; next_locked <= '1'; end if; - when S_GOOD => NEXT_STATE <= SYNCED; + when S_GOOD => NEXT_STATE <= SYNCED; next_locked <= '1'; - when S_DATA => if( sync_in = '1' ) then + when S_DATA => if( sync_in = '1' ) then NEXT_STATE <= CLEAR; next_rst_pc <= '1'; next_rst_lc <= '1'; @@ -299,7 +300,7 @@ begin next_dataframe <= '1'; next_locked <= '1'; end if; - when S_FR0 => if ( sync_in = '1' ) then + when S_FR0 => if ( sync_in = '1' ) then NEXT_STATE <= CLEAR; next_rst_pc <= '1'; next_rst_lc <= '1'; @@ -318,7 +319,7 @@ begin next_dataframe <= '1'; next_locked <= '1'; end if; - when S_FR1 => if ( sync_in = '1' ) then + when S_FR1 => if ( sync_in = '1' ) then NEXT_STATE <= CLEAR; next_rst_pc <= '1'; next_rst_lc <= '1'; @@ -337,7 +338,7 @@ begin next_dataframe <= '1'; next_locked <= '1'; end if; - when S_FR2 => if ( sync_in = '1' ) then + when S_FR2 => if ( sync_in = '1' ) then NEXT_STATE <= CLEAR; next_rst_pc <= '1'; next_rst_lc <= '1'; @@ -356,7 +357,7 @@ begin next_dataframe <= '1'; next_locked <= '1'; end if; - when S_FR3 => if ( sync_in = '1' ) then + when S_FR3 => if ( sync_in = '1' ) then NEXT_STATE <= CLEAR; next_rst_pc <= '1'; next_rst_lc <= '1'; @@ -379,15 +380,15 @@ begin next_dataframe <= '1'; next_locked <= '1'; end if; - when S_BADD => NEXT_STATE <= S_LOST; + when S_BADD => NEXT_STATE <= S_LOST; next_lost <= '1'; - when S_BADM => NEXT_STATE <= S_LOST; + when S_BADM => NEXT_STATE <= S_LOST; next_lost <= '1'; - when S_BADP => NEXT_STATE <= S_LOST; + when S_BADP => NEXT_STATE <= S_LOST; next_lost <= '1'; - when S_ADC => NEXT_STATE <= S_LOST; + when S_ADC => NEXT_STATE <= S_LOST; next_lost <= '1'; - when S_LOST => if( sync_in = '1' ) then + when S_LOST => if( sync_in = '1' ) then NEXT_STATE <= CLEAR; -- next try next_rst_pc <= '1'; next_rst_lc <= '1'; @@ -401,7 +402,7 @@ begin NEXT_STATE <= S_LOST; next_lost <= '1'; end if; - when others => NEXT_STATE <= SLEEP; + when others => NEXT_STATE <= SLEEP; next_unknown <= '1'; end case; end process STATE_TRANSFORM; @@ -410,29 +411,29 @@ end process STATE_TRANSFORM; STATE_DECODE: process( CURRENT_STATE ) begin case CURRENT_STATE is - when SLEEP => bsm <= x"00"; - when CLEAR => bsm <= x"01"; - when UWSYNC => bsm <= x"20"; - when USYNC => bsm <= x"02"; - when U_BADM => bsm <= x"03"; - when U_BADP => bsm <= x"04"; - when U_FLAT => bsm <= x"05"; - when U_GOOD => bsm <= x"06"; - when U_TIME => bsm <= x"07"; - when U_ADC => bsm <= x"08"; - when SYNCED => bsm <= x"09"; - when S_BADP => bsm <= x"0a"; - when S_BADM => bsm <= x"0b"; - when S_GOOD => bsm <= x"0c"; - when S_DATA => bsm <= x"0d"; - when S_FR0 => bsm <= x"0e"; - when S_FR1 => bsm <= x"0f"; - when S_FR2 => bsm <= x"10"; - when S_FR3 => bsm <= x"11"; - when S_BADD => bsm <= x"12"; - when S_ADC => bsm <= x"13"; - when S_LOST => bsm <= x"14"; - when others => bsm <= x"ff"; + when SLEEP => bsm <= x"00"; + when CLEAR => bsm <= x"01"; + when UWSYNC => bsm <= x"20"; + when USYNC => bsm <= x"02"; + when U_BADM => bsm <= x"03"; + when U_BADP => bsm <= x"04"; + when U_FLAT => bsm <= x"05"; + when U_GOOD => bsm <= x"06"; + when U_TIME => bsm <= x"07"; + when U_ADC => bsm <= x"08"; + when SYNCED => bsm <= x"09"; + when S_BADP => bsm <= x"0a"; + when S_BADM => bsm <= x"0b"; + when S_GOOD => bsm <= x"0c"; + when S_DATA => bsm <= x"0d"; + when S_FR0 => bsm <= x"0e"; + when S_FR1 => bsm <= x"0f"; + when S_FR2 => bsm <= x"10"; + when S_FR3 => bsm <= x"11"; + when S_BADD => bsm <= x"12"; + when S_ADC => bsm <= x"13"; + when S_LOST => bsm <= x"14"; + when others => bsm <= x"ff"; end case; end process STATE_DECODE; diff --git a/src/apv_locker.vhd b/src/apv_locker.vhd index ee48a47..e40cff3 100755 --- a/src/apv_locker.vhd +++ b/src/apv_locker.vhd @@ -6,128 +6,129 @@ use ieee.std_logic_unsigned.all; library work; use work.adcmv3_components.all; --- This block takes care of syncing in the APVs. Only "synced" APVs are allowed to deliver data streams --- to the processing units. +-- This block takes care of syncing in the APVs. Only "synced" APVs are allowed to deliver data streams +-- to the processing units. entity apv_locker is - port( CLK_APV_IN : in std_logic; - RESET_IN : in std_logic; - ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to CLK_APV_IN - ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid - -- Slow control input, mainly digital thresholds here - SYNC_IN : in std_logic; -- sync pulse input - APV_ON_IN : in std_logic; -- this APV channel is switched on - BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0' - BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1' - FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline - FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline - -- Generic APV status outputs (valid only if ADC_CLK_IN is working!) - STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off) - STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid - STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet - STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully - STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong - STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully - STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected - STATUS_TICKMARK_OUT : out std_logic; - -- Frame related status, to be stored in the raw status buffer - -- Information is valid with APV_LAST_OUT, except FRAME_ERROR_OUT, FRAME_ROW_OUT and - -- FRAME_CTR_OUT which are valid with beginning of APV_ANALOG_OUT. - FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header - FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header - FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?) - FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow - FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow - FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames - -- Channel related information, to be stored in the raw data buffer - APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID - APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high - APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low - APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data - APV_ANALOG_OUT : out std_logic; -- APV analog data is valid - APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer - APV_LAST_OUT : out std_logic; -- last APV channel of dataframe - -- Debug information - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_APV_IN : in std_logic; + RESET_IN : in std_logic; + ADC_RAW_IN : in std_logic_vector(11 downto 0); -- ADC: raw data, synchronous to CLK_APV_IN + ADC_VALID_IN : in std_logic; -- ADC: ser2par data is valid + -- Slow control input, mainly digital thresholds here + SYNC_IN : in std_logic; -- sync pulse input + APV_ON_IN : in std_logic; -- this APV channel is switched on + BIT_LOW_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '0' + BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- slow control: threshold for digital '1' + FL_LOW_IN : in std_logic_vector(11 downto 0); -- lower threshold for ADC flatline + FL_HIGH_IN : in std_logic_vector(11 downto 0); -- upper threshold for ADC flatline + -- Generic APV status outputs (valid only if ADC_CLK_IN is working!) + STATUS_IGNORE_OUT : out std_logic; -- APV is to be ignored (effectively => switched off) + STATUS_BADADC_OUT : out std_logic; -- ADC ser2par data is invalid + STATUS_UNKNOWN_OUT : out std_logic; -- APV is not initialized yet + STATUS_LOCKED_OUT : out std_logic; -- APV locked successfully + STATUS_LOST_OUT : out std_logic; -- APV tickmark missing or wrong + STATUS_NOSYNC_OUT : out std_logic; -- APV did not lock successfully + STATUS_MISSING_OUT : out std_logic; -- APV is missing, ADC flatline detected + STATUS_TICKMARK_OUT : out std_logic; + -- Frame related status, to be stored in the raw status buffer + -- Information is valid with APV_LAST_OUT, except FRAME_ERROR_OUT, FRAME_ROW_OUT and + -- FRAME_CTR_OUT which are valid with beginning of APV_ANALOG_OUT. + FRAME_ROW_OUT : out std_logic_vector(7 downto 0); -- decoded row from APV header + FRAME_ERROR_OUT : out std_logic; -- decoded error bit from APV header + FRAME_FLAT_OUT : out std_logic; -- APV sends a flat line (analog dead?) + FRAME_OVF_OUT : out std_logic; -- at least one channel in frame was overflow + FRAME_UDF_OUT : out std_logic; -- at least one channel in frame was underflow + FRAME_CTR_OUT : out std_logic_vector(3 downto 0); -- frame counter for incoming data frames + -- Channel related information, to be stored in the raw data buffer + APV_CHANNEL_OUT : out std_logic_vector(6 downto 0); -- physical channel ID + APV_OVERFLOW_OUT : out std_logic; -- channel is truncated high + APV_UNDERFLOW_OUT : out std_logic; -- channel is truncated low + APV_RAW_OUT : out std_logic_vector(11 downto 0); -- APV raw data + APV_ANALOG_OUT : out std_logic; -- APV analog data is valid + APV_START_OUT : out std_logic; -- valid data frame found, reserve one buffer + APV_LAST_OUT : out std_logic; -- last APV channel of dataframe + -- Debug information + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of apv_locker is - -- normal signals - signal lock_bsm : std_logic_vector(7 downto 0); - signal tickmark_found : std_logic; - signal header_found : std_logic; - signal flatline_found : std_logic; - signal status_unknown : std_logic; - signal status_badadc : std_logic; - signal status_locked : std_logic; - signal status_lost : std_logic; - signal status_nosync : std_logic; - signal status_missing : std_logic; - signal next_status_ignore : std_logic; - signal status_ignore : std_logic; - signal frame_flat : std_logic; - signal next_frame_ovf : std_logic; - signal frame_ovf : std_logic; - signal next_frame_udf : std_logic; - signal frame_udf : std_logic; - signal frame_row : std_logic_vector(7 downto 0); - signal frame_error : std_logic; - signal bit_data : std_logic_vector(11 downto 0); - signal bit_valid : std_logic_vector(11 downto 0); - - signal rst_pc_sm : std_logic; - signal rst_pc_ctr : std_logic; - signal pc_ctr : std_logic_vector(5 downto 0); - signal next_pc_match : std_logic; - signal pc_match : std_logic; - - signal rst_tc_sm : std_logic; - signal inc_tc_sm : std_logic; - signal tc_ctr : std_logic_vector(3 downto 0); - signal next_sync_timeout : std_logic; - signal sync_timeout : std_logic; - - signal rst_lc_sm : std_logic; - signal inc_lc_sm : std_logic; - signal lc_ctr : std_logic_vector(3 downto 0); - signal next_sync_success : std_logic; - signal sync_success : std_logic; - - signal delay_store : std_logic_vector(7 downto 0); - signal store_header : std_logic; - - signal apv_channel : std_logic_vector(6 downto 0); - signal ce_chnl_ctr : std_logic; - signal frame_analog : std_logic; - signal set_frame_analog : std_logic; - signal rst_frame_analog : std_logic; - signal next_apv_last : std_logic; - signal apv_last : std_logic; - signal apv_start : std_logic; - - signal adc_raw_one : std_logic_vector(11 downto 0); - signal adc_raw_two : std_logic_vector(11 downto 0); - - signal bit_high : std_logic; - signal bit_low : std_logic; - signal apv_overflow : std_logic; - signal apv_underflow : std_logic; - - signal next_ce_underflow : std_logic; - signal next_ce_overflow : std_logic; - - signal sum_ovf : std_logic_vector(7 downto 0); - signal sum_udf : std_logic_vector(7 downto 0); - - signal frame_ctr : std_logic_vector(3 downto 0); - signal comb_ce_frame_ctr : std_logic; - - signal debug : std_logic_vector(15 downto 0); - - signal apv_on : std_logic; -- 40MHz clock domain register - +-- normal signals +signal lock_bsm : std_logic_vector(7 downto 0); +signal tickmark_found : std_logic; +signal header_found : std_logic; +signal flatline_found : std_logic; +signal status_unknown : std_logic; +signal status_badadc : std_logic; +signal status_locked : std_logic; +signal status_lost : std_logic; +signal status_nosync : std_logic; +signal status_missing : std_logic; +signal next_status_ignore : std_logic; +signal status_ignore : std_logic; +signal frame_flat : std_logic; +signal next_frame_ovf : std_logic; +signal frame_ovf : std_logic; +signal next_frame_udf : std_logic; +signal frame_udf : std_logic; +signal frame_row : std_logic_vector(7 downto 0); +signal frame_error : std_logic; +signal bit_data : std_logic_vector(11 downto 0); +signal bit_valid : std_logic_vector(11 downto 0); + +signal rst_pc_sm : std_logic; +signal rst_pc_ctr : std_logic; +signal pc_ctr : std_logic_vector(5 downto 0); +signal next_pc_match : std_logic; +signal pc_match : std_logic; + +signal rst_tc_sm : std_logic; +signal inc_tc_sm : std_logic; +signal tc_ctr : std_logic_vector(3 downto 0); +signal next_sync_timeout : std_logic; +signal sync_timeout : std_logic; + +signal rst_lc_sm : std_logic; +signal inc_lc_sm : std_logic; +signal lc_ctr : std_logic_vector(3 downto 0); +signal next_sync_success : std_logic; +signal sync_success : std_logic; + +signal delay_store : std_logic_vector(7 downto 0); +signal store_header : std_logic; + +signal apv_channel : std_logic_vector(6 downto 0); +signal ce_chnl_ctr : std_logic; +signal frame_analog : std_logic; +signal set_frame_analog : std_logic; +signal rst_frame_analog : std_logic; +signal next_apv_last : std_logic; +signal apv_last : std_logic; +signal apv_start : std_logic; + +signal adc_raw_one : std_logic_vector(11 downto 0); +signal adc_raw_two : std_logic_vector(11 downto 0); + +signal bit_high : std_logic; +signal bit_low : std_logic; +signal apv_overflow : std_logic; +signal apv_underflow : std_logic; + +signal next_ce_underflow : std_logic; +signal next_ce_overflow : std_logic; + +signal sum_ovf : std_logic_vector(7 downto 0); +signal sum_udf : std_logic_vector(7 downto 0); + +signal frame_ctr : std_logic_vector(3 downto 0); +signal comb_ce_frame_ctr : std_logic; + +signal debug : std_logic_vector(15 downto 0); + +signal apv_on : std_logic; -- 40MHz clock domain register + begin -- Debug signals @@ -135,30 +136,32 @@ debug <= (others => '0'); -- Clock domain crossing THE_APVON_SYNCER: state_sync -port map( STATE_A_IN => apv_on_in, - CLK_B_IN => clk_apv_in, - RESET_B_IN => reset_in, - STATE_B_OUT => apv_on - ); +port map( + STATE_A_IN => apv_on_in, + CLK_B_IN => clk_apv_in, + RESET_B_IN => reset_in, + STATE_B_OUT => apv_on +); -- Input stage, for tickmark and header recognition, and bit decoding. -- Also detects missing APVs by flatline. THE_APV_DIGITAL: apv_digital -port map( CLK_APV_IN => clk_apv_in, - RESET_IN => reset_in, - ADC_RAW_IN => adc_raw_in, - BIT_LOW_IN => bit_low_in, - BIT_HIGH_IN => bit_high_in, - FL_LOW_IN => fl_low_in, - FL_HIGH_IN => fl_high_in, - BIT_DATA_OUT => bit_data, - BIT_VALID_OUT => bit_valid, -- for testing! - BIT_HIGH_OUT => bit_high, -- for analog off recognition, one cycle earlier - BIT_LOW_OUT => bit_low, -- for analog off recognition, one cycle earlier - TICKMARK_OUT => tickmark_found, - HEADER_OUT => header_found, - FLAT_LINE_OUT => flatline_found - ); +port map( + CLK_APV_IN => clk_apv_in, + RESET_IN => reset_in, + ADC_RAW_IN => adc_raw_in, + BIT_LOW_IN => bit_low_in, + BIT_HIGH_IN => bit_high_in, + FL_LOW_IN => fl_low_in, + FL_HIGH_IN => fl_high_in, + BIT_DATA_OUT => bit_data, + BIT_VALID_OUT => bit_valid, -- for testing! + BIT_HIGH_OUT => bit_high, -- for analog off recognition, one cycle earlier + BIT_LOW_OUT => bit_low, -- for analog off recognition, one cycle earlier + TICKMARK_OUT => tickmark_found, + HEADER_OUT => header_found, + FLAT_LINE_OUT => flatline_found +); -- Count enables for the underflow / overflow counters next_ce_underflow <= '1' when (bit_high = '0' and bit_low = '1' and frame_analog = '1') else '0'; @@ -166,12 +169,12 @@ next_ce_overflow <= '1' when (bit_high = '1' and bit_low = '0' and frame_analog -- Counter for underflow channels THE_UNDERFLOW_CTR_PROC: process( clk_apv_in ) -begin +begin if( rising_edge(clk_apv_in) ) then if( (reset_in = '1') or (delay_store(1) = '1') ) then sum_udf <= (others => '0'); elsif( next_ce_underflow = '1' ) then - sum_udf <= sum_udf + 1; + sum_udf <= sum_udf + 1; end if; end if; end process THE_UNDERFLOW_CTR_PROC; @@ -183,12 +186,12 @@ frame_flat <= sum_udf(7); -- Counter for Overflow channels THE_OVERFLOW_CTR_PROC: process( clk_apv_in ) -begin +begin if( rising_edge(clk_apv_in) ) then if( (reset_in = '1') or (delay_store(1) = '1') ) then sum_ovf <= (others => '0'); elsif( next_ce_overflow = '1' ) then - sum_ovf <= sum_ovf + 1; + sum_ovf <= sum_ovf + 1; end if; end if; end process THE_OVERFLOW_CTR_PROC; @@ -209,30 +212,31 @@ end process THE_SYNC_PROC; -- locking state machine THE_APV_LOCK_SM: apv_lock_sm -port map( CLK_APV_IN => clk_apv_in, - RESET_IN => reset_in, - SYNC_IN => sync_in, -- 40 MHz signal! - ADC_VALID_IN => adc_valid_in, - TIMED_IN => sync_timeout, - MATCH_IN => pc_match, - LOCKED_IN => sync_success, - TICK_IN => tickmark_found, - HEADER_IN => header_found, - FLATLINE_IN => flatline_found, - RST_PC_OUT => rst_pc_sm, - RST_TC_OUT => rst_tc_sm, - INC_TC_OUT => inc_tc_sm, - RST_LC_OUT => rst_lc_sm, - INC_LC_OUT => inc_lc_sm, - UNKNOWN_OUT => status_unknown, - BADADC_OUT => status_badadc, - LOCKED_OUT => status_locked, - LOST_OUT => status_lost, - NOSYNC_OUT => status_nosync, - NOAPV_OUT => status_missing, - BSM_OUT => lock_bsm, - DEBUG_OUT => open - ); +port map( + CLK_APV_IN => clk_apv_in, + RESET_IN => reset_in, + SYNC_IN => sync_in, -- 40 MHz signal! + ADC_VALID_IN => adc_valid_in, + TIMED_IN => sync_timeout, + MATCH_IN => pc_match, + LOCKED_IN => sync_success, + TICK_IN => tickmark_found, + HEADER_IN => header_found, + FLATLINE_IN => flatline_found, + RST_PC_OUT => rst_pc_sm, + RST_TC_OUT => rst_tc_sm, + INC_TC_OUT => inc_tc_sm, + RST_LC_OUT => rst_lc_sm, + INC_LC_OUT => inc_lc_sm, + UNKNOWN_OUT => status_unknown, + BADADC_OUT => status_badadc, + LOCKED_OUT => status_locked, + LOST_OUT => status_lost, + NOSYNC_OUT => status_nosync, + NOAPV_OUT => status_missing, + BSM_OUT => lock_bsm, + DEBUG_OUT => open +); next_status_ignore <= not apv_on; @@ -252,7 +256,7 @@ begin pc_ctr <= pc_ctr + 1; pc_match <= next_pc_match; rst_pc_ctr <= pc_match; - end if; + end if; end if; end process THE_PERIOD_COUNTER; @@ -273,7 +277,7 @@ begin end if; end process THE_TIMEOUT_COUNTER; --- watermark for the successful synchronisation +-- watermark for the successful synchronisation next_sync_success <= '1' when ( lc_ctr = x"8" ) else '0'; -- lock counter for the lock process @@ -298,7 +302,7 @@ begin delay_store <= (others => '0'); else delay_store(7 downto 1) <= delay_store(6 downto 0); - -- we only accept data frames when they arrive at a well defined tickmark place, + -- we only accept data frames when they arrive at a well defined tickmark place, -- when the APV is really switched on, and it is in locked state. delay_store(0) <= header_found and pc_match and apv_on and status_locked; end if; @@ -373,7 +377,7 @@ begin if( rising_edge(clk_apv_in) ) then if ( reset_in = '1' ) then frame_error <= '0'; -- bit is inverted! - frame_row <= (others => '0'); + frame_row <= (others => '0'); elsif( store_header = '1' ) then frame_error <= not bit_data(0); -- bit is inverted! frame_row <= bit_data(8 downto 1); @@ -418,7 +422,7 @@ apv_raw_out <= adc_raw_two; apv_overflow_out <= apv_overflow; apv_underflow_out <= apv_underflow; apv_analog_out <= ce_chnl_ctr; -apv_start_out <= apv_start; +apv_start_out <= apv_start; apv_last_out <= apv_last; frame_flat_out <= frame_flat; diff --git a/src/apv_pc_nc_alu.vhd b/src/apv_pc_nc_alu.vhd index 04668c7..723e82f 100644 --- a/src/apv_pc_nc_alu.vhd +++ b/src/apv_pc_nc_alu.vhd @@ -14,31 +14,33 @@ use work.adcmv3_components.all; -- Data is piped out directly. entity apv_pc_nc_alu is - port( CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; - START_IN : in std_logic; -- start signal, used for initialisation of counters - MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested - CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number - LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG - EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG - BUF_GOOD_IN : in std_logic; -- process buffer - BUF_BAD_IN : in std_logic; -- write only error header - BUF_IGNORE_IN : in std_logic; -- do not write anything - ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers - DO_HEADER_IN : in std_logic; - DO_ERROR_IN : in std_logic; - EVT_TYPE_IN : in std_logic_vector(2 downto 0); - RAW_ADDR_IN : in std_logic_vector(6 downto 0); - RAW_DATA_IN : in std_logic_vector(37 downto 0); - PED_DATA_IN : in std_logic_vector(17 downto 0); - THR_DATA_IN : in std_logic_vector(17 downto 0); - FRAME_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0] - WE_OUT : out std_logic; - COUNT_OUT : out std_logic_vector(9 downto 0); - ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout - DBG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + START_IN : in std_logic; -- start signal, used for initialisation of counters + MAX_FRAMES_IN : in std_logic_vector(3 downto 0); -- number of frames requested + CURR_FRAME_IN : in std_logic_vector(3 downto 0); -- current frame number + LOC_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG + EDS_FRM_CTR_IN : in std_logic_vector(3 downto 0); -- DEBUG + BUF_GOOD_IN : in std_logic; -- process buffer + BUF_BAD_IN : in std_logic; -- write only error header + BUF_IGNORE_IN : in std_logic; -- do not write anything + ERROR_IN : in std_logic_vector(3 downto 0); -- buffer status, errors from checkers + DO_HEADER_IN : in std_logic; + DO_ERROR_IN : in std_logic; + SUPPRESS_IN : in std_logic; -- suppress bit + EVT_TYPE_IN : in std_logic_vector(2 downto 0); -- RICH data configuration bits + RAW_ADDR_IN : in std_logic_vector(6 downto 0); + RAW_DATA_IN : in std_logic_vector(37 downto 0); + PED_DATA_IN : in std_logic_vector(17 downto 0); + THR_DATA_IN : in std_logic_vector(17 downto 0); + FRAME_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(26 downto 0); -- [21] -> [31], [20:0] -> [20:0] + WE_OUT : out std_logic; + COUNT_OUT : out std_logic_vector(9 downto 0); + ANYDATA_OUT : out std_logic; -- this FIFO needs attention during readout + DBG_OUT : out std_logic_vector(15 downto 0) +); end; ---------------------------------------------------------------------- @@ -48,49 +50,50 @@ end; architecture behavioral of apv_pc_nc_alu is - -- normal signals - signal raw_data_q : std_logic_vector(12 downto 0); -- input register - signal ped_data_q : std_logic_vector(12 downto 0); -- input register - signal ped_corr_data_q : std_logic_vector(12 downto 0); -- registered pedestal corrected value - signal ped_corr_data_qq : std_logic_vector(12 downto 0); -- registered pedestal corrected value - signal ped_corr_data_qqq : std_logic_vector(12 downto 0); -- registered pedestal corrected value - signal loc_baseline_q : std_logic_vector(13 downto 0); - signal nc_corr_data_q : std_logic_vector(13 downto 0); - signal nc_corr_data_qq : std_logic_vector(13 downto 0); - signal nc_corr_data_qqq : std_logic_vector(21 downto 0); - signal thr_data_q : std_logic_vector(13 downto 0); - signal udf_int : std_logic_vector(6 downto 0); - signal ovf_int : std_logic_vector(6 downto 0); - signal frame_int : std_logic_vector(6 downto 0); - signal off_int : std_logic_vector(6 downto 0); - signal next_data_we : std_logic; - signal data_we : std_logic; - - signal thr_pass : std_logic; - - -- data steering signals - signal next_ped_off : std_logic; - signal ped_off : std_logic; -- switch off pedestals - signal next_lcb_off : std_logic; - signal lcb_off : std_logic; -- switch off local baseline correction - signal next_clip_max : std_logic; - signal clip_max : std_logic; -- clip OVF values to maximum - signal next_clip_min : std_logic; - signal clip_min : std_logic; -- clip UDF values to minimum - signal next_bad_corr : std_logic_vector(6 downto 2); - signal bad_corr : std_logic_vector(6 downto 2); - signal toggle : std_logic_vector(6 downto 0); - - -- Channel counter - signal channel : std_logic_vector(6 downto 0); - - signal count : std_logic_vector(9 downto 0); - - signal anydata : std_logic; - - -- Debug signals - signal debug : std_logic_vector(15 downto 0); - +-- normal signals +signal raw_data_q : std_logic_vector(12 downto 0); -- input register +signal ped_data_q : std_logic_vector(12 downto 0); -- input register +signal ped_corr_data_q : std_logic_vector(12 downto 0); -- registered pedestal corrected value +signal ped_corr_data_qq : std_logic_vector(12 downto 0); -- registered pedestal corrected value +signal ped_corr_data_qqq : std_logic_vector(12 downto 0); -- registered pedestal corrected value +signal loc_baseline_q : std_logic_vector(13 downto 0); +signal nc_corr_data_q : std_logic_vector(13 downto 0); +signal nc_corr_data_qq : std_logic_vector(13 downto 0); +signal nc_corr_data_qqq : std_logic_vector(21 downto 0); +signal thr_data_q : std_logic_vector(13 downto 0); +signal udf_int : std_logic_vector(6 downto 0); +signal ovf_int : std_logic_vector(6 downto 0); +signal frame_int : std_logic_vector(6 downto 0); +signal off_int : std_logic_vector(6 downto 0); +signal next_data_we : std_logic; +signal data_we : std_logic; +signal adjust_data : std_logic_vector(13 downto 0); + +signal thr_pass : std_logic; + +-- data steering signals +signal next_ped_off : std_logic; +signal ped_off : std_logic; -- switch off pedestals +signal next_lcb_off : std_logic; +signal lcb_off : std_logic; -- switch off local baseline correction +signal next_clip_max : std_logic; +signal clip_max : std_logic; -- clip OVF values to maximum +signal next_clip_min : std_logic; +signal clip_min : std_logic; -- clip UDF values to minimum +signal next_bad_corr : std_logic_vector(6 downto 2); +signal bad_corr : std_logic_vector(6 downto 2); +signal toggle : std_logic_vector(6 downto 0); + +-- Channel counter +signal channel : std_logic_vector(6 downto 0); + +signal count : std_logic_vector(9 downto 0); + +signal anydata : std_logic; + +-- Debug signals +signal debug : std_logic_vector(15 downto 0); + begin --------------------------------------------------------------------------------- @@ -100,42 +103,46 @@ begin -- 000 RAW128 128 raw data (+ 4096 + 8192) -- 001 PED128 128 pedestal data (+ 4096 - pedestal) -- 010 PED128THR <=128 pedestal data above threshold --- 011 --- --- --- +-- 011 RAW64 64 raw data -- 100 NC64PED64 128 do NC on physic channels, corr. channels pedestal corrected -- 101 NC64 64 only NC physic channels -- 110 NC64GOOD <=64 only good NC channels -- 111 NC64THR <=64 only good NC channels above threshold --------------------------------------------------------------------------------- --- Switch off pedestals (RAW128 mode) -next_ped_off <= '1' when ( evt_type_in = "000" ) else '0'; +-- Switch off pedestals (RAW128 and RAW64 mode) +next_ped_off <= '1' when ( (evt_type_in = b"000") or (evt_type_in = b"011") ) else '0'; --- Switch off local baseline (RAW128, PED128, PED128THR modes) -next_lcb_off <= '1' when ( (evt_type_in = "000") or (evt_type_in = "001") or (evt_type_in = "010") ) else '0'; +-- Switch off local baseline (RAW128, PED128, PED128THR, RAW64 modes) +next_lcb_off <= '1' when ( (evt_type_in = b"000") or (evt_type_in = b"001") or (evt_type_in = b"010") or (evt_type_in = b"011") ) + else '0'; --- Clipping function for neighbour corrected values (all modes except RAW128) -next_clip_min <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or (evt_type_in = "011") or - (evt_type_in(2) = '1') ) and (udf_int(2) = '1') ) +-- Clipping function for neighbour corrected values (all modes except RAW128 and RAW64) +next_clip_min <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or + (evt_type_in(2) = '1') ) and (udf_int(2) = '1') ) else '0'; -next_clip_max <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or (evt_type_in = "011") or - (evt_type_in(2) = '1') ) and (ovf_int(2) = '1') ) +next_clip_max <= '1' when ( ((evt_type_in = "001") or (evt_type_in = "010") or + (evt_type_in(2) = '1') ) and (ovf_int(2) = '1') ) else '0'; -- Neighbour correction: handle broken or switched off correction channels. -- A broken (UDF/OVF) or switched off (OFF) correction channel kills its two physical neighbour channels. next_bad_corr(2) <= '1' when ( (udf_int(0) = '1') or (udf_int(2) = '1') or - (ovf_int(0) = '1') or (ovf_int(2) = '1') or - (off_int(0) = '1') or (off_int(2) = '1') ) - else '0'; + (ovf_int(0) = '1') or (ovf_int(2) = '1') or + (off_int(0) = '1') or (off_int(2) = '1') ) + else '0'; next_bad_corr(3) <= '1' when ( (bad_corr(2) = '1') and (evt_type_in(2) = '1') ) else '0'; -next_bad_corr(4) <= '1' when ( ((bad_corr(3) = '1') and (toggle(3) = '1') and (frame_int(3) = '1')) or - (off_int(3) = '1') ) - else '0'; +next_bad_corr(4) <= '1' when ( ((bad_corr(3) = '1') and (toggle(3) = '1') and (frame_int(3) = '1')) or + (off_int(3) = '1') ) + else '0'; next_bad_corr(5) <= bad_corr(4); next_bad_corr(6) <= bad_corr(5); +-- baseline shifting for raw modes (4096) +adjust_data <= b"01_0000_0000_0000" when evt_type_in(2) = '0' else b"00_0000_0000_0000"; + -- We carry the OVF/UDF/OFF information all through the chain! THE_SYNC_PROC: process( clk_in ) begin @@ -158,7 +165,7 @@ end process THE_SYNC_PROC; THE_RAW_INPUT_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then - raw_data_q <= '1' & raw_data_in(11 downto 0); + raw_data_q <= '1' & raw_data_in(11 downto 0); end if; end process THE_RAW_INPUT_PROC; @@ -169,7 +176,7 @@ begin if( (reset_in = '1') or (ped_off = '1') ) then ped_data_q <= (others => '0'); else - ped_data_q <= '0' & ped_data_in(11 downto 0); + ped_data_q <= '0' & ped_data_in(11 downto 0); end if; end if; end process THE_PED_INPUT_PROC; @@ -196,7 +203,7 @@ THE_MEAN_CALC_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then if( (reset_in = '1') or (lcb_off = '1') ) then - loc_baseline_q <= (others => '0'); + loc_baseline_q <= (others => '0'); else loc_baseline_q <= ('0' & ped_corr_data_q) + ('0' & ped_corr_data_qqq); end if; @@ -212,24 +219,34 @@ begin elsif( clip_max = '1' ) then nc_corr_data_q <= (others => '1'); -- channel is overflow else - nc_corr_data_q <= ('1' & ped_corr_data_qqq) - ('0' & loc_baseline_q(13 downto 1)); + nc_corr_data_q <= ('1' & ped_corr_data_qqq) - ('0' & loc_baseline_q(13 downto 1)); end if; end if; end process THE_NC_CORR_PROC; -- One caveat: in PED128 our artificial baseline is 4096, in NC64THR it is 8192. -thr_data_q(13) <= '1'; --'1' when (evt_type_in = "111") else '0'; +thr_data_q(13) <= '1'; thr_data_q(12) <= '0' when (evt_type_in = "111") else '1'; -- Threshold comparison THE_THR_COMP: comp14bit -port map( DATAA => nc_corr_data_q, - DATAB => thr_data_q, - CLOCK => clk_in, - CLOCKEN => '1', - ACLR => reset_in, -- BUG 10092009 - AGEB => thr_pass - ); +port map( + DATAA => nc_corr_data_q, + DATAB => thr_data_q, + CLOCK => clk_in, + CLOCKEN => '1', + ACLR => reset_in, + AGEB => thr_pass +); + +-- in raw modes, we must shift back to "normal" nominal baseline +THE_ADJUSTMENT_PROC: process( clk_in ) +begin + if( rising_edge(clk_in) ) then + nc_corr_data_qq <= nc_corr_data_q - adjust_data; + end if; +end process THE_ADJUSTMENT_PROC; + -- Delay NCD by one cycle, store THR data THE_NC_DELAY_PROC: process( clk_in ) @@ -237,21 +254,21 @@ begin if( rising_edge(clk_in) ) then if( reset_in = '1' ) then nc_corr_data_qqq <= (others => '0'); - nc_corr_data_qq <= (others => '0'); +-- nc_corr_data_qq <= (others => '0'); thr_data_q(11 downto 0) <= (others => '0'); else if ( (do_header_in = '0') and (do_error_in = '0') ) then nc_corr_data_qqq(21) <= '0'; -- DATA nc_corr_data_qqq(20 downto 14) <= channel; nc_corr_data_qqq(13 downto 0) <= nc_corr_data_qq; - elsif( (do_header_in = '1') ) then + elsif( (do_header_in = '1') ) then nc_corr_data_qqq(21) <= '1'; -- HEADER nc_corr_data_qqq(20) <= buf_bad_in; nc_corr_data_qqq(19 downto 16) <= error_in; nc_corr_data_qqq(15 downto 12) <= max_frames_in; nc_corr_data_qqq(11 downto 8) <= curr_frame_in; nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18); - elsif( (do_error_in = '1') ) then + elsif( (do_error_in = '1') ) then nc_corr_data_qqq(21) <= '1'; -- HEADER nc_corr_data_qqq(20) <= raw_data_in(26); -- error nc_corr_data_qqq(19 downto 16) <= eds_frm_ctr_in; -- EDS start frame @@ -259,25 +276,26 @@ begin nc_corr_data_qqq(11 downto 8) <= raw_data_in(17 downto 14); -- frame counter nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18); -- row end if; - nc_corr_data_qq <= nc_corr_data_q; +-- nc_corr_data_qq <= nc_corr_data_q; thr_data_q(11 downto 0) <= thr_data_in(11 downto 0); end if; end if; end process THE_NC_DELAY_PROC; -- Judgement day: will data survive? -next_data_we <= '1' when ( ((buf_good_in = '1') and (evt_type_in = "000") and (frame_int(5) = '1')) or - ((buf_good_in = '1') and (evt_type_in = "001") and (frame_int(5) = '1')) or - ((buf_good_in = '1') and (evt_type_in = "010") and (frame_int(5) = '1') and (thr_pass = '1') and (bad_corr(5) = '0')) or - ((buf_good_in = '1') and (evt_type_in = "100") and (frame_int(5) = '1')) or - ((buf_good_in = '1') and (evt_type_in = "101") and (frame_int(5) = '1') and (toggle(5) = '1')) or - ((buf_good_in = '1') and (evt_type_in = "110") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0')) or - ((buf_good_in = '1') and (evt_type_in = "111") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0') and (thr_pass = '1')) or - (((buf_good_in = '1') or (buf_bad_in = '1')) and (do_header_in = '1')) or --- ((buf_bad_in = '1') and (do_error_in = '1')) - ((do_error_in = '1')) - ) - else '0'; +next_data_we <= '1' when ( + ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "000") and (frame_int(5) = '1')) or + ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "001") and (frame_int(5) = '1')) or + ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "010") and (frame_int(5) = '1') and (thr_pass = '1') and (bad_corr(5) = '0')) or + ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "011") and (frame_int(5) = '1') and (toggle(5) = '1')) or + ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "100") and (frame_int(5) = '1')) or + ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "101") and (frame_int(5) = '1') and (toggle(5) = '1')) or + ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "110") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0')) or + ((suppress_in = '0') and (buf_good_in = '1') and (evt_type_in = "111") and (frame_int(5) = '1') and (toggle(5) = '1') and (bad_corr(5) = '0') and (thr_pass = '1')) or + (((buf_good_in = '1') or (buf_bad_in = '1')) and (do_header_in = '1')) or +-- ((buf_bad_in = '1') and (do_error_in = '1')) + ((do_error_in = '1')) +) else '0'; -- Channel counter for outgoing data THE_CHANNEL_CTR_PROC: process( clk_in ) @@ -291,7 +309,10 @@ begin end if; end process THE_CHANNEL_CTR_PROC; --- Channel counter for outgoing data +-- Data word counter, including all words written (i.e. also headers and debug words) +-- +-- NB: we have 10 bits for COUNT. So we can use up to 1023 data words per event, including +-- all debug words. THE_DATA_CTR_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then @@ -300,6 +321,7 @@ begin anydata <= '0'; elsif( (data_we = '1') and (anydata = '0') ) then anydata <= '1'; + count <= count + 1; -- changed elsif( (data_we = '1') and (anydata = '1') ) then count <= count + 1; end if; @@ -307,7 +329,7 @@ begin end process THE_DATA_CTR_PROC; -- output signals (most of them are only needed for simulation!) -we_out <= data_we; +we_out <= data_we; count_out <= count; anydata_out <= anydata; @@ -321,7 +343,7 @@ fifo_data_out(25) <= data_we; fifo_data_out(24) <= bad_corr(6); fifo_data_out(23) <= ovf_int(6); fifo_data_out(22) <= udf_int(6); -fifo_data_out(21 downto 0) <= nc_corr_data_qqq; +fifo_data_out(21 downto 0) <= nc_corr_data_qqq; -- Debug signals --debug(31 downto 16) <= (others => '0'); @@ -331,30 +353,4 @@ debug(13 downto 0) <= thr_data_q; dbg_out <= debug; -end behavioral; - ---THE_NC_DELAY_PROC: process( clk_in ) ---begin --- if( rising_edge(clk_in) ) then --- if( reset_in = '1' ) then --- nc_corr_data_qqq <= (others => '0'); --- nc_corr_data_qq <= (others => '0'); --- thr_data_q(11 downto 0) <= (others => '0'); --- else --- if( (do_header_in = '0') and (do_error_in = '0') ) then --- nc_corr_data_qqq(21) <= '0'; -- DATA --- nc_corr_data_qqq(20 downto 14) <= channel; --- nc_corr_data_qqq(13 downto 0) <= nc_corr_data_qq; --- else --- nc_corr_data_qqq(21) <= '1'; -- HEADER --- nc_corr_data_qqq(20) <= buf_bad_in; --- nc_corr_data_qqq(19 downto 16) <= error_in; --- nc_corr_data_qqq(15 downto 12) <= max_frames_in; --- nc_corr_data_qqq(11 downto 8) <= curr_frame_in; --- nc_corr_data_qqq(7 downto 0) <= raw_data_in(25 downto 18); --- end if; --- nc_corr_data_qq <= nc_corr_data_q; --- thr_data_q(11 downto 0) <= thr_data_in(11 downto 0); --- end if; --- end if; ---end process THE_NC_DELAY_PROC; +end behavioral; \ No newline at end of file diff --git a/src/apv_raw_buffer.vhd b/src/apv_raw_buffer.vhd index 47d3f24..b76d4ec 100755 --- a/src/apv_raw_buffer.vhd +++ b/src/apv_raw_buffer.vhd @@ -6,7 +6,7 @@ use ieee.std_logic_unsigned.all; library work; use work.adcmv3_components.all; --- This entity is used to decouple the ADC/APV part (with 40MHz) from the data +-- This entity is used to decouple the ADC/APV part (with 40MHz) from the data -- handling part (which runs with 100MHz). -- Signals: -- - all signals starting with ADC_* are synchronous to CLK_APV_IN @@ -16,110 +16,111 @@ use work.adcmv3_components.all; -- - take care of the one clock delay between BUF_ADDR_IN and BUF_DATA_OUT. entity apv_raw_buffer is - port( CLK_APV_IN : in std_logic; -- write clock from APV handling stage - RESET_IN : in std_logic; - -- buffer level control signals - FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV - MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event - -- CLK_APV_IN sync'ed signals from APV_LOCKER - ADC_ANALOG_IN : in std_logic; -- write enable for ADC data - ADC_START_IN : in std_logic; -- data frame detected, block the buffer page - ADC_LAST_IN : in std_logic; -- last channel signal - ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID - ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR - ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV - ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame - -- BUF_CLK_IN sync'ed signals from back side logic - BUF_CLK_IN : in std_logic; -- read clock - BUF_RESET_IN : in std_logic; -- 100MHz reset - BUF_START_OUT : out std_logic; -- one block starts writing (aka ADC_START) - BUF_READY_OUT : out std_logic; -- one block has been written (aka ADC_LAST) - BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer - BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer) - BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer - BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output - BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output - BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation - BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation - BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off - BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer - BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler+ - BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set! - -- Debug signals - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_APV_IN : in std_logic; -- write clock from APV handling stage + RESET_IN : in std_logic; + -- buffer level control signals + FRM_REQD_IN : in std_logic; -- one data frame has been requested from APV + MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers per event + -- CLK_APV_IN sync'ed signals from APV_LOCKER + ADC_ANALOG_IN : in std_logic; -- write enable for ADC data + ADC_START_IN : in std_logic; -- data frame detected, block the buffer page + ADC_LAST_IN : in std_logic; -- last channel signal + ADC_CHANNEL_IN : in std_logic_vector(6 downto 0); -- physical channel ID + ADC_RAW_IN : in std_logic_vector(17 downto 0); -- raw ADC data, UDF, OVF, ERROR + ADC_STATUS_IN : in std_logic_vector(7 downto 0); -- status information for APV + ADC_FRAME_IN : in std_logic_vector(11 downto 0); -- status information for frame + -- BUF_CLK_IN sync'ed signals from back side logic + BUF_CLK_IN : in std_logic; -- read clock + BUF_RESET_IN : in std_logic; -- 100MHz reset + BUF_START_OUT : out std_logic; -- one block starts writing (aka ADC_START) + BUF_READY_OUT : out std_logic; -- one block has been written (aka ADC_LAST) + BUF_ADDR_IN : in std_logic_vector(6 downto 0); -- address inside current buffer + BUF_DONE_IN : in std_logic; -- buffer has been read (discard buffer) + BUF_DATA_OUT : out std_logic_vector(17 downto 0); -- data from buffer + BUF_STATUS_OUT : out std_logic_vector(7 downto 0); -- generic APV status output + BUF_FRAME_OUT : out std_logic_vector(11 downto 0); -- current frame status output + BUF_GOOD_OUT : out std_logic; -- APV is active and synced -> GOOD situation + BUF_BROKEN_OUT : out std_logic; -- APV is active, but not synced -> BAD situation + BUF_IGNORE_OUT : out std_logic; -- APV is switched off -> switched off + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); -- number of stored frames inside buffer + BUF_TICKMARK_OUT : out std_logic; -- tickmark signal for timeouts in the EDS handler+ + BUF_FULL_OUT : out std_logic; -- inhibit any next trigger if set! + -- Debug signals + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of apv_raw_buffer is - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of behavioral : architecture is "APV_RAW_BUF_group"; - - -- normal signals - signal adc_status_q : std_logic_vector(7 downto 0); - signal adc_status_qq : std_logic_vector(7 downto 0); - - signal adc_start_x : std_logic; - signal adc_start : std_logic; - signal adc_last_x : std_logic; - signal adc_last : std_logic; - - signal ce_wr_pointer : std_logic; - signal wr_pointer : std_logic_vector(3 downto 0); - signal ce_rd_pointer : std_logic; - signal rd_pointer : std_logic_vector(3 downto 0); - - signal buf_good_x : std_logic; - signal buf_good : std_logic; - signal buf_broken_x : std_logic; - signal buf_broken : std_logic; - signal buf_ignore_x : std_logic; - signal buf_ignore : std_logic; - - signal buf_level : std_logic_vector(4 downto 0); - signal buf_level_up_x : std_logic; - signal buf_level_down_x : std_logic; - - signal wr_data_addr : std_logic_vector(10 downto 0); - signal wr_data_d : std_logic_vector(17 downto 0); - signal wr_data_ena : std_logic; - signal rd_data_addr : std_logic_vector(10 downto 0); - signal rd_data_d : std_logic_vector(17 downto 0); - signal rd_data_ena : std_logic; - - signal buf_frame : std_logic_vector(11 downto 0); - - signal adc_tickmark : std_logic; - signal buf_tickmark : std_logic; - - -- Alias names for status bits - signal apv_on_x : std_logic; -- 40MHz clock domain signal - signal apv_on : std_logic; - signal apv_adcok_x : std_logic; -- 40MHz clock domain signal - signal apv_adcok : std_logic; - signal apv_locked_x : std_logic; -- 40MHz clock domain signal - signal apv_locked : std_logic; - - -- from old APV_BUFHANDLER block - signal apv_free_ctr : std_logic_vector(4 downto 0); - signal apv_free_up : std_logic; - signal apv_free_down : std_logic; - signal buf_free_ctr : std_logic_vector(4 downto 0); - signal buf_free_up : std_logic; - signal buf_free_down : std_logic; - - signal sum_apv_buf : std_logic_vector(5 downto 0); - signal sum_apv : std_logic_vector(5 downto 0); - signal sum_buf : std_logic_vector(5 downto 0); - signal trg_limit : std_logic_vector(5 downto 0); - - signal debug : std_logic_vector(15 downto 0); - - signal apv_or_buf_full_x : std_logic; - signal apv_or_buf_full : std_logic; - +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of behavioral : architecture is "APV_RAW_BUF_group"; + +-- normal signals +signal adc_status_q : std_logic_vector(7 downto 0); +signal adc_status_qq : std_logic_vector(7 downto 0); + +signal adc_start_x : std_logic; +signal adc_start : std_logic; +signal adc_last_x : std_logic; +signal adc_last : std_logic; + +signal ce_wr_pointer : std_logic; +signal wr_pointer : std_logic_vector(3 downto 0); +signal ce_rd_pointer : std_logic; +signal rd_pointer : std_logic_vector(3 downto 0); + +signal buf_good_x : std_logic; +signal buf_good : std_logic; +signal buf_broken_x : std_logic; +signal buf_broken : std_logic; +signal buf_ignore_x : std_logic; +signal buf_ignore : std_logic; + +signal buf_level : std_logic_vector(4 downto 0); +signal buf_level_up_x : std_logic; +signal buf_level_down_x : std_logic; + +signal wr_data_addr : std_logic_vector(10 downto 0); +signal wr_data_d : std_logic_vector(17 downto 0); +signal wr_data_ena : std_logic; +signal rd_data_addr : std_logic_vector(10 downto 0); +signal rd_data_d : std_logic_vector(17 downto 0); +signal rd_data_ena : std_logic; + +signal buf_frame : std_logic_vector(11 downto 0); + +signal adc_tickmark : std_logic; +signal buf_tickmark : std_logic; + +-- Alias names for status bits +signal apv_on_x : std_logic; -- 40MHz clock domain signal +signal apv_on : std_logic; +signal apv_adcok_x : std_logic; -- 40MHz clock domain signal +signal apv_adcok : std_logic; +signal apv_locked_x : std_logic; -- 40MHz clock domain signal +signal apv_locked : std_logic; + +-- from old APV_BUFHANDLER block +signal apv_free_ctr : std_logic_vector(4 downto 0); +signal apv_free_up : std_logic; +signal apv_free_down : std_logic; +signal buf_free_ctr : std_logic_vector(4 downto 0); +signal buf_free_up : std_logic; +signal buf_free_down : std_logic; + +signal sum_apv_buf : std_logic_vector(5 downto 0); +signal sum_apv : std_logic_vector(5 downto 0); +signal sum_buf : std_logic_vector(5 downto 0); +signal trg_limit : std_logic_vector(5 downto 0); + +signal debug : std_logic_vector(15 downto 0); + +signal apv_or_buf_full_x : std_logic; +signal apv_or_buf_full : std_logic; + begin -- Debugging signals @@ -131,25 +132,28 @@ apv_locked_x <= adc_status_in(5); -- '0' = not locked, '1' = locked apv_on_x <= not adc_status_in(1); -- '0' = "off" means "ignore", '1' = "on" means "look at me" THE_APV_ON_SYNC: state_sync -port map( STATE_A_IN => apv_on_x, - CLK_B_IN => buf_clk_in, - RESET_B_IN => buf_reset_in, - STATE_B_OUT => apv_on - ); +port map( + STATE_A_IN => apv_on_x, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + STATE_B_OUT => apv_on +); THE_APV_LOCKED_SYNC: state_sync -port map( STATE_A_IN => apv_locked_x, - CLK_B_IN => buf_clk_in, - RESET_B_IN => buf_reset_in, - STATE_B_OUT => apv_locked - ); +port map( + STATE_A_IN => apv_locked_x, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + STATE_B_OUT => apv_locked +); THE_APV_ADCOK_SYNC: state_sync -port map( STATE_A_IN => apv_adcok_x, - CLK_B_IN => buf_clk_in, - RESET_B_IN => buf_reset_in, - STATE_B_OUT => apv_adcok - ); +port map( + STATE_A_IN => apv_adcok_x, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + STATE_B_OUT => apv_adcok +); -- We deliver three status signals to the data handler: -- BUF_GOOD_OUT : APV is switched on and alive, so data packets can be expected in case of triggers. @@ -162,10 +166,10 @@ port map( STATE_A_IN => apv_adcok_x, -- CLOCK DOMAINS! buf_good_x <= '1' when ((apv_on = '1') and (apv_adcok = '1') and (apv_locked = '1')) else '0'; -buf_broken_x <= '1' when ((apv_on = '1') and (apv_adcok = '0' or apv_locked = '0')) else '0'; +buf_broken_x <= '1' when ((apv_on = '1') and (apv_adcok = '0' or apv_locked = '0')) else '0'; buf_ignore_x <= '1' when ( apv_on = '0' ) else '0'; -THE_BUF_SYNCER_PROC: process( buf_clk_in ) +THE_BUF_SYNCER_PROC: process( buf_clk_in ) begin if( rising_edge(buf_clk_in) ) then buf_good <= buf_good_x; @@ -181,35 +185,38 @@ end process THE_BUF_SYNCER_PROC; adc_start_x <= (adc_start_in and buf_good_x); THE_ADC_START_SYNCER: pulse_sync -port map( CLK_A_IN => clk_apv_in, - RESET_A_IN => reset_in, - PULSE_A_IN => adc_start_x, - CLK_B_IN => buf_clk_in, - RESET_B_IN => buf_reset_in, - PULSE_B_OUT => adc_start - ); +port map( + CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_in, + PULSE_A_IN => adc_start_x, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + PULSE_B_OUT => adc_start +); adc_last_x <= (adc_last_in and buf_good_x); THE_ADC_LAST_SYNCER: pulse_sync -port map( CLK_A_IN => clk_apv_in, - RESET_A_IN => reset_in, - PULSE_A_IN => adc_last_x, - CLK_B_IN => buf_clk_in, - RESET_B_IN => buf_reset_in, - PULSE_B_OUT => adc_last - ); +port map( + CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_in, + PULSE_A_IN => adc_last_x, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + PULSE_B_OUT => adc_last +); -- The tickmark signal is also transfered from 40M to 100M clock domain adc_tickmark <= adc_status_in(0); -- alias THE_TICKMARK_SYNCER: pulse_sync -port map( CLK_A_IN => clk_apv_in, - RESET_A_IN => reset_in, - PULSE_A_IN => adc_tickmark, - CLK_B_IN => buf_clk_in, - RESET_B_IN => buf_reset_in, - PULSE_B_OUT => buf_tickmark - ); +port map( + CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_in, + PULSE_A_IN => adc_tickmark, + CLK_B_IN => buf_clk_in, + RESET_B_IN => buf_reset_in, + PULSE_B_OUT => buf_tickmark +); -- Control signals for the write pointer counter @@ -243,7 +250,7 @@ begin end process THE_RD_POINTER; -- We need a level counter for the EDS handler, anyhow -buf_level_up_x <= adc_last; +buf_level_up_x <= adc_last; buf_level_down_x <= (buf_done_in and buf_good); THE_BUF_LEVEL_COUNTER_PROC: process( buf_clk_in ) @@ -268,44 +275,46 @@ wr_data_d <= adc_raw_in; -- We have two EBRs to implement a 2kx18 ring buffer THE_INPUT_BRAM: input_bram -port map( WRADDRESS => wr_data_addr, - RDADDRESS => rd_data_addr, - DATA => wr_data_d, - WE => wr_data_ena, - RDCLOCK => buf_clk_in, - RDCLOCKEN => rd_data_ena, - RESET => reset_in, - WRCLOCK => clk_apv_in, - WRCLOCKEN => '1', - Q => rd_data_d - ); +port map( + WRADDRESS => wr_data_addr, + RDADDRESS => rd_data_addr, + DATA => wr_data_d, + WE => wr_data_ena, + RDCLOCK => buf_clk_in, + RDCLOCKEN => rd_data_ena, + RESET => reset_in, + WRCLOCK => clk_apv_in, + WRCLOCKEN => '1', + Q => rd_data_d +); -- We use a LUT based DPRAM for the 16x12b status memory THE_FRAME_STATUS_MEM: frame_status_mem -port map( WRADDRESS => wr_pointer, - DATA => adc_frame_in, - WRCLOCK => clk_apv_in, - WE => ce_wr_pointer, -- we store the frame status with the last ADC word - WRCLOCKEN => '1', - RDADDRESS => rd_pointer, - RDCLOCK => buf_clk_in, - RDCLOCKEN => '1', - RESET => reset_in, - Q => buf_frame - ); +port map( + WRADDRESS => wr_pointer, + DATA => adc_frame_in, + WRCLOCK => clk_apv_in, + WE => ce_wr_pointer, -- we store the frame status with the last ADC word + WRCLOCKEN => '1', + RDADDRESS => rd_pointer, + RDCLOCK => buf_clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + Q => buf_frame +); ------------------------------------------------------------------------------------------ -- Buffer fill levels, busy generation ------------------------------------------------------------------------------------------ -- We need to keep track of the APV analog fifo fill level. --- Two signals are used: +-- Two signals are used: -- - an early "FRAME_REQD" to decrement to number of free entries, --- - a late "FRAME_RCVD" to notify that a requested frame has been transfered +-- - a late "FRAME_RCVD" to notify that a requested frame has been transfered -- from APV to the raw buffer. apv_free_down <= frm_reqd_in; -apv_free_up <= adc_last; +apv_free_up <= adc_last; THE_APV_FREE_COUNTER_PROC: process( buf_clk_in ) begin @@ -313,14 +322,14 @@ begin if ( buf_reset_in = '1' ) then apv_free_ctr <= "10000"; elsif( apv_free_down = '1' and apv_free_up = '0' ) then - apv_free_ctr <= apv_free_ctr - 1; + apv_free_ctr <= apv_free_ctr - 1; elsif( apv_free_down = '0' and apv_free_up = '1' ) then apv_free_ctr <= apv_free_ctr + 1; end if; end if; end process THE_APV_FREE_COUNTER_PROC; --- The raw data buffer is also to be watched carefully. +-- The raw data buffer is also to be watched carefully. -- An early signal reserved on raw buffer page, while a late one releases one -- page to the buffer pool again. @@ -333,7 +342,7 @@ begin if ( buf_reset_in = '1' ) then buf_free_ctr <= "10000"; elsif( buf_free_down = '1' and buf_free_up = '0' ) then - buf_free_ctr <= buf_free_ctr - 1; + buf_free_ctr <= buf_free_ctr - 1; elsif( buf_free_down = '0' and buf_free_up = '1' ) then buf_free_ctr <= buf_free_ctr + 1; end if; @@ -351,8 +360,8 @@ THE_APV_BUF_ADDER: adder_6bit port map( DATAA => sum_apv, DATAB => sum_buf, CLOCK => buf_clk_in, - RESET => buf_reset_in, - CLOCKEN => '1', + RESET => buf_reset_in, + CLOCKEN => '1', RESULT => sum_apv_buf ); diff --git a/src/apv_sync_handler.vhd b/src/apv_sync_handler.vhd index 5360675..33e3ee7 100644 --- a/src/apv_sync_handler.vhd +++ b/src/apv_sync_handler.vhd @@ -7,56 +7,58 @@ library work; use work.adcmv3_components.all; entity apv_sync_handler is - port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock - RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) - CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; - APV_TRGSTART_IN : in std_logic; -- start signal for one sequence - APV_TRGSEL_IN : in std_logic; -- select signal for one sequence - APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished (100MHz) - APV_TRG_OUT : out std_logic; -- TRG line signal (40MHz APV) - APV_SYNC_OUT : out std_logic; -- signal for statemachines (40MHz APV) - BSM_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + APV_TRGSTART_IN : in std_logic; -- start signal for one sequence + APV_TRGSEL_IN : in std_logic; -- select signal for one sequence + APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished (100MHz) + APV_TRG_OUT : out std_logic; -- TRG line signal (40MHz APV) + APV_SYNC_OUT : out std_logic; -- signal for statemachines (40MHz APV) + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of apv_sync_handler is - -- state machine signals - type STATES is (SLEEP,START,T2,T1,T0,DLY0,DLY1,DLY2,DLY3,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; +-- state machine signals +type STATES is (SLEEP,START,T2,T1,T0,DLY0,DLY1,DLY2,DLY3,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; - -- normal signals - signal apv_trgdone : std_logic; - signal apv_trgstart : std_logic; - signal comb_apv_trgstart : std_logic; - -- state machine generated signals - signal next_apv_done : std_logic; - signal apv_done : std_logic; - signal next_apv_trg : std_logic; - signal apv_trg : std_logic; - signal next_apv_sync : std_logic; - signal apv_sync : std_logic; +-- normal signals +signal apv_trgdone : std_logic; +signal apv_trgstart : std_logic; +signal comb_apv_trgstart : std_logic; +-- state machine generated signals +signal next_apv_done : std_logic; +signal apv_done : std_logic; +signal next_apv_trg : std_logic; +signal apv_trg : std_logic; +signal next_apv_sync : std_logic; +signal apv_sync : std_logic; begin -- APV_TRGSTART_IN crosses a clock domain (100M -> 40M). -comb_apv_trgstart <= apv_trgstart_in and apv_trgsel_in; +comb_apv_trgstart <= apv_trgstart_in and apv_trgsel_in; THE_APVTRGSTART_SYNC: pulse_sync -port map( CLK_A_IN => clk_in, - RESET_A_IN => reset_in, - PULSE_A_IN => comb_apv_trgstart, - CLK_B_IN => clk_apv_in, - RESET_B_IN => reset_apv_in, - PULSE_B_OUT => apv_trgstart - ); +port map( + CLK_A_IN => clk_in, + RESET_A_IN => reset_in, + PULSE_A_IN => comb_apv_trgstart, + CLK_B_IN => clk_apv_in, + RESET_B_IN => reset_apv_in, + PULSE_B_OUT => apv_trgstart +); -- A statemachine handles all actions for creating the trigger sequence -- state registers -STATE_MEM: process( clk_apv_in ) +STATE_MEM: process( clk_apv_in ) begin if( rising_edge(clk_apv_in) ) then if( reset_apv_in = '1' ) then @@ -81,29 +83,29 @@ begin next_apv_trg <= '0'; next_apv_sync <= '0'; case CURRENT_STATE is - when SLEEP => if( apv_trgstart = '1' ) then + when SLEEP => if( apv_trgstart = '1' ) then NEXT_STATE <= START; else NEXT_STATE <= SLEEP; end if; - when START => NEXT_STATE <= T2; + when START => NEXT_STATE <= T2; next_apv_trg <= '1'; - when T2 => NEXT_STATE <= T1; - when T1 => NEXT_STATE <= T0; + when T2 => NEXT_STATE <= T1; + when T1 => NEXT_STATE <= T0; next_apv_trg <= '1'; - when T0 => NEXT_STATE <= DLY0; + when T0 => NEXT_STATE <= DLY0; next_apv_sync <= '1'; - when DLY0 => NEXT_STATE <= DLY1; + when DLY0 => NEXT_STATE <= DLY1; next_apv_sync <= '1'; - when DLY1 => NEXT_STATE <= DLY2; + when DLY1 => NEXT_STATE <= DLY2; next_apv_sync <= '1'; - when DLY2 => NEXT_STATE <= DLY3; + when DLY2 => NEXT_STATE <= DLY3; next_apv_sync <= '1'; - when DLY3 => NEXT_STATE <= DONE; + when DLY3 => NEXT_STATE <= DONE; next_apv_done <= '1'; next_apv_sync <= '1'; - when DONE => NEXT_STATE <= SLEEP; - when others => NEXT_STATE <= SLEEP; + when DONE => NEXT_STATE <= SLEEP; + when others => NEXT_STATE <= SLEEP; end case; end process STATE_TRANSFORM; @@ -111,36 +113,37 @@ end process STATE_TRANSFORM; STATE_DECODE: process( CURRENT_STATE ) begin case CURRENT_STATE is - when SLEEP => bsm_out <= x"0"; - when START => bsm_out <= x"1"; - when T2 => bsm_out <= x"2"; - when T1 => bsm_out <= x"3"; - when T0 => bsm_out <= x"4"; - when DLY0 => bsm_out <= x"5"; - when DLY1 => bsm_out <= x"6"; - when DLY2 => bsm_out <= x"7"; - when DLY3 => bsm_out <= x"8"; - when DONE => bsm_out <= x"9"; - when others => bsm_out <= x"f"; + when SLEEP => bsm_out <= x"0"; + when START => bsm_out <= x"1"; + when T2 => bsm_out <= x"2"; + when T1 => bsm_out <= x"3"; + when T0 => bsm_out <= x"4"; + when DLY0 => bsm_out <= x"5"; + when DLY1 => bsm_out <= x"6"; + when DLY2 => bsm_out <= x"7"; + when DLY3 => bsm_out <= x"8"; + when DONE => bsm_out <= x"9"; + when others => bsm_out <= x"f"; end case; end process STATE_DECODE; -- APV_TRGDONE_OUT crosses a clock domain (40M -> 100M). THE_APVTRGDONE_SYNC: pulse_sync -port map( CLK_A_IN => clk_apv_in, - RESET_A_IN => reset_apv_in, - PULSE_A_IN => apv_done, - CLK_B_IN => clk_in, - RESET_B_IN => reset_in, - PULSE_B_OUT => apv_trgdone - ); +port map( + CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_apv_in, + PULSE_A_IN => apv_done, + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + PULSE_B_OUT => apv_trgdone +); -- output signals apv_trgdone_out <= apv_trgdone; apv_trg_out <= apv_trg; apv_sync_out <= apv_sync; -debug_out(15 downto 0) <= (others => '0'); +debug_out(15 downto 0) <= (others => '0'); end behavioral; diff --git a/src/apv_trg_handler.vhd b/src/apv_trg_handler.vhd index af130f0..36063b4 100644 --- a/src/apv_trg_handler.vhd +++ b/src/apv_trg_handler.vhd @@ -7,74 +7,76 @@ library work; use work.adcmv3_components.all; entity apv_trg_handler is - port( CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock - RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) - CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; -- synced reset signal (100MHz master clock) - APV_TRGSTART_IN : in std_logic; -- start signal for one sequence - APV_TRGSEL_IN : in std_logic; -- select signal for one sequence - APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers - APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers - APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished - APV_TRG_OUT : out std_logic; - APV_TRGSENT_OUT : out std_logic; - BSM_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + RESET_APV_IN : in std_logic; -- synced reset signal (40MHz APV) + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; -- synced reset signal (100MHz master clock) + APV_TRGSTART_IN : in std_logic; -- start signal for one sequence + APV_TRGSEL_IN : in std_logic; -- select signal for one sequence + APV_TRG_TODO_IN : in std_logic_vector(3 downto 0); -- number of APV triggers + APV_TRG_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between APV triggers + APV_TRGDONE_OUT : out std_logic; -- APV trigger statemachine finished + APV_TRG_OUT : out std_logic; + APV_TRGSENT_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of apv_trg_handler is - -- state machine signals - type STATES is (SLEEP,START,T2,T1,T0,DEL,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - -- normal signals - signal apv_trgstart : std_logic; - signal next_apv_trgstart : std_logic; - signal todo_ctr : std_logic_vector(3 downto 0); - signal comb_todo_done : std_logic; - signal delay_ctr : std_logic_vector(3 downto 0); - signal comb_delay_done : std_logic; - signal apv_trgsent : std_logic; - signal apv_trgdone : std_logic; - - -- State machine generates signals - signal next_todo_ctr_ce : std_logic; - signal todo_ctr_ce : std_logic; - signal next_delay_ctr_ce : std_logic; - signal delay_ctr_ce : std_logic; - signal next_delay_ctr_ld : std_logic; - signal delay_ctr_ld : std_logic; - signal next_apv_done : std_logic; - signal apv_done : std_logic; - signal next_apv_trgcnt : std_logic; - signal apv_trgcnt : std_logic; - signal next_apv_trg : std_logic; - signal apv_trg : std_logic; +-- state machine signals +type STATES is (SLEEP,START,T2,T1,T0,DEL,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- normal signals +signal apv_trgstart : std_logic; +signal next_apv_trgstart : std_logic; +signal todo_ctr : std_logic_vector(3 downto 0); +signal comb_todo_done : std_logic; +signal delay_ctr : std_logic_vector(3 downto 0); +signal comb_delay_done : std_logic; +signal apv_trgsent : std_logic; +signal apv_trgdone : std_logic; + +-- State machine generates signals +signal next_todo_ctr_ce : std_logic; +signal todo_ctr_ce : std_logic; +signal next_delay_ctr_ce : std_logic; +signal delay_ctr_ce : std_logic; +signal next_delay_ctr_ld : std_logic; +signal delay_ctr_ld : std_logic; +signal next_apv_done : std_logic; +signal apv_done : std_logic; +signal next_apv_trgcnt : std_logic; +signal apv_trgcnt : std_logic; +signal next_apv_trg : std_logic; +signal apv_trg : std_logic; begin -- APV_TRGSTART_IN crosses a clock domain (100M -> 40M). -next_apv_trgstart <= apv_trgstart_in and apv_trgsel_in; +next_apv_trgstart <= apv_trgstart_in and apv_trgsel_in; THE_APVTRGSTART_SYNC: pulse_sync -port map( CLK_A_IN => clk_in, - RESET_A_IN => reset_in, - PULSE_A_IN => next_apv_trgstart, - CLK_B_IN => clk_apv_in, - RESET_B_IN => reset_apv_in, - PULSE_B_OUT => apv_trgstart - ); +port map( + CLK_A_IN => clk_in, + RESET_A_IN => reset_in, + PULSE_A_IN => next_apv_trgstart, + CLK_B_IN => clk_apv_in, + RESET_B_IN => reset_apv_in, + PULSE_B_OUT => apv_trgstart +); -- A statemachine handles all actions for creating the trigger sequence (40MHz domain) -- state registers -STATE_MEM: process( clk_apv_in ) +STATE_MEM: process( clk_apv_in ) begin if( rising_edge(clk_apv_in) ) then if( reset_apv_in = '1' ) then CURRENT_STATE <= SLEEP; - todo_ctr_ce <= '0'; + todo_ctr_ce <= '0'; delay_ctr_ce <= '0'; delay_ctr_ld <= '0'; apv_done <= '0'; @@ -103,12 +105,12 @@ begin next_apv_trg <= '0'; next_apv_trgcnt <= '0'; case CURRENT_STATE is - when SLEEP => if( apv_trgstart = '1' ) then + when SLEEP => if( apv_trgstart = '1' ) then NEXT_STATE <= START; else NEXT_STATE <= SLEEP; end if; - when START => if( comb_todo_done = '1' ) then + when START => if( comb_todo_done = '1' ) then NEXT_STATE <= DONE; next_apv_done <= '1'; else @@ -116,12 +118,12 @@ begin next_delay_ctr_ld <= '1'; next_apv_trg <= '1'; end if; - when T2 => NEXT_STATE <= T1; + when T2 => NEXT_STATE <= T1; next_todo_ctr_ce <= '1'; next_apv_trgcnt <= '1'; - when T1 => NEXT_STATE <= T0; + when T1 => NEXT_STATE <= T0; next_delay_ctr_ce <= '1'; - when T0 => if ( (comb_todo_done = '1') ) then + when T0 => if ( (comb_todo_done = '1') ) then NEXT_STATE <= DONE; next_apv_done <= '1'; elsif( (comb_todo_done = '0') and (comb_delay_done = '0') ) then @@ -132,7 +134,7 @@ begin next_delay_ctr_ld <= '1'; next_apv_trg <= '1'; end if; - when DEL => if( comb_delay_done = '1' ) then + when DEL => if( comb_delay_done = '1' ) then NEXT_STATE <= T2; next_delay_ctr_ld <= '1'; next_apv_trg <= '1'; @@ -140,8 +142,8 @@ begin NEXT_STATE <= DEL; next_delay_ctr_ce <= '1'; end if; - when DONE => NEXT_STATE <= SLEEP; - when others => NEXT_STATE <= SLEEP; + when DONE => NEXT_STATE <= SLEEP; + when others => NEXT_STATE <= SLEEP; end case; end process STATE_TRANSFORM; @@ -149,14 +151,14 @@ end process STATE_TRANSFORM; STATE_DECODE: process( CURRENT_STATE ) begin case CURRENT_STATE is - when SLEEP => bsm_out <= x"0"; - when START => bsm_out <= x"1"; - when T2 => bsm_out <= x"2"; - when T1 => bsm_out <= x"3"; - when T0 => bsm_out <= x"4"; - when DEL => bsm_out <= x"5"; - when DONE => bsm_out <= x"6"; - when others => bsm_out <= x"f"; + when SLEEP => bsm_out <= x"0"; + when START => bsm_out <= x"1"; + when T2 => bsm_out <= x"2"; + when T1 => bsm_out <= x"3"; + when T0 => bsm_out <= x"4"; + when DEL => bsm_out <= x"5"; + when DONE => bsm_out <= x"6"; + when others => bsm_out <= x"f"; end case; end process STATE_DECODE; @@ -192,31 +194,33 @@ comb_delay_done <= '1' when (delay_ctr = x"0") else '0'; -- APV_TRGSENT_OUT crosses a clock domain (40M -> 100M). THE_APVTRGSENT_SYNC: pulse_sync -port map( CLK_A_IN => clk_apv_in, - RESET_A_IN => reset_apv_in, - PULSE_A_IN => apv_trgcnt, - CLK_B_IN => clk_in, - RESET_B_IN => reset_in, - PULSE_B_OUT => apv_trgsent - ); +port map( + CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_apv_in, + PULSE_A_IN => apv_trgcnt, + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + PULSE_B_OUT => apv_trgsent +); -- APV_TRGDONE_OUT crosses a clock domain (40M -> 100M). THE_APVTRGDONE_SYNC: pulse_sync -port map( CLK_A_IN => clk_apv_in, - RESET_A_IN => reset_apv_in, - PULSE_A_IN => apv_done, - CLK_B_IN => clk_in, - RESET_B_IN => reset_in, - PULSE_B_OUT => apv_trgdone - ); +port map( + CLK_A_IN => clk_apv_in, + RESET_A_IN => reset_apv_in, + PULSE_A_IN => apv_done, + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + PULSE_B_OUT => apv_trgdone +); -- output signals apv_trgdone_out <= apv_trgdone; apv_trg_out <= apv_trg; apv_trgsent_out <= apv_trgsent; -debug_out(15 downto 12) <= todo_ctr; -debug_out(11 downto 8) <= delay_ctr; +debug_out(15 downto 12) <= todo_ctr; +debug_out(11 downto 8) <= delay_ctr; debug_out(7) <= delay_ctr_ld; debug_out(6) <= '0'; debug_out(5) <= comb_delay_done; diff --git a/src/apv_trgctrl.vhd b/src/apv_trgctrl.vhd index 8b43a32..2ce2960 100644 --- a/src/apv_trgctrl.vhd +++ b/src/apv_trgctrl.vhd @@ -7,97 +7,101 @@ library work; use work.adcmv3_components.all; entity apv_trgctrl is - port( CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; -- 100MHz clock domain reset - CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock - -- Triggers - SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs - TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs - TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs - STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow - TRG_FOUND_OUT : out std_logic; - -- slow control settings - TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event - TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 - TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers - TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 - TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers - TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 - TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers - TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 - TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers - TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers - -- TRB LVL1 signals - TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag - TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag - TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type - TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received - TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger - TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel - TRB_RST_COUNTER_IN : in std_logic; -- reset timing trigger counter - TRB_COUNTER_OUT : out std_logic_vector(15 downto 0); -- timing trigger counter - -- EDS signals - EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word - EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done - EDS_DONE_IN : in std_logic; -- release current EDS buffer - EDS_FULL_OUT : out std_logic; -- EDS buffer is full - EDS_LEVEL_OUT : out std_logic_vector(4 downto 0); - FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement) - -- APV signals - APV_TRG_OUT : out std_logic; - APV_SYNC_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(63 downto 0) - ); +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; -- 100MHz clock domain reset + CLK_APV_IN : in std_logic; -- 40MHz phase shifted clock + -- Triggers + SYNC_TRG_IN : in std_logic; -- 100MHz signal to SYNC APVs + TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs + TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs + STILL_BUSY_IN : in std_logic; -- set to '1' if any buffer is in danger of overflow + TRG_FOUND_OUT : out std_logic; + SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number + -- slow control settings + TRG_MAX_OUT : out std_logic_vector(3 downto 0); -- maximum number of triggers/event + TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 + TRG_3_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 + TRG_2_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 + TRG_1_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 + TRG_0_DELAY_IN : in std_logic_vector(3 downto 0); -- delay between triggers + TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers + -- TRB LVL1 signals + TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag + TRB_TRND_IN : in std_logic_vector(7 downto 0); -- TRB LVL1 random tag + TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- TRB LVL1 trigger type + TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- TRB LVL1 trigger information + TRB_TRGRCVD_IN : in std_logic; -- TRB LVL1 trigger received + TRB_MISSING_OUT : out std_logic; -- TRB LVL1 trigger arrived, but has no corresponding timing trigger + TRB_RELEASE_OUT : out std_logic; -- release TRB LVL1 channel + TRB_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local timing trigger counter + TRB_COUNTER_IN : in std_logic_vector(15 downto 0); -- TRB counter input + TRB_LD_COUNTER_IN : in std_logic; -- load local counter with TRB counter value + -- EDS signals + EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EventDataSheet (tm) data word + EDS_AVAIL_OUT : out std_logic; -- EDS valid, APV trigger done + EDS_DONE_IN : in std_logic; -- release current EDS buffer + EDS_FULL_OUT : out std_logic; -- EDS buffer is full + EDS_LEVEL_OUT : out std_logic_vector(4 downto 0); + FRM_REQD_OUT : out std_logic; -- frame requested, (level counter decrement) + -- APV signals + APV_TRG_OUT : out std_logic; + APV_SYNC_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(63 downto 0) +); end; architecture behavioral of apv_trgctrl is - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of behavioral : architecture is "APV_TRG_CTRL_group"; - - -- normal signals - signal apv_trgsel : std_logic_vector(3 downto 0); - signal apv_trgstart : std_logic; - signal apv_trgdone : std_logic_vector(3 downto 0); - signal next_apv_trgdone_all : std_logic; - signal apv_trgdone_all : std_logic; - signal apv_trg : std_logic_vector(3 downto 0); - signal next_apv_trg_all : std_logic; - signal apv_trg_all : std_logic; - signal apv_clk_rst : std_logic; -- 40MHz sync'ed reset signal - - signal sc_trg_stretch : std_logic_vector(3 downto 0); - signal maximum_trg : std_logic_vector(3 downto 0); - - -- EDS fill signals - signal atc_eds_data : std_logic_vector(39 downto 0); - signal atc_eds_start : std_logic; - signal atc_eds_we : std_logic; - signal eds_data : std_logic_vector(39 downto 0); - signal eds_full : std_logic; - signal eds_avail : std_logic; - signal eds_level : std_logic_vector(4 downto 0); - signal trb_release : std_logic; - signal trb_missing : std_logic; - signal trg_found : std_logic; - - signal test_eds_data : std_logic_vector(39 downto 0); - - -- APV signals - signal apv_trgsent : std_logic_vector(3 downto 0); - signal next_apv_trgsent_all : std_logic; - signal apv_trgsent_all : std_logic; - signal apv_sync : std_logic; - signal apv_sync_signal : std_logic; - - signal trb_counter : std_logic_vector(15 downto 0); - signal busy_release : std_logic; - - signal debug : std_logic_vector(63 downto 0); - signal bsm : std_logic_vector(7 downto 0); - +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of behavioral : architecture is "APV_TRG_CTRL_group"; + +-- normal signals +signal apv_trgsel : std_logic_vector(3 downto 0); +signal apv_trgstart : std_logic; +signal apv_trgdone : std_logic_vector(3 downto 0); +signal next_apv_trgdone_all : std_logic; +signal apv_trgdone_all : std_logic; +signal apv_trg : std_logic_vector(3 downto 0); +signal next_apv_trg_all : std_logic; +signal apv_trg_all : std_logic; +signal apv_clk_rst : std_logic; -- 40MHz sync'ed reset signal + +signal sc_trg_stretch : std_logic_vector(3 downto 0); +signal maximum_trg : std_logic_vector(3 downto 0); + +-- EDS fill signals +signal atc_eds_data : std_logic_vector(39 downto 0); +signal atc_eds_start : std_logic; +signal atc_eds_we : std_logic; +signal eds_data : std_logic_vector(39 downto 0); +signal eds_full : std_logic; +signal eds_avail : std_logic; +signal eds_level : std_logic_vector(4 downto 0); +signal trb_release : std_logic; +signal trb_missing : std_logic; +signal trg_found : std_logic; + +signal test_eds_data : std_logic_vector(39 downto 0); + +-- APV signals +signal apv_trgsent : std_logic_vector(3 downto 0); +signal next_apv_trgsent_all : std_logic; +signal apv_trgsent_all : std_logic; +signal apv_sync : std_logic; +signal apv_sync_signal : std_logic; + +signal trb_counter : std_logic_vector(15 downto 0); +signal busy_release : std_logic; + +signal debug : std_logic_vector(63 downto 0); +signal bsm : std_logic_vector(7 downto 0); + begin --------------------------------------------------------------------------- @@ -111,43 +115,48 @@ debug(39 downto 0) <= test_eds_data; -- RESET signal clock domain crossing (100MHz sysclk -> 40MHz APV clock) --------------------------------------------------------------------------- THE_RESET_SYNC: state_sync -port map( STATE_A_IN => reset_in, - CLK_B_IN => clk_apv_in, - RESET_B_IN => '0', - STATE_B_OUT => apv_clk_rst - ); - +port map( + STATE_A_IN => reset_in, + CLK_B_IN => clk_apv_in, + RESET_B_IN => '0', + STATE_B_OUT => apv_clk_rst +); + --------------------------------------------------------------------------- -- TRB trigger (one clock pulse) stretchers --------------------------------------------------------------------------- SC_TRG0_STRECH: pulse_stretch -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - START_IN => trb_trg_in(0), - PULSE_OUT => sc_trg_stretch(0), - DEBUG_OUT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => trb_trg_in(0), + PULSE_OUT => sc_trg_stretch(0), + DEBUG_OUT => open +); SC_TRG1_STRECH: pulse_stretch -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - START_IN => trb_trg_in(1), - PULSE_OUT => sc_trg_stretch(1), - DEBUG_OUT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => trb_trg_in(1), + PULSE_OUT => sc_trg_stretch(1), + DEBUG_OUT => open +); SC_TRG2_STRECH: pulse_stretch -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - START_IN => trb_trg_in(2), - PULSE_OUT => sc_trg_stretch(2), - DEBUG_OUT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => trb_trg_in(2), + PULSE_OUT => sc_trg_stretch(2), + DEBUG_OUT => open +); SC_TRG3_STRECH: pulse_stretch -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - START_IN => trb_trg_in(3), - PULSE_OUT => sc_trg_stretch(3), - DEBUG_OUT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => trb_trg_in(3), + PULSE_OUT => sc_trg_stretch(3), + DEBUG_OUT => open +); --------------------------------------------------------------------------- -- Busy handling @@ -165,48 +174,53 @@ end process THE_SYNC_PROC; -- for generation of APV TRG pulse sequences (like 1-0-0, or 1-0-1, etc.) --------------------------------------------------------------------------- THE_REAL_TRG_HANDLER: real_trg_handler -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - TIME_TRG_IN => time_trg_in, - TRB_TRG_IN => sc_trg_stretch, - APV_TRGDONE_IN => apv_trgdone_all, - TRG_3_TODO_IN => trg_3_todo_in, - TRG_2_TODO_IN => trg_2_todo_in, - TRG_1_TODO_IN => trg_1_todo_in, - TRG_0_TODO_IN => trg_0_todo_in, - TRG_SETUP_IN => trg_setup_in, - TRG_FOUND_OUT => trg_found, - TRB_TTAG_IN => trb_ttag_in, - TRB_TRND_IN => trb_trnd_in, - TRB_TTYPE_IN => trb_ttype_in, - TRB_TRGRCVD_IN => trb_trgrcvd_in, - TRB_MISSING_OUT => trb_missing, - BUSY_RELEASE_IN => busy_release, - RST_LVL1_COUNTER_IN => trb_rst_counter_in, - LVL1_COUNTER_OUT => trb_counter, - APV_TRGSEL_OUT => apv_trgsel, - APV_TRGSTART_OUT => apv_trgstart, - EDS_DATA_OUT => atc_eds_data, - EDS_START_OUT => atc_eds_start, -- just for debugging - EDS_WE_OUT => atc_eds_we, - EDS_READY_OUT => trb_release, - DBG_FRMCTR_OUT => open, - BSM_OUT => bsm, --open, - DEBUG_OUT => open --debug - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + TIME_TRG_IN => time_trg_in, + TRB_TRG_IN => sc_trg_stretch, + APV_TRGDONE_IN => apv_trgdone_all, + TRG_3_TODO_IN => trg_3_todo_in, + TRG_2_TODO_IN => trg_2_todo_in, + TRG_1_TODO_IN => trg_1_todo_in, + TRG_0_TODO_IN => trg_0_todo_in, + TRG_SETUP_IN => trg_setup_in, + TRG_FOUND_OUT => trg_found, + SECTOR_IN => sector_in, + TRB_TTAG_IN => trb_ttag_in, + TRB_TRND_IN => trb_trnd_in, + TRB_TTYPE_IN => trb_ttype_in, + TRB_TINFO_IN => trb_tinfo_in, + TRB_TRGRCVD_IN => trb_trgrcvd_in, + TRB_MISSING_OUT => trb_missing, + BUSY_RELEASE_IN => busy_release, + LVL1_COUNTER_OUT => trb_counter, + LVL1_COUNTER_IN => trb_counter_in, + LVL1_LD_COUNTER_IN => trb_ld_counter_in, + APV_TRGSEL_OUT => apv_trgsel, + APV_TRGSTART_OUT => apv_trgstart, + EDS_DATA_OUT => atc_eds_data, + EDS_START_OUT => atc_eds_start, -- just for debugging + EDS_WE_OUT => atc_eds_we, + EDS_READY_OUT => trb_release, + DBG_FRMCTR_OUT => open, + BSM_OUT => bsm, --open, + DEBUG_OUT => open --debug +); -- automatically determine the maximum amount of APV frames per trigger -- mind the delay in this block! THE_MAX_TRG: max_data -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - TODO_3_IN => trg_3_todo_in, - TODO_2_IN => trg_2_todo_in, - TODO_1_IN => trg_1_todo_in, - TODO_0_IN => trg_0_todo_in, - TODO_MAX_OUT => maximum_trg, - DEBUG_OUT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + TODO_3_IN => trg_3_todo_in, + TODO_2_IN => trg_2_todo_in, + TODO_1_IN => trg_1_todo_in, + TODO_0_IN => trg_0_todo_in, + TODO_MAX_OUT => maximum_trg, + DEBUG_OUT => open +); -- Only for storing last EDS for debugging! THE_TEST_EDS_DATA_PROC: process( clk_in ) @@ -222,110 +236,116 @@ end process THE_TEST_EDS_DATA_PROC; -- EDS buffer with fill level information --------------------------------------------------------------------------- THE_EDS_BUF: eds_buf -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - EDS_DATA_IN => atc_eds_data, -- data from trigger handler - EDS_WE_IN => atc_eds_we, -- write enable from trigger handler - EDS_DONE_IN => eds_done_in, -- release current EDS page - EDS_DATA_OUT => eds_data, -- current EDS data out - EDS_AVAILABLE_OUT => eds_avail, -- current EDS is valid - BUF_FULL_OUT => eds_full, -- EDS buffer is full - BUF_LEVEL_OUT => eds_level, -- for debugging - DEBUG_OUT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + EDS_DATA_IN => atc_eds_data, -- data from trigger handler + EDS_WE_IN => atc_eds_we, -- write enable from trigger handler + EDS_DONE_IN => eds_done_in, -- release current EDS page + EDS_DATA_OUT => eds_data, -- current EDS data out + EDS_AVAILABLE_OUT => eds_avail, -- current EDS is valid + BUF_FULL_OUT => eds_full, -- EDS buffer is full + BUF_LEVEL_OUT => eds_level, -- for debugging + DEBUG_OUT => open +); --------------------------------------------------------------------------- -- Trigger input 3: normal trigger --------------------------------------------------------------------------- THE_APV_TRG_HANDLER_3: apv_trg_handler -port map( CLK_APV_IN => clk_apv_in, - RESET_APV_IN => apv_clk_rst, - CLK_IN => clk_in, - RESET_IN => reset_in, - APV_TRGSTART_IN => apv_trgstart, - APV_TRGSEL_IN => apv_trgsel(3), - APV_TRG_TODO_IN => trg_3_todo_in, - APV_TRG_DELAY_IN => trg_3_delay_in, - APV_TRGDONE_OUT => apv_trgdone(3), - APV_TRG_OUT => apv_trg(3), - APV_TRGSENT_OUT => apv_trgsent(3), - BSM_OUT => open, - DEBUG_OUT => open - ); +port map( + CLK_APV_IN => clk_apv_in, + RESET_APV_IN => apv_clk_rst, + CLK_IN => clk_in, + RESET_IN => reset_in, + APV_TRGSTART_IN => apv_trgstart, + APV_TRGSEL_IN => apv_trgsel(3), + APV_TRG_TODO_IN => trg_3_todo_in, + APV_TRG_DELAY_IN => trg_3_delay_in, + APV_TRGDONE_OUT => apv_trgdone(3), + APV_TRG_OUT => apv_trg(3), + APV_TRGSENT_OUT => apv_trgsent(3), + BSM_OUT => open, + DEBUG_OUT => open +); --------------------------------------------------------------------------- -- Trigger input 2: normal trigger --------------------------------------------------------------------------- THE_APV_TRG_HANDLER_2: apv_trg_handler -port map( CLK_APV_IN => clk_apv_in, - RESET_APV_IN => apv_clk_rst, - CLK_IN => clk_in, - RESET_IN => reset_in, - APV_TRGSTART_IN => apv_trgstart, - APV_TRGSEL_IN => apv_trgsel(2), - APV_TRG_TODO_IN => trg_2_todo_in, - APV_TRG_DELAY_IN => trg_2_delay_in, - APV_TRGDONE_OUT => apv_trgdone(2), - APV_TRG_OUT => apv_trg(2), - APV_TRGSENT_OUT => apv_trgsent(2), - BSM_OUT => open, - DEBUG_OUT => open - ); +port map( + CLK_APV_IN => clk_apv_in, + RESET_APV_IN => apv_clk_rst, + CLK_IN => clk_in, + RESET_IN => reset_in, + APV_TRGSTART_IN => apv_trgstart, + APV_TRGSEL_IN => apv_trgsel(2), + APV_TRG_TODO_IN => trg_2_todo_in, + APV_TRG_DELAY_IN => trg_2_delay_in, + APV_TRGDONE_OUT => apv_trgdone(2), + APV_TRG_OUT => apv_trg(2), + APV_TRGSENT_OUT => apv_trgsent(2), + BSM_OUT => open, + DEBUG_OUT => open +); --------------------------------------------------------------------------- -- Trigger input 1: normal trigger --------------------------------------------------------------------------- THE_APV_TRG_HANDLER_1: apv_trg_handler -port map( CLK_APV_IN => clk_apv_in, - RESET_APV_IN => apv_clk_rst, - CLK_IN => clk_in, - RESET_IN => reset_in, - APV_TRGSTART_IN => apv_trgstart, - APV_TRGSEL_IN => apv_trgsel(1), - APV_TRG_TODO_IN => trg_1_todo_in, - APV_TRG_DELAY_IN => trg_1_delay_in, - APV_TRGDONE_OUT => apv_trgdone(1), - APV_TRG_OUT => apv_trg(1), - APV_TRGSENT_OUT => apv_trgsent(1), - BSM_OUT => open, - DEBUG_OUT => open - ); +port map( + CLK_APV_IN => clk_apv_in, + RESET_APV_IN => apv_clk_rst, + CLK_IN => clk_in, + RESET_IN => reset_in, + APV_TRGSTART_IN => apv_trgstart, + APV_TRGSEL_IN => apv_trgsel(1), + APV_TRG_TODO_IN => trg_1_todo_in, + APV_TRG_DELAY_IN => trg_1_delay_in, + APV_TRGDONE_OUT => apv_trgdone(1), + APV_TRG_OUT => apv_trg(1), + APV_TRGSENT_OUT => apv_trgsent(1), + BSM_OUT => open, + DEBUG_OUT => open +); --------------------------------------------------------------------------- -- Trigger input 0: normal trigger --------------------------------------------------------------------------- THE_APV_TRG_HANDLER_0: apv_trg_handler -port map( CLK_APV_IN => clk_apv_in, - RESET_APV_IN => apv_clk_rst, - CLK_IN => clk_in, - RESET_IN => reset_in, - APV_TRGSTART_IN => apv_trgstart, - APV_TRGSEL_IN => apv_trgsel(0), - APV_TRG_TODO_IN => trg_0_todo_in, - APV_TRG_DELAY_IN => trg_0_delay_in, - APV_TRGDONE_OUT => apv_trgdone(0), - APV_TRG_OUT => apv_trg(0), - APV_TRGSENT_OUT => apv_trgsent(0), - BSM_OUT => open, - DEBUG_OUT => open - ); +port map( + CLK_APV_IN => clk_apv_in, + RESET_APV_IN => apv_clk_rst, + CLK_IN => clk_in, + RESET_IN => reset_in, + APV_TRGSTART_IN => apv_trgstart, + APV_TRGSEL_IN => apv_trgsel(0), + APV_TRG_TODO_IN => trg_0_todo_in, + APV_TRG_DELAY_IN => trg_0_delay_in, + APV_TRGDONE_OUT => apv_trgdone(0), + APV_TRG_OUT => apv_trg(0), + APV_TRGSENT_OUT => apv_trgsent(0), + BSM_OUT => open, + DEBUG_OUT => open +); --------------------------------------------------------------------------- -- APV SYNC trigger signal -- NOT CLEAN, outside trigger logic! --------------------------------------------------------------------------- THE_APV_SYNC_HANDLER: apv_sync_handler -port map( CLK_APV_IN => clk_apv_in, - RESET_APV_IN => apv_clk_rst, - CLK_IN => clk_in, - RESET_IN => reset_in, - APV_TRGSTART_IN => sync_trg_in, - APV_TRGSEL_IN => '1', - APV_TRGDONE_OUT => open, - APV_TRG_OUT => apv_sync_signal, - APV_SYNC_OUT => apv_sync, - BSM_OUT => open, - DEBUG_OUT => open - ); +port map( + CLK_APV_IN => clk_apv_in, + RESET_APV_IN => apv_clk_rst, + CLK_IN => clk_in, + RESET_IN => reset_in, + APV_TRGSTART_IN => sync_trg_in, + APV_TRGSEL_IN => '1', + APV_TRGDONE_OUT => open, + APV_TRG_OUT => apv_sync_signal, + APV_SYNC_OUT => apv_sync, + BSM_OUT => open, + DEBUG_OUT => open +); -- combine all DONE and SENT signals for feedback next_apv_trgdone_all <= apv_trgdone(3) or apv_trgdone(2) or apv_trgdone(1) or apv_trgdone(0); diff --git a/src/buf_toc.vhd b/src/buf_toc.vhd index 0cc2fc8..4026f02 100644 --- a/src/buf_toc.vhd +++ b/src/buf_toc.vhd @@ -10,68 +10,67 @@ use work.adcmv3_components.all; -- ddmmyy - blafasel entity buf_toc is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - BUF_TICK_IN : in std_logic; -- tickmark from raw buffer - BUF_START_IN : in std_logic; -- start of frame from raw buffer - WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode - FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS - BUF_LVL_IN : in std_logic_vector(7 downto 0); - GOODDATA_OUT : out std_logic; -- APV is on, sent data, process it - BADDATA_OUT : out std_logic; -- APV is on, broken buffer, NO processing, only ERROR HDR - NODATA_OUT : out std_logic; -- APV is off, do not send anything! - READY_OUT : out std_logic; - BSM_OUT : out std_logic_vector(7 downto 0); - DBG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUF_TICK_IN : in std_logic; -- tickmark from raw buffer + BUF_START_IN : in std_logic; -- start of frame from raw buffer + WAITFRAME_IN : in std_logic; -- statemachine is in "wait for frame" mode + FRAMES_REQD_IN : in std_logic_vector(3 downto 0); -- number of frames requested from EDS + BUF_LVL_IN : in std_logic_vector(7 downto 0); + GOODDATA_OUT : out std_logic; -- APV is on, sent data, process it + BADDATA_OUT : out std_logic; -- APV is on, broken buffer, NO processing, only ERROR HDR + NODATA_OUT : out std_logic; -- APV is off, do not send anything! + READY_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of buf_toc is - -- components +-- state machine signals +type STATES is (SLEEP,CLEAR,RSTTOC,WATCH,COUNT,GDATA,BDATA,IDATA,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; - -- state machine signals - type STATES is (SLEEP,CLEAR,RSTTOC,WATCH,COUNT,GDATA,BDATA,IDATA,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; +-- normal signals +signal bsm_x : std_logic_vector(7 downto 0); +signal debug_x : std_logic_vector(15 downto 0); - -- normal signals - signal bsm_x : std_logic_vector(7 downto 0); - signal debug_x : std_logic_vector(15 downto 0); +signal buf_lvl : std_logic_vector(4 downto 0); +signal buf_good : std_logic; +signal buf_broken : std_logic; +signal buf_ignore : std_logic; - signal buf_lvl : std_logic_vector(4 downto 0); - signal buf_good : std_logic; - signal buf_broken : std_logic; - signal buf_ignore : std_logic; - - signal next_gooddata : std_logic; - signal gooddata : std_logic; - signal next_baddata : std_logic; - signal baddata : std_logic; - signal next_nodata : std_logic; - signal nodata : std_logic; - signal next_ready : std_logic; - signal ready : std_logic; +signal next_gooddata : std_logic; +signal gooddata : std_logic; +signal next_baddata : std_logic; +signal baddata : std_logic; +signal next_nodata : std_logic; +signal nodata : std_logic; +signal next_ready : std_logic; +signal ready : std_logic; - signal frames_needed : std_logic_vector(4 downto 0); +signal frames_needed : std_logic_vector(4 downto 0); - signal next_frames_avail : std_logic; - signal frames_avail : std_logic; +signal next_frames_avail : std_logic; +signal frames_avail : std_logic; + +signal toc_ctr : std_logic_vector(3 downto 0); +signal next_toc_rst : std_logic; +signal toc_rst : std_logic; +signal next_toc_ce : std_logic; +signal toc_ce : std_logic; +signal next_toc_hit : std_logic; +signal toc_hit : std_logic; + +signal next_stat_clr : std_logic; +signal stat_clr : std_logic; + +signal stat_good : std_logic; +signal stat_bad : std_logic; +signal stat_ignore : std_logic; - signal toc_ctr : std_logic_vector(3 downto 0); - signal next_toc_rst : std_logic; - signal toc_rst : std_logic; - signal next_toc_ce : std_logic; - signal toc_ce : std_logic; - signal next_toc_hit : std_logic; - signal toc_hit : std_logic; - - signal next_stat_clr : std_logic; - signal stat_clr : std_logic; - - signal stat_good : std_logic; - signal stat_bad : std_logic; - signal stat_ignore : std_logic; - begin -- Aliasing @@ -109,7 +108,7 @@ end process THE_SYNC_PROC; -- state machine for handling synchronisation -- state registers -STATE_MEM: process( clk_in ) +STATE_MEM: process( clk_in ) begin if( rising_edge(clk_in) ) then if( reset_in = '1' ) then @@ -136,7 +135,7 @@ end process STATE_MEM; -- state transitions -STATE_TRANSFORM: process( CURRENT_STATE, waitframe_in, buf_good, buf_ignore, +STATE_TRANSFORM: process( CURRENT_STATE, waitframe_in, buf_good, buf_ignore, buf_start_in, buf_tick_in, frames_avail, toc_hit ) begin NEXT_STATE <= SLEEP; -- avoid latches @@ -148,13 +147,13 @@ begin next_ready <= '0'; next_stat_clr <= '0'; case CURRENT_STATE is - when SLEEP => if( waitframe_in = '1' ) then + when SLEEP => if( waitframe_in = '1' ) then NEXT_STATE <= CLEAR; next_stat_clr <= '1'; else NEXT_STATE <= SLEEP; end if; - when CLEAR => if ( buf_ignore = '1' ) then + when CLEAR => if ( buf_ignore = '1' ) then NEXT_STATE <= IDATA; -- switched off buffer, ignore it next_nodata <= '1'; elsif( buf_good = '1' ) then @@ -164,8 +163,8 @@ begin NEXT_STATE <= BDATA; -- bad buffer, so we skip it immediatly next_baddata <= '1'; end if; - when RSTTOC => NEXT_STATE <= WATCH; - when WATCH => if ( frames_avail = '1' ) then + when RSTTOC => NEXT_STATE <= WATCH; + when WATCH => if ( frames_avail = '1' ) then NEXT_STATE <= GDATA; -- all frames did arrive next_gooddata <= '1'; elsif( (toc_hit = '1') or (buf_good = '0') ) then @@ -180,21 +179,21 @@ begin else NEXT_STATE <= WATCH; end if; - when COUNT => NEXT_STATE <= WATCH; - when GDATA => NEXT_STATE <= DONE; + when COUNT => NEXT_STATE <= WATCH; + when GDATA => NEXT_STATE <= DONE; next_ready <= '1'; - when BDATA => NEXT_STATE <= DONE; + when BDATA => NEXT_STATE <= DONE; next_ready <= '1'; - when IDATA => NEXT_STATE <= DONE; + when IDATA => NEXT_STATE <= DONE; next_ready <= '1'; - when DONE => if( waitframe_in = '1' ) then + when DONE => if( waitframe_in = '1' ) then NEXT_STATE <= DONE; next_ready <= '1'; else NEXT_STATE <= SLEEP; end if; - - when others => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; end case; end process STATE_TRANSFORM; @@ -202,16 +201,16 @@ end process STATE_TRANSFORM; STATE_DECODE: process( CURRENT_STATE ) begin case CURRENT_STATE is - when SLEEP => bsm_x <= x"00"; - when CLEAR => bsm_x <= x"01"; - when RSTTOC => bsm_x <= x"02"; - when WATCH => bsm_x <= x"03"; - when COUNT => bsm_x <= x"04"; - when GDATA => bsm_x <= x"05"; - when BDATA => bsm_x <= x"06"; - when IDATA => bsm_x <= x"07"; - when DONE => bsm_x <= x"08"; - when others => bsm_x <= x"ff"; + when SLEEP => bsm_x <= x"00"; + when CLEAR => bsm_x <= x"01"; + when RSTTOC => bsm_x <= x"02"; + when WATCH => bsm_x <= x"03"; + when COUNT => bsm_x <= x"04"; + when GDATA => bsm_x <= x"05"; + when BDATA => bsm_x <= x"06"; + when IDATA => bsm_x <= x"07"; + when DONE => bsm_x <= x"08"; + when others => bsm_x <= x"ff"; end case; end process STATE_DECODE; diff --git a/src/dhdr_buf.vhd b/src/dhdr_buf.vhd index 8a18c7e..bb3c097 100644 --- a/src/dhdr_buf.vhd +++ b/src/dhdr_buf.vhd @@ -7,41 +7,42 @@ library work; use work.adcmv3_components.all; entity dhdr_buf is - port( CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; - -- DHDR information block - DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input - DHDR_WE_IN : in std_logic; -- EDS write enable - DHDR_DONE_IN : in std_logic; -- release EDS - DHDR_DATA_OUT : out std_logic_vector(47 downto 0); - DHDR_AVAILABLE_OUT : out std_logic; - -- trigger busy information - BUF_FULL_OUT : out std_logic; - BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); - -- Debug signals - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + -- DHDR information block + DHDR_DATA_IN : in std_logic_vector(47 downto 0); -- EDS data input + DHDR_WE_IN : in std_logic; -- EDS write enable + DHDR_DONE_IN : in std_logic; -- release EDS + DHDR_DATA_OUT : out std_logic_vector(47 downto 0); + DHDR_AVAILABLE_OUT : out std_logic; + -- trigger busy information + BUF_FULL_OUT : out std_logic; + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of dhdr_buf is - -- normal signals - signal debug : std_logic_vector(15 downto 0); - - -- Signals for controlling the DHDR buffer memory - signal dhdr_data : std_logic_vector(47 downto 0); - signal dhdr_rd_addr : std_logic_vector(3 downto 0); - signal dhdr_wr_addr : std_logic_vector(3 downto 0); - signal dhdr_wr : std_logic; - signal dhdr_rd : std_logic; - signal dhdr_free_ctr : std_logic_vector(4 downto 0); -- fill level counter - signal dhdr_free_up : std_logic; - signal dhdr_free_down : std_logic; - signal dhdr_available_x : std_logic; - signal dhdr_available : std_logic; -- at least one valid EDS entry is available - signal dhdr_full_x : std_logic; - signal dhdr_full : std_logic; - +-- normal signals +signal debug : std_logic_vector(15 downto 0); + +-- Signals for controlling the DHDR buffer memory +signal dhdr_data : std_logic_vector(47 downto 0); +signal dhdr_rd_addr : std_logic_vector(3 downto 0); +signal dhdr_wr_addr : std_logic_vector(3 downto 0); +signal dhdr_wr : std_logic; +signal dhdr_rd : std_logic; +signal dhdr_free_ctr : std_logic_vector(4 downto 0); -- fill level counter +signal dhdr_free_up : std_logic; +signal dhdr_free_down : std_logic; +signal dhdr_available_x : std_logic; +signal dhdr_available : std_logic; -- at least one valid EDS entry is available +signal dhdr_full_x : std_logic; +signal dhdr_full : std_logic; + begin -- General process for syncing combinatorial signals @@ -89,33 +90,41 @@ THE_DHDR_FREE_COUNTER_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then if ( reset_in = '1' ) then - dhdr_free_ctr <= "10000"; + dhdr_free_ctr <= b"10000"; elsif( (dhdr_free_down = '1') and (dhdr_free_up = '0') ) then - dhdr_free_ctr <= dhdr_free_ctr - 1; + dhdr_free_ctr <= dhdr_free_ctr - 1; elsif( (dhdr_free_down = '0') and (dhdr_free_up = '1') ) then dhdr_free_ctr <= dhdr_free_ctr + 1; end if; end if; end process THE_DHDR_FREE_COUNTER_PROC; -dhdr_full_x <= '1' when (dhdr_free_ctr = "00000") else '0'; +dhdr_full_x <= '1' when (dhdr_free_ctr = b"00001") else '0'; -- was zero before +dhdr_available_x <= '1' when (dhdr_free_ctr /= b"10000") else '0'; +-- danger. may also fail in case you release an entry before reserving it! + +-- replace this ugly rd/wr/free counters and the DPRAM by a FIFO. -- A 16x32b DPRAM is used for buffering the DataHeaDeR (DHDR) THE_DHDR_BUFFER: dhdr_buffer_dpram -port map( WRADDRESS => dhdr_wr_addr, - DATA => dhdr_data_in, - WRCLOCK => clk_in, - WE => dhdr_we_in, - WRCLOCKEN => '1', - RDADDRESS => dhdr_rd_addr, - RDCLOCK => clk_in, - RDCLOCKEN => '1', - RESET => reset_in, - Q => dhdr_data - ); +port map( + WRADDRESS => dhdr_wr_addr, + DATA => dhdr_data_in, + WRCLOCK => clk_in, + WE => dhdr_we_in, + WRCLOCKEN => '1', + RDADDRESS => dhdr_rd_addr, + RDCLOCK => clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + Q => dhdr_data +); -- Are there any EDS to work on? -dhdr_available_x <= '1' when (dhdr_wr_addr /= dhdr_rd_addr) else '0'; +--dhdr_available_x <= '1' when (dhdr_wr_addr /= dhdr_rd_addr) else '0'; +-- Epic fail: take 17 fast triggers => WR_ADDR = 1. +-- one slow IPU transfer => RD_ADDR = 1. +-- and as (1 /= 1) is false, the buffer is empty, blocking the next IPU transfer. -- Debug signals debug(15 downto 0) <= (others => '0'); diff --git a/src/eds_buf.vhd b/src/eds_buf.vhd index 446ffbb..5962967 100644 --- a/src/eds_buf.vhd +++ b/src/eds_buf.vhd @@ -7,41 +7,42 @@ library work; use work.adcmv3_components.all; entity eds_buf is - port( CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; - -- EDS input, all synced to CLK_IN - EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input - EDS_WE_IN : in std_logic; -- EDS write enable - EDS_DONE_IN : in std_logic; -- release EDS - EDS_DATA_OUT : out std_logic_vector(39 downto 0); - EDS_AVAILABLE_OUT : out std_logic; - -- trigger busy information - BUF_FULL_OUT : out std_logic; - BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); - -- Debug signals - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + -- EDS input, all synced to CLK_IN + EDS_DATA_IN : in std_logic_vector(39 downto 0); -- EDS data input + EDS_WE_IN : in std_logic; -- EDS write enable + EDS_DONE_IN : in std_logic; -- release EDS + EDS_DATA_OUT : out std_logic_vector(39 downto 0); + EDS_AVAILABLE_OUT : out std_logic; + -- trigger busy information + BUF_FULL_OUT : out std_logic; + BUF_LEVEL_OUT : out std_logic_vector(4 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of eds_buf is - -- normal signals - signal debug : std_logic_vector(15 downto 0); - - -- Signals for controlling the EDS buffer memory - signal eds_data : std_logic_vector(39 downto 0); - signal eds_rd_addr : std_logic_vector(3 downto 0); - signal eds_wr_addr : std_logic_vector(3 downto 0); - signal eds_wr : std_logic; - signal eds_rd : std_logic; - signal eds_free_ctr : std_logic_vector(4 downto 0); -- fill level counter - signal eds_free_up : std_logic; - signal eds_free_down : std_logic; - signal eds_available_x : std_logic; - signal eds_available : std_logic; -- at least one valid EDS entry is available - signal eds_full_x : std_logic; - signal eds_full : std_logic; - +-- normal signals +signal debug : std_logic_vector(15 downto 0); + +-- Signals for controlling the EDS buffer memory +signal eds_data : std_logic_vector(39 downto 0); +signal eds_rd_addr : std_logic_vector(3 downto 0); +signal eds_wr_addr : std_logic_vector(3 downto 0); +signal eds_wr : std_logic; +signal eds_rd : std_logic; +signal eds_free_ctr : std_logic_vector(4 downto 0); -- fill level counter +signal eds_free_up : std_logic; +signal eds_free_down : std_logic; +signal eds_available_x : std_logic; +signal eds_available : std_logic; -- at least one valid EDS entry is available +signal eds_full_x : std_logic; +signal eds_full : std_logic; + begin -- General process for syncing combinatorial signals @@ -89,33 +90,39 @@ THE_EDS_FREE_COUNTER_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then if ( reset_in = '1' ) then - eds_free_ctr <= "10000"; + eds_free_ctr <= b"10000"; elsif( eds_free_down = '1' and eds_free_up = '0' ) then - eds_free_ctr <= eds_free_ctr - 1; + eds_free_ctr <= eds_free_ctr - 1; elsif( eds_free_down = '0' and eds_free_up = '1' ) then eds_free_ctr <= eds_free_ctr + 1; end if; end if; end process THE_EDS_FREE_COUNTER_PROC; -eds_full_x <= '1' when (eds_free_ctr = "00000") else '0'; +eds_full_x <= '1' when (eds_free_ctr = b"00000") else '0'; +eds_available_x <= '1' when (eds_free_ctr /= b"10000") else '0'; +-- danger. may also fail in case you release an entry before reserving it! + +-- replace this ugly rd/wr/free counters and the DPRAM by a FIFO. -- A 16x40b DPRAM is used for buffering the EventDataSheets (EDS) THE_EDS_BUFFER: eds_buffer_dpram -port map( WRADDRESS => eds_wr_addr, - DATA => eds_data_in, - WRCLOCK => clk_in, - WE => eds_we_in, - WRCLOCKEN => '1', - RDADDRESS => eds_rd_addr, - RDCLOCK => clk_in, - RDCLOCKEN => '1', - RESET => reset_in, - Q => eds_data - ); +port map( + WRADDRESS => eds_wr_addr, + DATA => eds_data_in, + WRCLOCK => clk_in, + WE => eds_we_in, + WRCLOCKEN => '1', + RDADDRESS => eds_rd_addr, + RDCLOCK => clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + Q => eds_data +); -- Are there any EDS to work on? -eds_available_x <= '1' when (eds_wr_addr /= eds_rd_addr) else '0'; +--eds_available_x <= '1' when (eds_wr_addr /= eds_rd_addr) else '0'; +-- epic fail: cut'n'paste error from dhdr_buf.vhd -- Debug signals debug(15 downto 0) <= (others => '0'); diff --git a/src/fifo_16x11.lpc b/src/fifo_16x11.lpc index 49a7243..ece4afe 100644 --- a/src/fifo_16x11.lpc +++ b/src/fifo_16x11.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=FIFO -CoreRevision=4.5 +CoreRevision=4.7 ModuleName=fifo_16x11 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/03/2009 -Time=16:26:00 +Date=03/11/2010 +Time=10:33:40 [Parameters] Verilog=0 @@ -37,8 +37,8 @@ PeMode=Static - Single Threshold PeAssert=10 PeDeassert=12 FullFlg=0 -PfMode=Static - Single Threshold -PfAssert=508 +PfMode=Dynamic - Single Threshold +PfAssert=15 PfDeassert=506 RDataCount=1 EnECC=0 diff --git a/src/fifo_16x11.vhd b/src/fifo_16x11.vhd index 6214fe8..cd5ff67 100644 --- a/src/fifo_16x11.vhd +++ b/src/fifo_16x11.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP1_Build (24) --- Module Version: 4.5 ---X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 11 -depth 16 -no_enable -pe -1 -pf -1 -fill -e +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 4.7 +--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 11 -depth 16 -no_enable -pe -1 -pf -1 -fill -e --- Tue Mar 03 16:26:00 2009 +-- Thu Mar 11 10:33:40 2010 library IEEE; use IEEE.std_logic_1164.all; diff --git a/src/fifo_16x11_tmpl.vhd b/src/fifo_16x11_tmpl.vhd index 5e157c8..ca37eec 100644 --- a/src/fifo_16x11_tmpl.vhd +++ b/src/fifo_16x11_tmpl.vhd @@ -1,6 +1,6 @@ --- VHDL module instantiation generated by SCUBA ispLever_v72_SP1_Build (24) --- Module Version: 4.5 --- Tue Mar 03 16:26:00 2009 +-- VHDL module instantiation generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 4.7 +-- Thu Mar 11 10:33:40 2010 -- parameterized module component declaration component fifo_16x11 diff --git a/src/frmctr_check.vhd b/src/frmctr_check.vhd index 7eaae72..7df04d5 100755 --- a/src/frmctr_check.vhd +++ b/src/frmctr_check.vhd @@ -10,40 +10,41 @@ use work.adcmv3_components.all; -- Only channels with GOODDATA are taken into account. entity frmctr_check is - port( CLK_IN : in std_logic; - GOODDATA_IN : in std_logic_vector(15 downto 0); - FRAMECOUNTER_IN : in std_logic_vector(3 downto 0); - FRM_NR_0_IN : in std_logic_vector(3 downto 0); - FRM_NR_1_IN : in std_logic_vector(3 downto 0); - FRM_NR_2_IN : in std_logic_vector(3 downto 0); - FRM_NR_3_IN : in std_logic_vector(3 downto 0); - FRM_NR_4_IN : in std_logic_vector(3 downto 0); - FRM_NR_5_IN : in std_logic_vector(3 downto 0); - FRM_NR_6_IN : in std_logic_vector(3 downto 0); - FRM_NR_7_IN : in std_logic_vector(3 downto 0); - FRM_NR_8_IN : in std_logic_vector(3 downto 0); - FRM_NR_9_IN : in std_logic_vector(3 downto 0); - FRM_NR_10_IN : in std_logic_vector(3 downto 0); - FRM_NR_11_IN : in std_logic_vector(3 downto 0); - FRM_NR_12_IN : in std_logic_vector(3 downto 0); - FRM_NR_13_IN : in std_logic_vector(3 downto 0); - FRM_NR_14_IN : in std_logic_vector(3 downto 0); - FRM_NR_15_IN : in std_logic_vector(3 downto 0); - FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong - DBG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_IN : in std_logic; + GOODDATA_IN : in std_logic_vector(15 downto 0); + FRAMECOUNTER_IN : in std_logic_vector(3 downto 0); + FRM_NR_0_IN : in std_logic_vector(3 downto 0); + FRM_NR_1_IN : in std_logic_vector(3 downto 0); + FRM_NR_2_IN : in std_logic_vector(3 downto 0); + FRM_NR_3_IN : in std_logic_vector(3 downto 0); + FRM_NR_4_IN : in std_logic_vector(3 downto 0); + FRM_NR_5_IN : in std_logic_vector(3 downto 0); + FRM_NR_6_IN : in std_logic_vector(3 downto 0); + FRM_NR_7_IN : in std_logic_vector(3 downto 0); + FRM_NR_8_IN : in std_logic_vector(3 downto 0); + FRM_NR_9_IN : in std_logic_vector(3 downto 0); + FRM_NR_10_IN : in std_logic_vector(3 downto 0); + FRM_NR_11_IN : in std_logic_vector(3 downto 0); + FRM_NR_12_IN : in std_logic_vector(3 downto 0); + FRM_NR_13_IN : in std_logic_vector(3 downto 0); + FRM_NR_14_IN : in std_logic_vector(3 downto 0); + FRM_NR_15_IN : in std_logic_vector(3 downto 0); + FRC_ERROR_OUT : out std_logic; -- at least one framecounter is wrong + DBG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of frmctr_check is - -- normal signals - signal debug_x : std_logic_vector(15 downto 0); +-- normal signals +signal debug_x : std_logic_vector(15 downto 0); + +signal next_frc_match : std_logic_vector(15 downto 0); +signal frc_match : std_logic_vector(15 downto 0); +signal next_frc_error : std_logic; +signal frc_error : std_logic; - signal next_frc_match : std_logic_vector(15 downto 0); - signal frc_match : std_logic_vector(15 downto 0); - signal next_frc_error : std_logic; - signal frc_error : std_logic; - begin -- Sync process diff --git a/src/i2c_gstart.vhd b/src/i2c_gstart.vhd index ec4d696..6cc4602 100644 --- a/src/i2c_gstart.vhd +++ b/src/i2c_gstart.vhd @@ -7,48 +7,49 @@ library work; use work.adcmv3_components.all; entity I2C_GSTART is -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - START_IN : in std_logic; - DOSTART_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector(7 downto 0); - SDONE_OUT : out std_logic; - SOK_OUT : out std_logic; - SDA_IN : in std_logic; - SCL_IN : in std_logic; - R_SCL_OUT : out std_logic; - S_SCL_OUT : out std_logic; - R_SDA_OUT : out std_logic; - S_SDA_OUT : out std_logic; - BSM_OUT : out std_logic_vector(3 downto 0) - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + DOSTART_IN : in std_logic; + I2C_SPEED_IN : in std_logic_vector(7 downto 0); + SDONE_OUT : out std_logic; + SOK_OUT : out std_logic; + SDA_IN : in std_logic; + SCL_IN : in std_logic; + R_SCL_OUT : out std_logic; + S_SCL_OUT : out std_logic; + R_SDA_OUT : out std_logic; + S_SDA_OUT : out std_logic; + BSM_OUT : out std_logic_vector(3 downto 0) +); end entity; architecture Behavioral of I2C_GSTART is -- Signals - type STATES is (SLEEP,P_SCL,WCTR0,P_SDA,WCTR1,P_CHK,S_CHK0,RS_SDA,S_CHK1,ERROR,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; +type STATES is (SLEEP,P_SCL,WCTR0,P_SDA,WCTR1,P_CHK,S_CHK0,RS_SDA,S_CHK1,ERROR,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; - signal bsm : std_logic_vector(3 downto 0); - signal cctr : std_logic_vector(7 downto 0); -- counter for bit length +signal bsm : std_logic_vector(3 downto 0); +signal cctr : std_logic_vector(7 downto 0); -- counter for bit length - signal cycdone_x : std_logic; - signal cycdone : std_logic; -- one counter period done +signal cycdone_x : std_logic; +signal cycdone : std_logic; -- one counter period done - signal load_cyc_x : std_logic; - signal load_cyc : std_logic; - signal dec_cyc_x : std_logic; - signal dec_cyc : std_logic; - signal sdone_x : std_logic; - signal sdone : std_logic; -- Start/Stop done - signal sok_x : std_logic; - signal sok : std_logic; -- Start/Stop OK +signal load_cyc_x : std_logic; +signal load_cyc : std_logic; +signal dec_cyc_x : std_logic; +signal dec_cyc : std_logic; +signal sdone_x : std_logic; +signal sdone : std_logic; -- Start/Stop done +signal sok_x : std_logic; +signal sok : std_logic; -- Start/Stop OK - signal r_scl : std_logic; - signal s_scl : std_logic; - signal r_sda : std_logic; - signal s_sda : std_logic; +signal r_scl : std_logic; +signal s_scl : std_logic; +signal r_sda : std_logic; +signal s_sda : std_logic; -- Moduls @@ -60,7 +61,7 @@ begin if( rising_edge(clk_in) ) then if( reset_in = '1' ) then cctr <= (others => '0'); - elsif( load_cyc = '1' ) then + elsif( load_cyc = '1' ) then cctr <= i2c_speed_in; elsif( dec_cyc = '1' ) then cctr <= cctr - 1; @@ -103,7 +104,7 @@ begin sdone_x <= '0'; sok_x <= '1'; case CURRENT_STATE is - when SLEEP => if ( (dostart_in = '1') and (start_in = '1') ) then + when SLEEP => if ( (dostart_in = '1') and (start_in = '1') ) then NEXT_STATE <= S_CHK0; -- generate a start condition load_cyc_x <= '1'; elsif( (dostart_in = '1') and (start_in = '0') ) then @@ -112,17 +113,17 @@ begin else NEXT_STATE <= SLEEP; end if; - when P_SCL => NEXT_STATE <= WCTR0; + when P_SCL => NEXT_STATE <= WCTR0; dec_cyc_x <= '1'; - when S_CHK0 => if( (sda_in = '1') and (scl_in = '1') ) then + when S_CHK0 => if( (sda_in = '1') and (scl_in = '1') ) then NEXT_STATE <= RS_SDA; else NEXT_STATE <= ERROR; sok_x <= '0'; end if; - when RS_SDA => NEXT_STATE <= WCTR0; + when RS_SDA => NEXT_STATE <= WCTR0; dec_cyc_x <= '1'; - when WCTR0 => if ( (cycdone = '1') and (start_in = '1') ) then + when WCTR0 => if ( (cycdone = '1') and (start_in = '1') ) then NEXT_STATE <= S_CHK1; elsif( (cycdone = '1') and (start_in = '0') ) then NEXT_STATE <= P_SDA; @@ -131,41 +132,41 @@ begin NEXT_STATE <= WCTR0; dec_cyc_x <= '1'; end if; - when S_CHK1 => if( (sda_in = '0') and (scl_in = '1') ) then + when S_CHK1 => if( (sda_in = '0') and (scl_in = '1') ) then NEXT_STATE <= DONE; else NEXT_STATE <= ERROR; sok_x <= '0'; end if; - when P_SDA => NEXT_STATE <= WCTR1; + when P_SDA => NEXT_STATE <= WCTR1; dec_cyc_x <= '1'; - when WCTR1 => if( (cycdone = '1') ) then + when WCTR1 => if( (cycdone = '1') ) then NEXT_STATE <= P_CHK; else NEXT_STATE <= WCTR1; dec_cyc_x <= '1'; end if; - when P_CHK => if( (sda_in = '1') and (scl_in = '1') ) then + when P_CHK => if( (sda_in = '1') and (scl_in = '1') ) then NEXT_STATE <= DONE; sdone_x <= '1'; else NEXT_STATE <= ERROR; sok_x <= '0'; end if; - when ERROR => if( dostart_in = '0' ) then + when ERROR => if( dostart_in = '0' ) then NEXT_STATE <= SLEEP; else NEXT_STATE <= ERROR; sdone_x <= '1'; sok_x <= '0'; end if; - when DONE => if( dostart_in = '0' ) then + when DONE => if( dostart_in = '0' ) then NEXT_STATE <= SLEEP; else NEXT_STATE <= DONE; sdone_x <= '1'; end if; - when others => NEXT_STATE <= SLEEP; + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; @@ -173,18 +174,18 @@ end process TRANSFORM; DECODE: process(CURRENT_STATE) begin case CURRENT_STATE is - when SLEEP => bsm <= x"0"; - when S_CHK0 => bsm <= x"1"; - when RS_SDA => bsm <= x"2"; - when P_SCL => bsm <= x"3"; - when WCTR0 => bsm <= x"4"; - when S_CHK1 => bsm <= x"5"; - when P_SDA => bsm <= x"6"; - when WCTR1 => bsm <= x"7"; - when P_CHK => bsm <= x"8"; - when DONE => bsm <= x"9"; - when ERROR => bsm <= x"e"; - when others => bsm <= x"f"; + when SLEEP => bsm <= x"0"; + when S_CHK0 => bsm <= x"1"; + when RS_SDA => bsm <= x"2"; + when P_SCL => bsm <= x"3"; + when WCTR0 => bsm <= x"4"; + when S_CHK1 => bsm <= x"5"; + when P_SDA => bsm <= x"6"; + when WCTR1 => bsm <= x"7"; + when P_CHK => bsm <= x"8"; + when DONE => bsm <= x"9"; + when ERROR => bsm <= x"e"; + when others => bsm <= x"f"; end case; end process DECODE; diff --git a/src/i2c_master.vhd b/src/i2c_master.vhd index e843b62..80f197c 100644 --- a/src/i2c_master.vhd +++ b/src/i2c_master.vhd @@ -7,47 +7,48 @@ library work; use work.adcmv3_components.all; entity i2c_master is -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I2C connections - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); end entity; architecture Behavioral of i2c_master is -- Signals - type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - -- slave bus signals - signal slv_busy_x : std_logic; - signal slv_busy : std_logic; - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; - - signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input - signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data - signal reg_busy : std_logic; - - signal status_data : std_logic_vector(31 downto 0); - signal i2c_debug : std_logic_vector(31 downto 0); +type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- slave bus signals +signal slv_busy_x : std_logic; +signal slv_busy : std_logic; +signal slv_ack_x : std_logic; +signal slv_ack : std_logic; +signal store_wr_x : std_logic; +signal store_wr : std_logic; +signal store_rd_x : std_logic; +signal store_rd : std_logic; + +signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input +signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data +signal reg_busy : std_logic; + +signal status_data : std_logic_vector(31 downto 0); +signal i2c_debug : std_logic_vector(31 downto 0); begin @@ -56,26 +57,27 @@ begin --------------------------------------------------------- THE_I2C_SLIM: i2c_slim -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- I2C command / setup - I2C_GO_IN => reg_slv_data_in(31), - ACTION_IN => reg_slv_data_in(30), - I2C_SPEED_IN => reg_slv_data_in(29 downto 24), - I2C_ADR_IN => reg_slv_data_in(23 downto 16), - I2C_CMD_IN => reg_slv_data_in(15 downto 8), - I2C_DW_IN => reg_slv_data_in(7 downto 0), - I2C_DR_OUT => status_data(7 downto 0), - STATUS_OUT => status_data(31 downto 24), - I2C_BUSY_OUT => reg_busy, - -- I2C connections - SDA_IN => sda_in, - SDA_OUT => sda_out, - SCL_IN => scl_in, - SCL_OUT => scl_out, - -- Debug - STAT => i2c_debug - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- I2C command / setup + I2C_GO_IN => reg_slv_data_in(31), + ACTION_IN => reg_slv_data_in(30), + I2C_SPEED_IN => reg_slv_data_in(29 downto 24), + I2C_ADR_IN => reg_slv_data_in(23 downto 16), + I2C_CMD_IN => reg_slv_data_in(15 downto 8), + I2C_DW_IN => reg_slv_data_in(7 downto 0), + I2C_DR_OUT => status_data(7 downto 0), + STATUS_OUT => status_data(31 downto 24), + I2C_BUSY_OUT => reg_busy, + -- I2C connections + SDA_IN => sda_in, + SDA_OUT => sda_out, + SCL_IN => scl_in, + SCL_OUT => scl_out, + -- Debug + STAT => i2c_debug +); status_data(23 downto 21) <= (others => '0'); status_data(20 downto 16) <= i2c_debug(4 downto 0); @@ -116,7 +118,7 @@ begin store_wr_x <= '0'; store_rd_x <= '0'; case CURRENT_STATE is - when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then + when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then NEXT_STATE <= RD_RDY; store_rd_x <= '1'; elsif( (reg_busy = '0') and (slv_write_in = '1') ) then @@ -128,40 +130,40 @@ begin elsif( (reg_busy = '1') and (slv_write_in = '1') ) then NEXT_STATE <= WR_BSY; slv_busy_x <= '1'; - else + else NEXT_STATE <= SLEEP; end if; - when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_RDY => NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; - when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_RDY => NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; - when RD_ACK => if( slv_read_in = '0' ) then + when RD_ACK => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; end if; - when WR_ACK => if( slv_write_in = '0' ) then + when WR_ACK => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; end if; - when RD_BSY => if( slv_read_in = '0' ) then + when RD_BSY => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= RD_BSY; slv_busy_x <= '1'; end if; - when WR_BSY => if( slv_write_in = '0' ) then + when WR_BSY => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= WR_BSY; slv_busy_x <= '1'; end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; diff --git a/src/i2c_sendb.vhd b/src/i2c_sendb.vhd index 42d8187..42e22a9 100644 --- a/src/i2c_sendb.vhd +++ b/src/i2c_sendb.vhd @@ -6,72 +6,73 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL; library work; use work.adcmv3_components.all; -entity I2C_SENDB is -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - DOBYTE_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector( 7 downto 0 ); - I2C_BYTE_IN : in std_logic_vector( 8 downto 0 ); - I2C_BACK_OUT : out std_logic_vector( 8 downto 0 ); - SDA_IN : in std_logic; - R_SDA_OUT : out std_logic; - S_SDA_OUT : out std_logic; --- SCL_IN : in std_logic; - R_SCL_OUT : out std_logic; - S_SCL_OUT : out std_logic; - BDONE_OUT : out std_logic; - BOK_OUT : out std_logic; - BSM_OUT : out std_logic_vector( 3 downto 0 ) - ); +entity i2c_sendb is +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + DOBYTE_IN : in std_logic; + I2C_SPEED_IN : in std_logic_vector( 7 downto 0 ); + I2C_BYTE_IN : in std_logic_vector( 8 downto 0 ); + I2C_BACK_OUT : out std_logic_vector( 8 downto 0 ); + SDA_IN : in std_logic; + R_SDA_OUT : out std_logic; + S_SDA_OUT : out std_logic; +-- SCL_IN : in std_logic; + R_SCL_OUT : out std_logic; + S_SCL_OUT : out std_logic; + BDONE_OUT : out std_logic; + BOK_OUT : out std_logic; + BSM_OUT : out std_logic_vector( 3 downto 0 ) +); end entity; -architecture Behavioral of I2C_SENDB is +architecture Behavioral of i2c_sendb is -- Signals - type STATES is (SLEEP,LCL,WCL,LCH,WCH,FREE,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; +type STATES is (SLEEP,LCL,WCL,LCH,WCH,FREE,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; - signal bsm : std_logic_vector( 3 downto 0 ); +signal bsm : std_logic_vector( 3 downto 0 ); - signal inc_bit_x : std_logic; - signal inc_bit : std_logic; -- increment bit counter for byte to send - signal rst_bit_x : std_logic; - signal rst_bit : std_logic; -- reset bit counter for byte to send - signal load_cyc_x : std_logic; - signal load_cyc : std_logic; -- load cycle counter (SCL length) - signal dec_cyc_x : std_logic; - signal dec_cyc : std_logic; -- decrement cycle counter (SCL length) - signal load_sr_x : std_logic; - signal load_sr : std_logic; -- load output shift register - signal shift_o_x : std_logic; - signal shift_o : std_logic; -- output shift register control - signal shift_i_x : std_logic; - signal shift_i : std_logic; -- input shift register control - signal bdone_x : std_logic; - signal bdone : std_logic; - signal r_scl_x : std_logic; - signal r_scl : std_logic; -- output for SCL - signal s_scl_x : std_logic; - signal s_scl : std_logic; -- output for SCL +signal inc_bit_x : std_logic; +signal inc_bit : std_logic; -- increment bit counter for byte to send +signal rst_bit_x : std_logic; +signal rst_bit : std_logic; -- reset bit counter for byte to send +signal load_cyc_x : std_logic; +signal load_cyc : std_logic; -- load cycle counter (SCL length) +signal dec_cyc_x : std_logic; +signal dec_cyc : std_logic; -- decrement cycle counter (SCL length) +signal load_sr_x : std_logic; +signal load_sr : std_logic; -- load output shift register +signal shift_o_x : std_logic; +signal shift_o : std_logic; -- output shift register control +signal shift_i_x : std_logic; +signal shift_i : std_logic; -- input shift register control +signal bdone_x : std_logic; +signal bdone : std_logic; +signal r_scl_x : std_logic; +signal r_scl : std_logic; -- output for SCL +signal s_scl_x : std_logic; +signal s_scl : std_logic; -- output for SCL - signal bctr : std_logic_vector( 3 downto 0 ); -- bit counter (1...9) - signal cctr : std_logic_vector( 7 downto 0 ); -- counter for bit length - signal bok : std_logic; - signal cycdone : std_logic; -- one counter period done - signal bytedone : std_logic; -- all bits sents - signal in_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte in - signal out_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte out - signal i2c_back : std_logic_vector( 8 downto 0 ); -- shift register for byte in - signal r_sda : std_logic; -- output for SDA - signal s_sda : std_logic; -- output for SDA - signal load : std_logic; -- delay register - signal i2c_d : std_logic; -- auxiliary register +signal bctr : std_logic_vector( 3 downto 0 ); -- bit counter (1...9) +signal cctr : std_logic_vector( 7 downto 0 ); -- counter for bit length +signal bok : std_logic; +signal cycdone : std_logic; -- one counter period done +signal bytedone : std_logic; -- all bits sents +signal in_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte in +signal out_sr : std_logic_vector( 8 downto 0 ); -- shift register for byte out +signal i2c_back : std_logic_vector( 8 downto 0 ); -- shift register for byte in +signal r_sda : std_logic; -- output for SDA +signal s_sda : std_logic; -- output for SDA +signal load : std_logic; -- delay register +signal i2c_d : std_logic; -- auxiliary register -- Moduls begin --- Bit counter (for byte to send) +-- Bit counter (for byte to send) THE_BIT_CTR_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then @@ -94,7 +95,7 @@ begin if( rising_edge(clk_in) ) then if( reset_in = '1' ) then cctr <= (others => '0'); - elsif( load_cyc = '1' ) then + elsif( load_cyc = '1' ) then cctr <= i2c_speed_in; elsif( dec_cyc = '1' ) then cctr <= cctr - 1; @@ -104,7 +105,7 @@ end process THE_CYC_CTR_PROC; -- end of cycle recognition cycdone <= '1' when (cctr = x"00") else '0'; - + -- Bit output THE_BIT_OUT_PROC: process( clk_in ) begin @@ -125,7 +126,7 @@ end process THE_BIT_OUT_PROC; -- Bit input THE_BIT_IN_PROC: process( clk_in ) begin - if( rising_edge(clk_in) ) then + if( rising_edge(clk_in) ) then if ( reset_in = '1' ) then in_sr <= (others => '1'); elsif( shift_o = '1' ) then @@ -199,7 +200,7 @@ begin r_scl_x <= '0'; s_scl_x <= '0'; case CURRENT_STATE is - when SLEEP => if( dobyte_in = '1' ) then + when SLEEP => if( dobyte_in = '1' ) then NEXT_STATE <= LCL; inc_bit_x <= '1'; load_cyc_x <= '1'; @@ -209,9 +210,9 @@ begin NEXT_STATE <= SLEEP; load_sr_x <= '1'; end if; - when LCL => NEXT_STATE <= WCL; + when LCL => NEXT_STATE <= WCL; dec_cyc_x <= '1'; - when WCL => if( cycdone = '1' ) then + when WCL => if( cycdone = '1' ) then NEXT_STATE <= LCH; load_cyc_x <= '1'; s_scl_x <= '1'; @@ -219,9 +220,9 @@ begin NEXT_STATE <= WCL; dec_cyc_x <= '1'; end if; - when LCH => NEXT_STATE <= WCH; + when LCH => NEXT_STATE <= WCH; dec_cyc_x <= '1'; - when WCH => if ( (cycdone = '1') and (bytedone = '0') ) then + when WCH => if ( (cycdone = '1') and (bytedone = '0') ) then NEXT_STATE <= LCL; inc_bit_x <= '1'; load_cyc_x <= '1'; @@ -236,10 +237,10 @@ begin NEXT_STATE <= WCH; dec_cyc_x <= '1'; end if; - when FREE => NEXT_STATE <= DONE; + when FREE => NEXT_STATE <= DONE; rst_bit_x <= '1'; bdone_x <= '1'; - when DONE => if( dobyte_in = '0' ) then + when DONE => if( dobyte_in = '0' ) then NEXT_STATE <= SLEEP; else NEXT_STATE <= DONE; @@ -247,7 +248,7 @@ begin bdone_x <= '1'; end if; -- Just in case... - when others => NEXT_STATE <= SLEEP; + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; @@ -255,15 +256,15 @@ end process TRANSFORM; DECODE: process(CURRENT_STATE) begin case CURRENT_STATE is - when SLEEP => bsm <= x"0"; - when LCL => bsm <= x"1"; - when WCL => bsm <= x"2"; - when LCH => bsm <= x"3"; - when WCH => bsm <= x"4"; - when FREE => bsm <= x"5"; - when DONE => bsm <= x"6"; - when others => bsm <= x"f"; - end case; + when SLEEP => bsm <= x"0"; + when LCL => bsm <= x"1"; + when WCL => bsm <= x"2"; + when LCH => bsm <= x"3"; + when WCH => bsm <= x"4"; + when FREE => bsm <= x"5"; + when DONE => bsm <= x"6"; + when others => bsm <= x"f"; + end case; end process DECODE; -- SCL and SDA output pulses @@ -275,7 +276,7 @@ begin r_sda <= '0'; s_sda <= '0'; else - load <= shift_o; + load <= shift_o; r_sda <= load and not i2c_d; s_sda <= load and i2c_d; end if; @@ -293,7 +294,7 @@ i2c_back_out <= i2c_back; bdone_out <= bdone; bok_out <= bok; --- Debugging +-- Debugging bsm_out <= bsm; end Behavioral; diff --git a/src/i2c_slim.vhd b/src/i2c_slim.vhd index 5c347ea..7ca5680 100644 --- a/src/i2c_slim.vhd +++ b/src/i2c_slim.vhd @@ -10,85 +10,86 @@ use work.adcmv3_components.all; -- REMARK: this is not a bug, but a feature.... entity i2c_slim is -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- I2C command / setup - I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions - ACTION_IN : in std_logic; -- '0' -> write, '1' -> read - I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined) - I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored) - I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte) - I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command - I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command - STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits - I2C_BUSY_OUT : out std_logic; - -- I2C connections - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; - -- Debug - STAT : out std_logic_vector(31 downto 0) - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- I2C command / setup + I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions + ACTION_IN : in std_logic; -- '0' -> write, '1' -> read + I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined) + I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte) + I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command + I2C_DR_OUT : out std_logic_vector( 7 downto 0 ); -- data word from read command + STATUS_OUT : out std_logic_vector( 7 downto 0 ); -- status and error bits + I2C_BUSY_OUT : out std_logic; + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- Debug + STAT : out std_logic_vector(31 downto 0) +); end i2c_slim; architecture Behavioral of i2c_slim is -- Signals - type STATES is (SLEEP,LOADA,GSTART,SENDA,LOADC,SENDC,LOADD,SENDD,GSTOP,INC, - E_START,E_ADDR,E_CMD,E_WD,E_RSTART,E_RADDR,DONE,FAILED,CLRERR); - signal CURRENT_STATE, NEXT_STATE: STATES; - - signal bsm : std_logic_vector( 4 downto 0 ); - signal phase : std_logic; -- '0' => first phase, '1' => second phase of read cycle +type STATES is (SLEEP,LOADA,GSTART,SENDA,LOADC,SENDC,LOADD,SENDD,GSTOP,INC, + E_START,E_ADDR,E_CMD,E_WD,E_RSTART,E_RADDR,DONE,FAILED,CLRERR); +signal CURRENT_STATE, NEXT_STATE: STATES; - signal start_x : std_logic; - signal start : std_logic; -- '0' => generate STOP, '1' => generate START - signal dostart_x : std_logic; - signal dostart : std_logic; -- trigger the GenStart module - signal dobyte_x : std_logic; - signal dobyte : std_logic; -- trigger the ByteSend module - signal i2c_done_x : std_logic; - signal i2c_done : std_logic; -- acknowledge signal to the outside world - signal running_x : std_logic; - signal running : std_logic; -- legacy +signal bsm : std_logic_vector( 4 downto 0 ); +signal phase : std_logic; -- '0' => first phase, '1' => second phase of read cycle - signal load_a_x : std_logic; - signal load_a : std_logic; - signal load_c_x : std_logic; - signal load_c : std_logic; - signal load_d_x : std_logic; - signal load_d : std_logic; +signal start_x : std_logic; +signal start : std_logic; -- '0' => generate STOP, '1' => generate START +signal dostart_x : std_logic; +signal dostart : std_logic; -- trigger the GenStart module +signal dobyte_x : std_logic; +signal dobyte : std_logic; -- trigger the ByteSend module +signal i2c_done_x : std_logic; +signal i2c_done : std_logic; -- acknowledge signal to the outside world +signal running_x : std_logic; +signal running : std_logic; -- legacy - signal sdone : std_logic; -- acknowledge signal from GenStart module - signal sok : std_logic; -- status signal from GenStart module - signal bdone : std_logic; -- acknowledge signal from SendByte module - signal bok : std_logic; -- status signal from SendByte module - signal e_sf : std_logic; -- Start failed - signal e_anak : std_logic; -- Adress byte NAK - signal e_cnak : std_logic; -- Command byte NAK - signal e_dnak : std_logic; -- Data byte NAK - signal e_rsf : std_logic; -- Repeated Start failed - signal e_ranak : std_logic; -- Repeated Adress NAK - signal i2c_byte : std_logic_vector( 8 downto 0 ); - signal i2c_dr : std_logic_vector( 8 downto 0 ); +signal load_a_x : std_logic; +signal load_a : std_logic; +signal load_c_x : std_logic; +signal load_c : std_logic; +signal load_d_x : std_logic; +signal load_d : std_logic; - signal s_scl : std_logic; - signal r_scl : std_logic; - signal s_sda : std_logic; - signal r_sda : std_logic; - signal r_scl_gs : std_logic; - signal s_scl_gs : std_logic; - signal r_sda_gs : std_logic; - signal s_sda_gs : std_logic; - signal r_scl_sb : std_logic; - signal s_scl_sb : std_logic; - signal r_sda_sb : std_logic; - signal s_sda_sb : std_logic; +signal sdone : std_logic; -- acknowledge signal from GenStart module +signal sok : std_logic; -- status signal from GenStart module +signal bdone : std_logic; -- acknowledge signal from SendByte module +signal bok : std_logic; -- status signal from SendByte module +signal e_sf : std_logic; -- Start failed +signal e_anak : std_logic; -- Adress byte NAK +signal e_cnak : std_logic; -- Command byte NAK +signal e_dnak : std_logic; -- Data byte NAK +signal e_rsf : std_logic; -- Repeated Start failed +signal e_ranak : std_logic; -- Repeated Adress NAK +signal i2c_byte : std_logic_vector( 8 downto 0 ); +signal i2c_dr : std_logic_vector( 8 downto 0 ); - signal gs_debug : std_logic_vector(3 downto 0); +signal s_scl : std_logic; +signal r_scl : std_logic; +signal s_sda : std_logic; +signal r_sda : std_logic; +signal r_scl_gs : std_logic; +signal s_scl_gs : std_logic; +signal r_sda_gs : std_logic; +signal s_sda_gs : std_logic; +signal r_scl_sb : std_logic; +signal s_scl_sb : std_logic; +signal r_sda_sb : std_logic; +signal s_sda_sb : std_logic; - signal i2c_speed : std_logic_vector(7 downto 0); +signal gs_debug : std_logic_vector(3 downto 0); + +signal i2c_speed : std_logic_vector(7 downto 0); begin @@ -150,18 +151,18 @@ begin load_c_x <= '0'; load_d_x <= '0'; case CURRENT_STATE is - when SLEEP => if( i2c_go_in = '1' ) then + when SLEEP => if( i2c_go_in = '1' ) then NEXT_STATE <= CLRERR; else NEXT_STATE <= SLEEP; running_x <= '0'; end if; - when CLRERR => NEXT_STATE <= LOADA; + when CLRERR => NEXT_STATE <= LOADA; load_a_x <= '1'; - when LOADA => NEXT_STATE <= GSTART; + when LOADA => NEXT_STATE <= GSTART; start_x <= '1'; dostart_x <= '1'; - when GSTART => if ( (sdone = '1') and (sok = '1') ) then + when GSTART => if ( (sdone = '1') and (sok = '1') ) then NEXT_STATE <= SENDA; dobyte_x <= '1'; elsif( (sdone = '1') and (sok = '0') and (phase = '0') ) then @@ -173,18 +174,18 @@ begin start_x <= '1'; dostart_x <= '1'; end if; - when E_START => NEXT_STATE <= FAILED; + when E_START => NEXT_STATE <= FAILED; dostart_x <= '1'; - when E_RSTART => NEXT_STATE <= FAILED; + when E_RSTART => NEXT_STATE <= FAILED; dostart_x <= '1'; - when SENDA => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then + when SENDA => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then NEXT_STATE <= LOADC; -- I2C write - load_c_x <= '1'; + load_c_x <= '1'; elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '0') ) then - NEXT_STATE <= LOADC; -- I2C read, send register address + NEXT_STATE <= LOADC; -- I2C read, send register address load_c_x <= '1'; elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '1') ) then - NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte + NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte load_d_x <= '1'; elsif( (bdone = '1') and (bok = '0') and (phase = '0') ) then NEXT_STATE <= E_ADDR; -- first address phase failed @@ -194,13 +195,13 @@ begin NEXT_STATE <= SENDA; dobyte_x <= '1'; end if; - when E_ADDR => NEXT_STATE <= FAILED; + when E_ADDR => NEXT_STATE <= FAILED; dostart_x <= '1'; - when E_RADDR => NEXT_STATE <= FAILED; + when E_RADDR => NEXT_STATE <= FAILED; dostart_x <= '1'; - when LOADC => NEXT_STATE <= SENDC; --- dobyte_x <= '1'; - when SENDC => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then + when LOADC => NEXT_STATE <= SENDC; +-- dobyte_x <= '1'; + when SENDC => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then NEXT_STATE <= LOADD; -- I2C write, prepare data load_d_x <= '1'; elsif( (bdone = '1') and (bok = '1') and (action_in = '1') ) then @@ -211,25 +212,25 @@ begin else NEXT_STATE <= SENDC; dobyte_x <= '1'; - end if; - when E_CMD => NEXT_STATE <= FAILED; + end if; + when E_CMD => NEXT_STATE <= FAILED; dostart_x <= '1'; - when LOADD => NEXT_STATE <= SENDD; - when SENDD => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then - NEXT_STATE <= GSTOP; -- I2C write, data phase failed + when LOADD => NEXT_STATE <= SENDD; + when SENDD => if ( (bdone = '1') and (bok = '1') and (action_in = '0') ) then + NEXT_STATE <= GSTOP; -- I2C write, data phase failed dostart_x <= '1'; elsif( (bdone = '1') and (action_in = '1') ) then NEXT_STATE <= GSTOP; -- I2C read, data phase - dostart_x <= '1'; + dostart_x <= '1'; elsif( (bdone = '1') and (bok = '0') and (action_in = '0') ) then NEXT_STATE <= E_WD; -- I2C write, data phase failed else NEXT_STATE <= SENDD; dobyte_x <= '1'; end if; - when E_WD => NEXT_STATE <= FAILED; + when E_WD => NEXT_STATE <= FAILED; dostart_x <= '1'; - when GSTOP => if ( (sdone = '1') and (action_in = '0') ) then + when GSTOP => if ( (sdone = '1') and (action_in = '0') ) then NEXT_STATE <= DONE; elsif( (sdone = '1') and (action_in = '1') and (phase = '1') ) then NEXT_STATE <= DONE; @@ -239,9 +240,9 @@ begin NEXT_STATE <= GSTOP; dostart_x <= '1'; end if; - when INC => NEXT_STATE <= LOADA; + when INC => NEXT_STATE <= LOADA; load_a_x <= '1'; - when FAILED => if( sdone = '1' ) then + when FAILED => if( sdone = '1' ) then NEXT_STATE <= DONE; i2c_done_x <= '1'; running_x <= '0'; @@ -249,7 +250,7 @@ begin NEXT_STATE <= FAILED; dostart_x <= '1'; end if; - when DONE => if( i2c_go_in = '1' ) then + when DONE => if( i2c_go_in = '1' ) then NEXT_STATE <= DONE; i2c_done_x <= '1'; running_x <= '0'; @@ -257,7 +258,7 @@ begin NEXT_STATE <= SLEEP; end if; -- Just in case... - when others => NEXT_STATE <= SLEEP; + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; @@ -265,27 +266,27 @@ end process TRANSFORM; DECODE: process(CURRENT_STATE) begin case CURRENT_STATE is - when SLEEP => bsm <= b"00000"; -- 00 - when CLRERR => bsm <= b"01100"; -- 0c - when LOADA => bsm <= b"00001"; -- 01 - when GSTART => bsm <= b"00010"; -- 02 - when SENDA => bsm <= b"00011"; -- 03 - when LOADC => bsm <= b"00100"; -- 04 - when SENDC => bsm <= b"00101"; -- 05 - when LOADD => bsm <= b"00110"; -- 06 - when SENDD => bsm <= b"00111"; -- 07 - when GSTOP => bsm <= b"01000"; -- 08 - when INC => bsm <= b"01001"; -- 09 - when FAILED => bsm <= b"01010"; -- 0a - when DONE => bsm <= b"01011"; -- 0b - when E_START => bsm <= b"10000"; -- 10 - when E_RSTART => bsm <= b"10001"; -- 11 - when E_ADDR => bsm <= b"10010"; -- 12 - when E_RADDR => bsm <= b"10011"; -- 13 - when E_CMD => bsm <= b"10100"; -- 14 - when E_WD => bsm <= b"10101"; -- 15 - when others => bsm <= b"11111"; -- 1f - end case; + when SLEEP => bsm <= b"00000"; -- 00 + when CLRERR => bsm <= b"01100"; -- 0c + when LOADA => bsm <= b"00001"; -- 01 + when GSTART => bsm <= b"00010"; -- 02 + when SENDA => bsm <= b"00011"; -- 03 + when LOADC => bsm <= b"00100"; -- 04 + when SENDC => bsm <= b"00101"; -- 05 + when LOADD => bsm <= b"00110"; -- 06 + when SENDD => bsm <= b"00111"; -- 07 + when GSTOP => bsm <= b"01000"; -- 08 + when INC => bsm <= b"01001"; -- 09 + when FAILED => bsm <= b"01010"; -- 0a + when DONE => bsm <= b"01011"; -- 0b + when E_START => bsm <= b"10000"; -- 10 + when E_RSTART => bsm <= b"10001"; -- 11 + when E_ADDR => bsm <= b"10010"; -- 12 + when E_RADDR => bsm <= b"10011"; -- 13 + when E_CMD => bsm <= b"10100"; -- 14 + when E_WD => bsm <= b"10101"; -- 15 + when others => bsm <= b"11111"; -- 1f + end case; end process DECODE; -- We need to load different data sets @@ -313,40 +314,42 @@ end process LOAD_DATA_PROC; -- The SendByte module THE_I2C_SENDB: I2C_SENDB -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - DOBYTE_IN => dobyte, - I2C_SPEED_IN => i2c_speed, - I2C_BYTE_IN => i2c_byte, - I2C_BACK_OUT => i2c_dr, - SDA_IN => sda_in, - R_SDA_OUT => r_sda_sb, - S_SDA_OUT => s_sda_sb, --- SCL_IN => scl_in, - R_SCL_OUT => r_scl_sb, - S_SCL_OUT => s_scl_sb, - BDONE_OUT => bdone, - BOK_OUT => bok, - BSM_OUT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + DOBYTE_IN => dobyte, + I2C_SPEED_IN => i2c_speed, + I2C_BYTE_IN => i2c_byte, + I2C_BACK_OUT => i2c_dr, + SDA_IN => sda_in, + R_SDA_OUT => r_sda_sb, + S_SDA_OUT => s_sda_sb, +-- SCL_IN => scl_in, + R_SCL_OUT => r_scl_sb, + S_SCL_OUT => s_scl_sb, + BDONE_OUT => bdone, + BOK_OUT => bok, + BSM_OUT => open +); -- The GenStart module THE_I2C_GSTART: I2C_GSTART -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - START_IN => start, - DOSTART_IN => dostart, - I2C_SPEED_IN => i2c_speed, - SDONE_OUT => sdone, - SOK_OUT => sok, - SDA_IN => sda_in, - SCL_IN => scl_in, - R_SCL_OUT => r_scl_gs, - S_SCL_OUT => s_scl_gs, - R_SDA_OUT => r_sda_gs, - S_SDA_OUT => s_sda_gs, - BSM_OUT => gs_debug --open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => start, + DOSTART_IN => dostart, + I2C_SPEED_IN => i2c_speed, + SDONE_OUT => sdone, + SOK_OUT => sok, + SDA_IN => sda_in, + SCL_IN => scl_in, + R_SCL_OUT => r_scl_gs, + S_SCL_OUT => s_scl_gs, + R_SDA_OUT => r_sda_gs, + S_SDA_OUT => s_sda_gs, + BSM_OUT => gs_debug --open +); r_scl <= r_scl_gs or r_scl_sb; s_scl <= s_scl_gs or s_scl_sb; @@ -377,31 +380,31 @@ THE_ERR_REG_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then if( reset_in = '1' ) then - e_sf <= '0'; - e_anak <= '0'; - e_cnak <= '0'; - e_dnak <= '0'; - e_rsf <= '0'; - e_ranak <= '0'; + e_sf <= '0'; + e_anak <= '0'; + e_cnak <= '0'; + e_dnak <= '0'; + e_rsf <= '0'; + e_ranak <= '0'; elsif( CURRENT_STATE = CLRERR ) then - e_sf <= '0'; - e_anak <= '0'; - e_cnak <= '0'; - e_dnak <= '0'; - e_rsf <= '0'; - e_ranak <= '0'; + e_sf <= '0'; + e_anak <= '0'; + e_cnak <= '0'; + e_dnak <= '0'; + e_rsf <= '0'; + e_ranak <= '0'; elsif( CURRENT_STATE = E_START ) then - e_sf <= '1'; + e_sf <= '1'; elsif( CURRENT_STATE = E_RSTART ) then - e_rsf <= '1'; + e_rsf <= '1'; elsif( CURRENT_STATE = E_ADDR ) then - e_anak <= '1'; + e_anak <= '1'; elsif( CURRENT_STATE = E_RADDR ) then - e_ranak <= '1'; + e_ranak <= '1'; elsif( CURRENT_STATE = E_CMD ) then - e_cnak <= '1'; + e_cnak <= '1'; elsif( CURRENT_STATE = E_WD ) then - e_dnak <= '1'; + e_dnak <= '1'; end if; end if; end process THE_ERR_REG_PROC; @@ -415,8 +418,8 @@ status_out(2) <= e_cnak; status_out(1) <= e_anak; status_out(0) <= e_sf; --- Outputs -i2c_dr_out <= i2c_dr(8 downto 1); +-- Outputs +i2c_dr_out <= i2c_dr(8 downto 1); i2c_busy_out <= running; -- Debug stuff diff --git a/src/ipu_fifo_stage.vhd b/src/ipu_fifo_stage.vhd index 1ef4bd4..fcc8d9a 100644 --- a/src/ipu_fifo_stage.vhd +++ b/src/ipu_fifo_stage.vhd @@ -9,138 +9,149 @@ use work.adcmv3_components.all; -- Missing: FIFO buffer handling, full / empty checks entity ipu_fifo_stage is - port( CLK_IN : in std_logic; -- 100MHz local clock - RESET_IN : in std_logic; -- synchronous reset - -- Slow control signals - SECTOR_IN : in std_logic_vector(2 downto 0); - MODULE_IN : in std_logic_vector(2 downto 0); - -- IPU channel connections - IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag - IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information - IPU_START_READOUT_IN : in std_logic; -- gimme data! - IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR - IPU_DATAREADY_OUT : out std_logic; -- data is valid - IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM - IPU_READ_IN : in std_logic; -- read strobe, low every second cycle - IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) - IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern - LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter - -- DHDR buffer input - DHDR_DATA_IN : in std_logic_vector(31 downto 0); - DHDR_LENGTH_IN : in std_logic_vector(15 downto 0); - DHDR_STORE_IN : in std_logic; - DHDR_BUF_FULL_OUT : out std_logic; - -- processed data input - FIFO_START_IN : in std_logic; - FIFO_0_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_1_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_2_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_3_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_4_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_5_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_6_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_7_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_8_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_9_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_10_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_11_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_12_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_13_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_14_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_15_DATA_IN : in std_logic_vector(39 downto 0); - FIFO_WE_IN : in std_logic_vector(15 downto 0); - FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs - -- Debug signals - DBG_BSM_OUT : out std_logic_vector(7 downto 0); - DBG_OUT : out std_logic_vector(63 downto 0) - ); +port( + CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control signals + SECTOR_IN : in std_logic_vector(2 downto 0); + MODULE_IN : in std_logic_vector(2 downto 0); + -- IPU channel connections + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_IN : in std_logic; -- gimme data! + IPU_DATA_OUT : out std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_OUT : out std_logic; -- data is valid + IPU_READOUT_FINISHED_OUT : out std_logic; -- no more data, end transfer, send TRM + IPU_READ_IN : in std_logic; -- read strobe, low every second cycle + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- error pattern + LVL2_COUNTER_OUT : out std_logic_vector(15 downto 0); -- local IPU cycle counter + -- DHDR buffer input + DHDR_DATA_IN : in std_logic_vector(31 downto 0); + DHDR_LENGTH_IN : in std_logic_vector(15 downto 0); + DHDR_STORE_IN : in std_logic; + DHDR_BUF_FULL_OUT : out std_logic; + -- processed data input + FIFO_START_IN : in std_logic; + FIFO_SPACE_REQ_IN : in std_logic_vector(11 downto 0); + FIFO_0_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_1_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_2_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_3_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_4_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_5_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_6_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_7_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_8_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_9_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_10_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_11_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_12_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_13_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_14_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_15_DATA_IN : in std_logic_vector(39 downto 0); + FIFO_WE_IN : in std_logic_vector(15 downto 0); + FIFO_DONE_IN : in std_logic; -- write level information into small FIFOs + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(63 downto 0) +); end; architecture behavioral of ipu_fifo_stage is - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of behavioral : architecture is "IPU_FIFO_STAGE_group"; - - -- state machine definitions - type STATES is (SLEEP,RDLF,GETFD,DELH,WHDR,GETD,WAITD,WAITDL,DEL0,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - -- signals - signal debug : std_logic_vector(63 downto 0); - signal bsm_x : std_logic_vector(7 downto 0); - signal next_trgnum_match : std_logic; - signal trgnum_match : std_logic; - - signal dhdr_fifo_in : std_logic_vector(47 downto 0); - signal dhdr_fifo_out : std_logic_vector(47 downto 0); - signal dhdr_avail : std_logic; - signal next_todo_list : std_logic_vector(15 downto 0); - signal todo_list : std_logic_vector(15 downto 0); - signal next_fifo_sel : std_logic_vector(4 downto 0); - signal fifo_sel : std_logic_vector(4 downto 0); - signal next_sel_fifo : std_logic_vector(15 downto 0); - signal sel_fifo : std_logic_vector(15 downto 0); - - signal comb_rd_dfifo : std_logic_vector(15 downto 0); - signal comb_st_data : std_logic_vector(15 downto 0); - signal comb_ack_todo : std_logic; - - signal ipu_out_data : std_logic_vector(31 downto 0); - - -- state machine signals - signal next_rd_lfifo : std_logic; - signal rd_lfifo : std_logic; -- read current LENGTH_FIFO information (as well as LockAtMe bit) - signal next_dataready : std_logic; - signal dataready : std_logic; -- data word is available - signal next_set_hdr : std_logic; - signal set_hdr : std_logic; -- store DHDR in output register - signal next_set_data : std_logic; - signal set_data : std_logic; -- store DATA from current DATA FIFO in output register - signal next_ld_todo : std_logic; - signal ld_todo : std_logic; -- load initial TODO list - signal next_ack_todo : std_logic; - signal ack_todo : std_logic; -- remove current entry from TODO list - signal next_finished : std_logic; - signal finished : std_logic; -- readout is finished - - -- generate needs arrays... - type fifo_data_t is array (0 to 15) of std_logic_vector(26 downto 0); - signal fifo_in_data : fifo_data_t; - signal fifo_out_data : fifo_data_t; - type fifo_count_t is array (0 to 15) of std_logic_vector(10 downto 0); - signal fifo_in_count : fifo_count_t; - type fifo_todo_t is array (0 to 15) of std_logic_vector(9 downto 0); - signal fifo_todo : fifo_todo_t; - type fifo_ldata_t is array (0 to 15) of std_logic_vector(10 downto 0); - signal fifo_ldata : fifo_ldata_t; - type fifo_wcnt_t is array (0 to 15) of std_logic_vector(11 downto 0); - signal fifo_wcnt : fifo_wcnt_t; - signal fifo_data_free : fifo_wcnt_t; +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of behavioral : architecture is "IPU_FIFO_STAGE_group"; + +-- state machine definitions +type STATES is (SLEEP,RDLF,GETFD,DELH,WHDR,GETD,WAITD,WAITDL,DEL0,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- signals +signal debug : std_logic_vector(63 downto 0); +signal bsm_x : std_logic_vector(7 downto 0); +signal next_trgnum_match : std_logic; +signal trgnum_match : std_logic; + +signal dhdr_fifo_in : std_logic_vector(47 downto 0); +signal dhdr_fifo_out : std_logic_vector(47 downto 0); +signal dhdr_avail : std_logic; +signal next_todo_list : std_logic_vector(15 downto 0); +signal todo_list : std_logic_vector(15 downto 0); +signal next_fifo_sel : std_logic_vector(4 downto 0); +signal fifo_sel : std_logic_vector(4 downto 0); +signal next_sel_fifo : std_logic_vector(15 downto 0); +signal sel_fifo : std_logic_vector(15 downto 0); + +signal comb_rd_dfifo : std_logic_vector(15 downto 0); +signal comb_st_data : std_logic_vector(15 downto 0); +signal comb_ack_todo : std_logic; + +signal ipu_out_data : std_logic_vector(31 downto 0); + +-- state machine signals +signal next_rd_lfifo : std_logic; +signal rd_lfifo : std_logic; -- read current LENGTH_FIFO information (as well as LockAtMe bit) +signal next_dataready : std_logic; +signal dataready : std_logic; -- data word is available +signal next_set_hdr : std_logic; +signal set_hdr : std_logic; -- store DHDR in output register +signal next_set_data : std_logic; +signal set_data : std_logic; -- store DATA from current DATA FIFO in output register +signal next_ld_todo : std_logic; +signal ld_todo : std_logic; -- load initial TODO list +signal next_ack_todo : std_logic; +signal ack_todo : std_logic; -- remove current entry from TODO list +signal next_finished : std_logic; +signal finished : std_logic; -- readout is finished +signal next_preload : std_logic; +signal preload : std_logic; -- read first data word from DATA FIFOs + +-- generate needs arrays... +type fifo_data_t is array (0 to 15) of std_logic_vector(26 downto 0); +signal fifo_in_data : fifo_data_t; +signal fifo_out_data : fifo_data_t; +type fifo_count_t is array (0 to 15) of std_logic_vector(10 downto 0); +signal fifo_in_count : fifo_count_t; +type fifo_todo_t is array (0 to 15) of std_logic_vector(9 downto 0); +signal fifo_todo : fifo_todo_t; +type fifo_ldata_t is array (0 to 15) of std_logic_vector(10 downto 0); +signal fifo_ldata : fifo_ldata_t; +type fifo_wcnt_t is array (0 to 15) of std_logic_vector(11 downto 0); +signal fifo_wcnt : fifo_wcnt_t; +signal fifo_data_free : fifo_wcnt_t; +type fifo_lunused_t is array (0 to 15) of std_logic_vector(6 downto 0); +signal fifo_lunused : fifo_lunused_t; + +signal dfifo_available : std_logic_vector(15 downto 0); + +signal lfifo_empty : std_logic_vector(15 downto 0); +signal lfifo_full : std_logic_vector(15 downto 0); + +signal next_fifo_done : std_logic_vector(15 downto 0); +signal fifo_done : std_logic_vector(15 downto 0); +signal next_fifo_last : std_logic; +signal fifo_last : std_logic; + +signal my_trg_number : std_logic_vector(31 downto 0); -- just for checking! + +signal old_apv_num : std_logic_vector(3 downto 0); +signal new_apv_num : std_logic_vector(3 downto 0); + +signal cyclectr : std_logic_vector(15 downto 0); -- cycle counter + +signal next_dhdr_buf_full : std_logic; +signal dhdr_buf_full : std_logic; - - signal next_fifo_done : std_logic_vector(15 downto 0); - signal fifo_done : std_logic_vector(15 downto 0); - signal next_fifo_last : std_logic; - signal fifo_last : std_logic; - - signal my_trg_number : std_logic_vector(31 downto 0); -- just for checking! - - signal old_apv_num : std_logic_vector(3 downto 0); - signal new_apv_num : std_logic_vector(3 downto 0); - - signal cyclectr : std_logic_vector(15 downto 0); -- cycle counter - - signal dhdr_buf_full : std_logic; - begin --------------------------------------------------------------------------- -- Statemachine --------------------------------------------------------------------------- -- state registers -STATE_MEM: process( clk_in ) +STATE_MEM: process( clk_in ) begin if( rising_edge(clk_in) ) then if( reset_in = '1' ) then @@ -151,6 +162,7 @@ begin set_data <= '0'; ld_todo <= '0'; ack_todo <= '0'; + preload <= '0'; finished <= '0'; else CURRENT_STATE <= NEXT_STATE; @@ -160,6 +172,7 @@ begin set_data <= next_set_data; ld_todo <= next_ld_todo; ack_todo <= next_ack_todo; + preload <= next_preload; finished <= next_finished; end if; end if; @@ -175,21 +188,23 @@ begin next_set_data <= '0'; next_ld_todo <= '0'; next_ack_todo <= '0'; + next_preload <= '0'; next_finished <= '0'; case CURRENT_STATE is - when SLEEP => if( (dhdr_avail = '1') and (ipu_start_readout_in = '1') ) then + when SLEEP => if( (dhdr_avail = '1') and (ipu_start_readout_in = '1') ) then NEXT_STATE <= RDLF; next_rd_lfifo <= '1'; else NEXT_STATE <= SLEEP; end if; - when RDLF => NEXT_STATE <= GETFD; + when RDLF => NEXT_STATE <= GETFD; next_set_hdr <= '1'; next_ld_todo <= '1'; - when GETFD => NEXT_STATE <= DELH; - when DELH => NEXT_STATE <= WHDR; + when GETFD => NEXT_STATE <= DELH; + next_preload <= '1'; + when DELH => NEXT_STATE <= WHDR; next_dataready <= '1'; - when WHDR => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then + when WHDR => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then NEXT_STATE <= GETD; -- there are datawords to send next_set_data <= '1'; next_ack_todo <= '1'; @@ -200,22 +215,22 @@ begin NEXT_STATE <= WHDR; next_dataready <= '1'; end if; - when GETD => if( fifo_last = '1' ) then + when GETD => if( fifo_last = '1' ) then NEXT_STATE <= DEL0; - else + else NEXT_STATE <= WAITD; next_dataready <= '1'; end if; - when WAITD => if( ipu_read_in = '1' ) then + when WAITD => if( ipu_read_in = '1' ) then NEXT_STATE <= GETD; next_set_data <= '1'; else NEXT_STATE <= WAITD; next_dataready <= '1'; end if; - when DEL0 => NEXT_STATE <= WAITDL; + when DEL0 => NEXT_STATE <= WAITDL; next_dataready <= '1'; - when WAITDL => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then + when WAITDL => if ( (ipu_read_in = '1') and (fifo_sel(4) = '0') ) then NEXT_STATE <= GETD; next_set_data <= '1'; next_ack_todo <= '1'; @@ -226,13 +241,13 @@ begin NEXT_STATE <= WAITDL; next_dataready <= '1'; end if; - when DONE => if( ipu_start_readout_in = '0' ) then + when DONE => if( ipu_start_readout_in = '0' ) then NEXT_STATE <= SLEEP; else NEXT_STATE <= DONE; end if; - when others => NEXT_STATE <= SLEEP; + when others => NEXT_STATE <= SLEEP; end case; end process STATE_TRANSFORM; @@ -244,96 +259,122 @@ ipu_readout_finished_out <= finished; ipu_length_out <= dhdr_fifo_out(47 downto 32); -- IPU error pattern: [24] => trigger tag mismatch -ipu_error_pattern_out(31 downto 25) <= (others => '0'); -ipu_error_pattern_out(24) <= not trgnum_match; -ipu_error_pattern_out(23 downto 0) <= (others => '0'); +ipu_error_pattern_out(31 downto 24) <= (others => '0'); +ipu_error_pattern_out(23) <= '0'; -- "single broken event" +ipu_error_pattern_out(23) <= '0'; -- "severe problem" +ipu_error_pattern_out(21) <= '0'; -- "partially not found" +ipu_error_pattern_out(20) <= not trgnum_match; -- "not found" +ipu_error_pattern_out(19 downto 0) <= (others => '0'); -- state decoding (ONLY FOR DEBUGGING!) STATE_DECODE: process( CURRENT_STATE ) begin case CURRENT_STATE is - when SLEEP => bsm_x <= x"00"; - when RDLF => bsm_x <= x"01"; - when GETFD => bsm_x <= x"02"; - when DELH => bsm_x <= x"03"; - when WHDR => bsm_x <= x"04"; - when GETD => bsm_x <= x"05"; - when WAITD => bsm_x <= x"06"; - when WAITDL => bsm_x <= x"07"; - when DEL0 => bsm_x <= x"08"; - when DONE => bsm_x <= x"09"; - when others => bsm_x <= x"ff"; + when SLEEP => bsm_x <= x"00"; + when RDLF => bsm_x <= x"01"; + when GETFD => bsm_x <= x"02"; + when DELH => bsm_x <= x"03"; + when WHDR => bsm_x <= x"04"; + when GETD => bsm_x <= x"05"; + when WAITD => bsm_x <= x"06"; + when WAITDL => bsm_x <= x"07"; + when DEL0 => bsm_x <= x"08"; + when DONE => bsm_x <= x"09"; + when others => bsm_x <= x"ff"; end case; end process STATE_DECODE; --------------------------------------------------------------------------- -- Aliasing the data streams --------------------------------------------------------------------------- -fifo_in_data(0) <= fifo_0_data_in(26 downto 0); fifo_in_count(0) <= fifo_0_data_in(37 downto 27); -fifo_in_data(1) <= fifo_1_data_in(26 downto 0); fifo_in_count(1) <= fifo_1_data_in(37 downto 27); -fifo_in_data(2) <= fifo_2_data_in(26 downto 0); fifo_in_count(2) <= fifo_2_data_in(37 downto 27); -fifo_in_data(3) <= fifo_3_data_in(26 downto 0); fifo_in_count(3) <= fifo_3_data_in(37 downto 27); -fifo_in_data(4) <= fifo_4_data_in(26 downto 0); fifo_in_count(4) <= fifo_4_data_in(37 downto 27); -fifo_in_data(5) <= fifo_5_data_in(26 downto 0); fifo_in_count(5) <= fifo_5_data_in(37 downto 27); -fifo_in_data(6) <= fifo_6_data_in(26 downto 0); fifo_in_count(6) <= fifo_6_data_in(37 downto 27); -fifo_in_data(7) <= fifo_7_data_in(26 downto 0); fifo_in_count(7) <= fifo_7_data_in(37 downto 27); -fifo_in_data(8) <= fifo_8_data_in(26 downto 0); fifo_in_count(8) <= fifo_8_data_in(37 downto 27); -fifo_in_data(9) <= fifo_9_data_in(26 downto 0); fifo_in_count(9) <= fifo_9_data_in(37 downto 27); -fifo_in_data(10) <= fifo_10_data_in(26 downto 0); fifo_in_count(10) <= fifo_10_data_in(37 downto 27); -fifo_in_data(11) <= fifo_11_data_in(26 downto 0); fifo_in_count(11) <= fifo_11_data_in(37 downto 27); -fifo_in_data(12) <= fifo_12_data_in(26 downto 0); fifo_in_count(12) <= fifo_12_data_in(37 downto 27); -fifo_in_data(13) <= fifo_13_data_in(26 downto 0); fifo_in_count(13) <= fifo_13_data_in(37 downto 27); -fifo_in_data(14) <= fifo_14_data_in(26 downto 0); fifo_in_count(14) <= fifo_14_data_in(37 downto 27); -fifo_in_data(15) <= fifo_15_data_in(26 downto 0); fifo_in_count(15) <= fifo_15_data_in(37 downto 27); +fifo_in_data(0) <= fifo_0_data_in(26 downto 0); fifo_in_count(0) <= fifo_0_data_in(37 downto 27); +fifo_in_data(1) <= fifo_1_data_in(26 downto 0); fifo_in_count(1) <= fifo_1_data_in(37 downto 27); +fifo_in_data(2) <= fifo_2_data_in(26 downto 0); fifo_in_count(2) <= fifo_2_data_in(37 downto 27); +fifo_in_data(3) <= fifo_3_data_in(26 downto 0); fifo_in_count(3) <= fifo_3_data_in(37 downto 27); +fifo_in_data(4) <= fifo_4_data_in(26 downto 0); fifo_in_count(4) <= fifo_4_data_in(37 downto 27); +fifo_in_data(5) <= fifo_5_data_in(26 downto 0); fifo_in_count(5) <= fifo_5_data_in(37 downto 27); +fifo_in_data(6) <= fifo_6_data_in(26 downto 0); fifo_in_count(6) <= fifo_6_data_in(37 downto 27); +fifo_in_data(7) <= fifo_7_data_in(26 downto 0); fifo_in_count(7) <= fifo_7_data_in(37 downto 27); +fifo_in_data(8) <= fifo_8_data_in(26 downto 0); fifo_in_count(8) <= fifo_8_data_in(37 downto 27); +fifo_in_data(9) <= fifo_9_data_in(26 downto 0); fifo_in_count(9) <= fifo_9_data_in(37 downto 27); +fifo_in_data(10) <= fifo_10_data_in(26 downto 0); fifo_in_count(10) <= fifo_10_data_in(37 downto 27); +fifo_in_data(11) <= fifo_11_data_in(26 downto 0); fifo_in_count(11) <= fifo_11_data_in(37 downto 27); +fifo_in_data(12) <= fifo_12_data_in(26 downto 0); fifo_in_count(12) <= fifo_12_data_in(37 downto 27); +fifo_in_data(13) <= fifo_13_data_in(26 downto 0); fifo_in_count(13) <= fifo_13_data_in(37 downto 27); +fifo_in_data(14) <= fifo_14_data_in(26 downto 0); fifo_in_count(14) <= fifo_14_data_in(37 downto 27); +fifo_in_data(15) <= fifo_15_data_in(26 downto 0); fifo_in_count(15) <= fifo_15_data_in(37 downto 27); --------------------------------------------------------------------------- -- DATA and LENGTH FIFO for the APV data streams --------------------------------------------------------------------------- +-- We also store the DHDR inside the LFIFOs. They are big enough and have unused bits like hell. +dhdr_fifo_in <= dhdr_length_in & dhdr_data_in; + GEN_FIFO: for i in 0 to 15 generate THE_DFIFO: fifo_2kx27 - port map( DATA => fifo_in_data(i), - CLOCK => clk_in, - WREN => fifo_we_in(i), - RDEN => comb_rd_dfifo(i), -- BUG - RESET => reset_in, - Q => fifo_out_data(i), -- BUG - WCNT => fifo_wcnt(i), -- BUG - EMPTY => open, -- BUG - FULL => open -- BUG - ); + port map( + DATA => fifo_in_data(i), + CLOCK => clk_in, + WREN => fifo_we_in(i), + RDEN => comb_rd_dfifo(i), -- BUG + RESET => reset_in, + Q => fifo_out_data(i), -- BUG + WCNT => fifo_wcnt(i), -- BUG + EMPTY => open, -- BUG + FULL => open -- BUG + ); -- Combinatorial read pulse for FIFOs - comb_rd_dfifo(i) <= (not fifo_done(i) and sel_fifo(i) and ipu_read_in and dataready) or (ld_todo and fifo_ldata(i)(10)); + comb_rd_dfifo(i) <= (not fifo_done(i) and sel_fifo(i) and ipu_read_in and dataready) or (preload and fifo_ldata(i)(10)); -- Combinatorial store pulse for data (last data word need to be transfered also!) comb_st_data(i) <= (sel_fifo(i) and ipu_read_in and dataready); - -- BUGBUGBUG: one clock cycle too late when changing FIFOs.... -- getting the number of free entries in the data fifo by subtracting [size] - [used entries] THE_SUBTRACTOR: suber_12bit - port map( DATAA => x"800", - DATAB => fifo_wcnt(i), - CLOCK => clk_in, - RESET => reset_in, - CLOCKEN => '1', - RESULT => fifo_data_free(i) - ); - + port map( + DATAA => x"800", + DATAB => fifo_wcnt(i), + CLOCK => clk_in, + RESET => reset_in, + CLOCKEN => '1', + RESULT => fifo_data_free(i) + ); + + -- check if next event will still fit into data FIFO + THE_COMPARATOR: comp_12bit + port map( + DATAA => fifo_data_free(i), + DATAB => fifo_space_req_in, + CLOCK => clk_in, + CLOCKEN => '1', + ACLR => '0', + AGTB => dfifo_available(i) + ); + -- length fifo - stores the number of words to fetch from dfifo - THE_LFIFO: fifo_16x11 - port map( DATA => fifo_in_count(i), - CLOCK => clk_in, - WREN => fifo_done_in, - RDEN => rd_lfifo, - RESET => reset_in, - Q => fifo_ldata(i), - WCNT => open, -- BUG - EMPTY => open, -- BUG - FULL => open -- BUG - ); + THE_LFIFO: fifo_1kx18 + port map( + DATA(17 downto 15) => dhdr_fifo_in(i*3 + 2 downto i*3), + DATA(14 downto 11) => b"0000", -- free for other stuff! + DATA(10 downto 0) => fifo_in_count(i), + CLOCK => clk_in, + WREN => fifo_done_in, + RDEN => rd_lfifo, + RESET => reset_in, + Q(17 downto 11) => fifo_lunused(i), -- will be portions of DHDR + Q(10 downto 0) => fifo_ldata(i), + WCNT => open, -- BUG + EMPTY => lfifo_empty(i), -- open -- BUG + FULL => lfifo_full(i) --open -- BUG + ); next_todo_list(i) <= fifo_ldata(i)(10); + -- reassamble the DHDR information + dhdr_fifo_out(i*3 + 2 downto i*3) <= fifo_lunused(i)(6 downto 4); + + -- TODO counter for all FIFOs THE_TODO_CTR_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then @@ -353,24 +394,10 @@ end generate GEN_FIFO; comb_ack_todo <= fifo_last and set_data; - ---------------------------------------------------------------------------- --- DHDR buffer - delivers all information ---------------------------------------------------------------------------- -dhdr_fifo_in <= dhdr_length_in & dhdr_data_in; - -THE_DHDR_BUF: dhdr_buf -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - DHDR_DATA_IN => dhdr_fifo_in, - DHDR_WE_IN => dhdr_store_in, - DHDR_DONE_IN => finished, - DHDR_DATA_OUT => dhdr_fifo_out, - DHDR_AVAILABLE_OUT => dhdr_avail, - BUF_FULL_OUT => dhdr_buf_full, - BUF_LEVEL_OUT => open, - DEBUG_OUT => open - ); +next_dhdr_buf_full <= '1' when (lfifo_full(0) = '1') or + (dfifo_available /= b"1111_1111_1111_1111") + else '0'; +dhdr_avail <= not lfifo_empty(0); -- FAKE -- compare incoming trigger number with stored DHDR information next_trgnum_match <= '1' when ( ipu_number_in = dhdr_fifo_out(15 downto 0) ) else '0'; @@ -392,7 +419,6 @@ end process THE_TRGNUM_MATCH_PROC; --------------------------------------------------------------------------- -- priority encoding is used to select the next buffer for readout --------------------------------------------------------------------------- ---THE_PRI_ENCODER_PROC: process( todo_list, fifo_sel, fifo_done ) THE_PRI_ENCODER_PROC: process( todo_list, fifo_done ) begin if ( todo_list(15 downto 15) = "1" ) then @@ -454,23 +480,24 @@ end process THE_TODO_LIST_PROC; THE_SYNC_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then - fifo_sel <= next_fifo_sel; - sel_fifo <= next_sel_fifo; - fifo_done <= next_fifo_done; - fifo_last <= next_fifo_last; + fifo_sel <= next_fifo_sel; + sel_fifo <= next_sel_fifo; + fifo_done <= next_fifo_done; + fifo_last <= next_fifo_last; + dhdr_buf_full <= next_dhdr_buf_full; end if; end process THE_SYNC_PROC; --------------------------------------------------------------------------- --- backplane wise APV mapping +-- backplane wise APV mapping --------------------------------------------------------------------------- -old_apv_num <= fifo_sel(3 downto 0); +old_apv_num <= fifo_sel(3 downto 0); THE_ADC_APV_MAP_MEM: adc_apv_map_mem -port map( ADDRESS(6 downto 4) => module_in(2 downto 0), - ADDRESS(3 downto 0) => old_apv_num, - Q => new_apv_num +port map( ADDRESS(6 downto 4) => module_in(2 downto 0), + ADDRESS(3 downto 0) => old_apv_num, + Q => new_apv_num ); --------------------------------------------------------------------------- @@ -535,11 +562,12 @@ end process THE_CYCLE_COUNTER_PROC; --------------------------------------------------------------------------- -- debug information --------------------------------------------------------------------------- -debug(63 downto 28) <= (others => '0'); -debug(27 downto 16) <= fifo_data_free(13); -debug(15 downto 12) <= (others => '0'); -debug(11 downto 0) <= fifo_wcnt(13); - +debug(63 downto 48) <= todo_list; +debug(47 downto 25) <= (others => '0'); +debug(24 downto 20) <= fifo_sel; +debug(19 downto 17) <= (others => '0'); +debug(16) <= fifo_last; +debug(15 downto 0) <= fifo_done; --------------------------------------------------------------------------- -- Output signals @@ -557,6 +585,6 @@ dbg_out <= debug; end behavioral; - + diff --git a/src/logic_analyzer.vhd b/src/logic_analyzer.vhd index 245f894..983bc23 100644 --- a/src/logic_analyzer.vhd +++ b/src/logic_analyzer.vhd @@ -7,56 +7,56 @@ library work; use work.adcmv3_components.all; entity logic_analyzer is -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- control signals - ARM_IN : in std_logic; -- arm the machine - TRG_IN : in std_logic; -- trigger the data acquisition - MAX_SAMPLE_IN : in std_logic_vector(9 downto 0); - -- status signals - SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses - SM_CE_OUT : out std_logic; - SM_WE_OUT : out std_logic; -- write enable for sample RAM - CLEAR_OUT : out std_logic; -- sample memory is being cleared - RUN_OUT : out std_logic; -- ready for trigger - SAMPLE_OUT : out std_logic; -- data acquisition running - READY_OUT : out std_logic; -- data acquisition is finished - LAST_OUT : out std_logic; -- last data word of sampling - -- Status lines - BSM_OUT : out std_logic_vector(3 downto 0); - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- control signals + ARM_IN : in std_logic; -- arm the machine + TRG_IN : in std_logic; -- trigger the data acquisition + MAX_SAMPLE_IN : in std_logic_vector(9 downto 0); + -- status signals + SM_ADDR_OUT : out std_logic_vector(9 downto 0); -- sample RAM addresses + SM_CE_OUT : out std_logic; + SM_WE_OUT : out std_logic; -- write enable for sample RAM + CLEAR_OUT : out std_logic; -- sample memory is being cleared + RUN_OUT : out std_logic; -- ready for trigger + SAMPLE_OUT : out std_logic; -- data acquisition running + READY_OUT : out std_logic; -- data acquisition is finished + LAST_OUT : out std_logic; -- last data word of sampling + -- Status lines + BSM_OUT : out std_logic_vector(3 downto 0); + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); end entity; architecture Behavioral of logic_analyzer is -- Signals +type STATES is (SM_SLEEP,SM_CLEAR,SM_RUN,SM_SAMPLE,SM_READY); +signal CURRENT_STATE, NEXT_STATE: STATES; - type STATES is (SM_SLEEP,SM_CLEAR,SM_RUN,SM_SAMPLE,SM_READY); - signal CURRENT_STATE, NEXT_STATE: STATES; +signal sm_addr : std_logic_vector(9 downto 0); +signal sm_counter : std_logic_vector(9 downto 0); - signal sm_addr : std_logic_vector(9 downto 0); - signal sm_counter : std_logic_vector(9 downto 0); +signal sm_we_x : std_logic; +signal sm_we : std_logic; +signal sm_ce_x : std_logic; +signal sm_ce : std_logic; +signal sm_rst_x : std_logic; +signal sm_rst : std_logic; +signal sm_acq_x : std_logic; +signal sm_acq : std_logic; +signal sm_done_x : std_logic; +signal sm_done : std_logic; - signal sm_we_x : std_logic; - signal sm_we : std_logic; - signal sm_ce_x : std_logic; - signal sm_ce : std_logic; - signal sm_rst_x : std_logic; - signal sm_rst : std_logic; - signal sm_acq_x : std_logic; - signal sm_acq : std_logic; - signal sm_done_x : std_logic; - signal sm_done : std_logic; +signal sm_clear_done_x : std_logic; +signal sm_clear_done : std_logic; +signal sm_sample_done_x : std_logic; +signal sm_sample_done : std_logic; - signal sm_clear_done_x : std_logic; - signal sm_clear_done : std_logic; - signal sm_sample_done_x : std_logic; - signal sm_sample_done : std_logic; +signal data_available : std_logic; - signal data_available : std_logic; - --- signal debug : std_logic_vector(31 downto 0); +-- signal debug : std_logic_vector(31 downto 0); begin @@ -147,13 +147,13 @@ begin sm_acq_x <= '0'; sm_done_x <= '0'; case CURRENT_STATE is - when SM_SLEEP => if( arm_in = '1' ) then + when SM_SLEEP => if( arm_in = '1' ) then NEXT_STATE <= SM_CLEAR; sm_rst_x <= '1'; - else + else NEXT_STATE <= SM_SLEEP; end if; - when SM_CLEAR => if( sm_clear_done = '1' ) then + when SM_CLEAR => if( sm_clear_done = '1' ) then NEXT_STATE <= SM_RUN; sm_ce_x <= '1'; sm_we_x <= '1'; @@ -162,7 +162,7 @@ begin sm_ce_x <= '1'; sm_we_x <= '1'; end if; - when SM_RUN => if( trg_in = '1' ) then + when SM_RUN => if( trg_in = '1' ) then NEXT_STATE <= SM_SAMPLE; sm_ce_x <= '1'; sm_we_x <= '1'; @@ -172,7 +172,7 @@ begin sm_ce_x <= '1'; sm_we_x <= '1'; end if; - when SM_SAMPLE => if( sm_sample_done = '1' ) then + when SM_SAMPLE => if( sm_sample_done = '1' ) then NEXT_STATE <= SM_READY; sm_done_x <= '1'; else @@ -181,9 +181,9 @@ begin sm_we_x <= '1'; sm_acq_x <= '1'; end if; - when SM_READY => NEXT_STATE <= SM_SLEEP; + when SM_READY => NEXT_STATE <= SM_SLEEP; - when others => NEXT_STATE <= SM_SLEEP; + when others => NEXT_STATE <= SM_SLEEP; end case; end process TRANSFORM; @@ -191,22 +191,22 @@ end process TRANSFORM; STATE_DECODE: process( CURRENT_STATE ) begin case CURRENT_STATE is - when SM_SLEEP => bsm_out <= x"0"; + when SM_SLEEP => bsm_out <= x"0"; clear_out <= '0'; run_out <= '0'; - when SM_CLEAR => bsm_out <= x"1"; + when SM_CLEAR => bsm_out <= x"1"; clear_out <= '1'; run_out <= '0'; - when SM_RUN => bsm_out <= x"2"; + when SM_RUN => bsm_out <= x"2"; clear_out <= '0'; run_out <= '1'; - when SM_SAMPLE => bsm_out <= x"3"; + when SM_SAMPLE => bsm_out <= x"3"; clear_out <= '0'; run_out <= '0'; - when SM_READY => bsm_out <= x"4"; + when SM_READY => bsm_out <= x"4"; clear_out <= '0'; run_out <= '0'; - when others => bsm_out <= x"f"; + when others => bsm_out <= x"f"; clear_out <= '0'; run_out <= '0'; end case; diff --git a/src/max_data.vhd b/src/max_data.vhd index 01cc2ee..b4077f6 100644 --- a/src/max_data.vhd +++ b/src/max_data.vhd @@ -1,55 +1,57 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.adcmv3_components.all; entity max_data is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - TODO_3_IN : in std_logic_vector(3 downto 0); - TODO_2_IN : in std_logic_vector(3 downto 0); - TODO_1_IN : in std_logic_vector(3 downto 0); - TODO_0_IN : in std_logic_vector(3 downto 0); - TODO_MAX_OUT : out std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TODO_3_IN : in std_logic_vector(3 downto 0); + TODO_2_IN : in std_logic_vector(3 downto 0); + TODO_1_IN : in std_logic_vector(3 downto 0); + TODO_0_IN : in std_logic_vector(3 downto 0); + TODO_MAX_OUT : out std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of max_data is - -- Placer Directives - - -- normal signals - -- first comparatopr step - signal max_32_data : std_logic_vector(3 downto 0); - signal max_21_data : std_logic_vector(3 downto 0); - signal max_10_data : std_logic_vector(3 downto 0); - signal comb_3_gt_2 : std_logic; - signal comb_2_gt_1 : std_logic; - signal comb_1_gt_0 : std_logic; - -- second comparator step - signal max_321_data : std_logic_vector(3 downto 0); - signal max_210_data : std_logic_vector(3 downto 0); - signal comb_32_gt_21 : std_logic; - signal comb_21_gt_10 : std_logic; - -- third comparator step - signal max_final_data : std_logic_vector(3 downto 0); - signal comb_final : std_logic; - - signal debug : std_logic_vector(15 downto 0); - -begin +-- Placer Directives + +-- normal signals +-- first comparatopr step +signal max_32_data : std_logic_vector(3 downto 0); +signal max_21_data : std_logic_vector(3 downto 0); +signal max_10_data : std_logic_vector(3 downto 0); +signal comb_3_gt_2 : std_logic; +signal comb_2_gt_1 : std_logic; +signal comb_1_gt_0 : std_logic; +-- second comparator step +signal max_321_data : std_logic_vector(3 downto 0); +signal max_210_data : std_logic_vector(3 downto 0); +signal comb_32_gt_21 : std_logic; +signal comb_21_gt_10 : std_logic; +-- third comparator step +signal max_final_data : std_logic_vector(3 downto 0); +signal comb_final : std_logic; + +signal debug : std_logic_vector(15 downto 0); + +begin -- FIRST COMPARATOR STEP -- compare MAX_3 against MAX_2, store the bigger one THE_COMP_3_2: comp4bit -port map( DATAA => todo_3_in, - DATAB => todo_2_in, - AGTB => comb_3_gt_2 - ); +port map( + DATAA => todo_3_in, + DATAB => todo_2_in, + AGTB => comb_3_gt_2 +); THE_3_2_STORE_PROC: process( clk_in ) begin @@ -67,10 +69,11 @@ end process THE_3_2_STORE_PROC; -- compare MAX_2 against MAX_1, store the bigger one THE_COMP_2_1: comp4bit -port map( DATAA => todo_2_in, - DATAB => todo_1_in, - AGTB => comb_2_gt_1 - ); +port map( + DATAA => todo_2_in, + DATAB => todo_1_in, + AGTB => comb_2_gt_1 +); THE_2_1_STORE_PROC: process( clk_in ) begin @@ -87,10 +90,11 @@ end process THE_2_1_STORE_PROC; -- compare MAX_1 against MAX_0, store the bigger one THE_COMP_1_0: comp4bit -port map( DATAA => todo_1_in, - DATAB => todo_0_in, - AGTB => comb_1_gt_0 - ); +port map( + DATAA => todo_1_in, + DATAB => todo_0_in, + AGTB => comb_1_gt_0 +); THE_1_0_STORE_PROC: process( clk_in ) begin @@ -109,10 +113,11 @@ end process THE_1_0_STORE_PROC; -- SECOND COMPARATOR STEP -- compare MAX_32 against MAX_21, store the bigger one THE_COMP_32_21: comp4bit -port map( DATAA => max_32_data, - DATAB => max_21_data, - AGTB => comb_32_gt_21 - ); +port map( + DATAA => max_32_data, + DATAB => max_21_data, + AGTB => comb_32_gt_21 +); THE_32_21_STORE_PROC: process( clk_in ) begin @@ -129,10 +134,11 @@ end process THE_32_21_STORE_PROC; -- compare MAX_21 against MAX_10, store the bigger one THE_COMP_21_10: comp4bit -port map( DATAA => max_21_data, - DATAB => max_10_data, - AGTB => comb_21_gt_10 - ); +port map( + DATAA => max_21_data, + DATAB => max_10_data, + AGTB => comb_21_gt_10 +); THE_21_10_STORE_PROC: process( clk_in ) begin @@ -149,10 +155,11 @@ end process THE_21_10_STORE_PROC; -- FINAL COMPARATOR STEP THE_COMP_FINAL: comp4bit -port map( DATAA => max_321_data, - DATAB => max_210_data, - AGTB => comb_final - ); +port map( + DATAA => max_321_data, + DATAB => max_210_data, + AGTB => comb_final +); THE_FINAL_STORE_PROC: process( clk_in ) begin @@ -172,7 +179,7 @@ debug(15 downto 0) <= (others => '0'); -- output signals todo_max_out <= max_final_data; -debug_out <= debug; - -end behavioral; - \ No newline at end of file +debug_out <= debug; + +end behavioral; + \ No newline at end of file diff --git a/src/msg_file.log b/src/msg_file.log index 079084d..85a99f7 100644 --- a/src/msg_file.log +++ b/src/msg_file.log @@ -1,35 +1,33 @@ -SCUBA, Version ispLever_v72_PROD_Build (44) -Fri Nov 20 19:14:28 2009 +SCUBA, Version ispLever_v8.0_PROD_Build (41) +Fri Apr 16 11:05:24 2010 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved. BEGIN SCUBA Module Synthesis - Issued command : F:\Programme\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -n dpram_8x19 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -dram -type ramdps -raddr_width 4 -rwidth 19 -waddr_width 4 -wwidth 19 -rnum_words 16 -wnum_words 16 -outData UNREGISTERED -e - Circuit name : dpram_8x19 - Module type : sdpram - Module Version : 3.4 - Address width : 4 - Data width : 19 + Issued command : X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_1kx18 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifoblk -addr_width 10 -data_width 18 -num_words 1024 -no_enable -pe -1 -pf -1 -fill -e + Circuit name : fifo_1kx18 + Module type : fifoblk + Module Version : 4.8 Ports : - Inputs : WrAddress[3:0], Data[18:0], WrClock, WE, WrClockEn, RdAddress[3:0] - Outputs : Q[18:0] + Inputs : Data[17:0], Clock, WrEn, RdEn, Reset + Outputs : Q[17:0], WCNT[10:0], Empty, Full I/O buffer : not inserted - Clock edge : rising edge EDIF output : suppressed - VHDL output : dpram_8x19.vhd - VHDL template : dpram_8x19_tmpl.vhd - VHDL testbench : tb_dpram_8x19_tmpl.vhd + VHDL output : fifo_1kx18.vhd + VHDL template : fifo_1kx18_tmpl.vhd + VHDL testbench : tb_fifo_1kx18_tmpl.vhd VHDL purpose : for synthesis and simulation Bus notation : big endian - Report output : dpram_8x19.srp + Report output : fifo_1kx18.srp Estimated Resource Usage: - LUT : 1 - DRAM : 5 + LUT : 80 + EBR : 1 + Reg : 35 END SCUBA Module Synthesis diff --git a/src/onewire_master.vhd b/src/onewire_master.vhd index 5f1628b..8b91174 100644 --- a/src/onewire_master.vhd +++ b/src/onewire_master.vhd @@ -9,94 +9,97 @@ use work.trb_net_std.all; -- stolen from Jan Michel, was trb_net_onewire.vhd entity onewire_master is - generic( CLK_PERIOD : integer := 10 ); -- clock perion in nanoseconds - port( CLK : in std_logic; - RESET : in std_logic; - READOUT_ENABLE_IN : in std_logic; - -- connection to 1-wire interface (16 APV FEs) - ONEWIRE : inout std_logic_vector(15 downto 0); - BP_ONEWIRE : inout std_logic; - -- connection to external DPRAM for slow control readout - BP_DATA_OUT : out std_logic_vector(15 downto 0); - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(6 downto 0); - WRITE_OUT : out std_logic; - BUSY_OUT : out std_logic; - -- debug - BSM_OUT : out std_logic_vector(7 downto 0); - STAT : out std_logic_vector(15 downto 0) - ); +generic( + CLK_PERIOD : integer := 10 -- clock perion in nanoseconds +); +port( + CLK : in std_logic; + RESET : in std_logic; + READOUT_ENABLE_IN : in std_logic; + -- connection to 1-wire interface (16 APV FEs) + ONEWIRE : inout std_logic_vector(15 downto 0); + BP_ONEWIRE : inout std_logic; + -- connection to external DPRAM for slow control readout + BP_DATA_OUT : out std_logic_vector(15 downto 0); + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(6 downto 0); + WRITE_OUT : out std_logic; + BUSY_OUT : out std_logic; + -- debug + BSM_OUT : out std_logic_vector(7 downto 0); + STAT : out std_logic_vector(15 downto 0) +); end entity; architecture onewire_master_arch of onewire_master is - constant MAX_COUNTER : integer := 2**28-1; - type state_t is (START, IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_ROM_COMMAND, READ_WAIT, - WRITE_START, WRITE_WAIT, READ_BIT, READ_READ_ROM, SEND_CONV_TEMP, - READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP, CHECK_PULSE); - signal STATE : state_t; - signal NEXT_STATE : state_t; - signal bsm : std_logic_vector(7 downto 0); - signal timecounter : integer range 0 to MAX_COUNTER; - signal bitcounter : integer range 0 to 127; - signal bitcounter_vector : std_logic_vector(6 downto 0); - signal inc_bitcounter : std_logic; - signal reset_bitcounter : std_logic; - signal reset_timecounter : std_logic; - signal send_bit : std_logic; - signal next_send_bit : std_logic; - signal recv_bit_ready : std_logic; - signal next_recv_bit_ready : std_logic; - signal ext_ram_addr : std_logic_vector(3 downto 0); - signal ram_addr : std_logic_vector(2 downto 0); - signal ram_wr : std_logic; - - -- state machine auxiliary signals - signal wait_pulse : std_logic; - signal next_wait_pulse : std_logic; - signal strong_pullup : std_logic; - signal next_strong_pullup : std_logic; - signal presence_reset : std_logic; - signal next_presence_reset : std_logic; - signal send_rom : std_logic; -- read UniqueID - signal next_send_rom : std_logic; - signal conv_temp : std_logic; -- send CONV_TEMP - signal next_conv_temp : std_logic; - signal reading_temp : std_logic; -- readback of temperature - signal next_reading_temp : std_logic; - signal skip_rom : std_logic; -- send SKIP_ROM - signal next_skip_rom : std_logic; - signal output_tmp : std_logic; -- 1W output signal - signal next_output_tmp : std_logic; - signal output : std_logic; - signal next_output : std_logic; - - -- presence pulse detection - signal neg_edge : std_logic_vector(16 downto 0); -- presence pulse edge detection - signal presence_found : std_logic_vector(16 downto 0); -- set signal for presence bits - signal presence : std_logic_vector(16 downto 0); -- presence bits - - type input_t is array (0 to 16) of std_logic_vector(7 downto 0); - signal input : input_t; - - type word_t is array (0 to 16) of std_logic_vector(15 downto 0); - signal word : word_t; - - signal recv_bit : std_logic_vector(16 downto 0); - signal next_recv_bit : std_logic_vector(16 downto 0); - - signal comb_ext_addr_go : std_logic; - - -- output signals, delayed by one cycle - signal mux_data : std_logic_vector(15 downto 0); - signal mux_addr : std_logic_vector(6 downto 0); - signal mux_wr : std_logic; - - signal onewire_tmp : std_logic_vector(16 downto 0); - - signal comb_busy : std_logic; - signal busy : std_logic; - +constant MAX_COUNTER : integer := 2**28-1; +type state_t is (START, IDLE, SEND_RESET, WAIT_AFTER_RESET, SEND_ROM_COMMAND, READ_WAIT, + WRITE_START, WRITE_WAIT, READ_BIT, READ_READ_ROM, SEND_CONV_TEMP, + READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP, CHECK_PULSE); +signal STATE : state_t; +signal NEXT_STATE : state_t; +signal bsm : std_logic_vector(7 downto 0); +signal timecounter : integer range 0 to MAX_COUNTER; +signal bitcounter : integer range 0 to 127; +signal bitcounter_vector : std_logic_vector(6 downto 0); +signal inc_bitcounter : std_logic; +signal reset_bitcounter : std_logic; +signal reset_timecounter : std_logic; +signal send_bit : std_logic; +signal next_send_bit : std_logic; +signal recv_bit_ready : std_logic; +signal next_recv_bit_ready : std_logic; +signal ext_ram_addr : std_logic_vector(3 downto 0); +signal ram_addr : std_logic_vector(2 downto 0); +signal ram_wr : std_logic; + +-- state machine auxiliary signals +signal wait_pulse : std_logic; +signal next_wait_pulse : std_logic; +signal strong_pullup : std_logic; +signal next_strong_pullup : std_logic; +signal presence_reset : std_logic; +signal next_presence_reset : std_logic; +signal send_rom : std_logic; -- read UniqueID +signal next_send_rom : std_logic; +signal conv_temp : std_logic; -- send CONV_TEMP +signal next_conv_temp : std_logic; +signal reading_temp : std_logic; -- readback of temperature +signal next_reading_temp : std_logic; +signal skip_rom : std_logic; -- send SKIP_ROM +signal next_skip_rom : std_logic; +signal output_tmp : std_logic; -- 1W output signal +signal next_output_tmp : std_logic; +signal output : std_logic; +signal next_output : std_logic; + +-- presence pulse detection +signal neg_edge : std_logic_vector(16 downto 0); -- presence pulse edge detection +signal presence_found : std_logic_vector(16 downto 0); -- set signal for presence bits +signal presence : std_logic_vector(16 downto 0); -- presence bits + +type input_t is array (0 to 16) of std_logic_vector(7 downto 0); +signal input : input_t; + +type word_t is array (0 to 16) of std_logic_vector(15 downto 0); +signal word : word_t; + +signal recv_bit : std_logic_vector(16 downto 0); +signal next_recv_bit : std_logic_vector(16 downto 0); + +signal comb_ext_addr_go : std_logic; + +-- output signals, delayed by one cycle +signal mux_data : std_logic_vector(15 downto 0); +signal mux_addr : std_logic_vector(6 downto 0); +signal mux_wr : std_logic; + +signal onewire_tmp : std_logic_vector(16 downto 0); + +signal comb_busy : std_logic; +signal busy : std_logic; + begin -- bidirectional connection @@ -175,7 +178,7 @@ end process THE_STATE_REGS_PROC; comb_busy <= '0' when (STATE = START) else '1'; -- State machine transitions -THE_STATE_MACHINE: process( STATE, timecounter, bitcounter_vector, input, send_bit, output_tmp, +THE_STATE_MACHINE: process( STATE, timecounter, bitcounter_vector, input, send_bit, output_tmp, skip_rom, recv_bit, conv_temp, reading_temp, send_rom, readout_enable_in ) begin NEXT_STATE <= STATE; @@ -197,14 +200,14 @@ begin next_presence_reset <= '0'; case STATE is - -- + -- when START => if( readout_enable_in = '1' ) then NEXT_STATE <= IDLE; reset_timecounter <= '1'; end if; - -- idle state for the DS1822 + -- idle state for the DS1822 when IDLE => if( is_time_reached(timecounter,640000,CLK_PERIOD) = '1' ) then NEXT_STATE <= SEND_RESET; @@ -224,7 +227,7 @@ begin when WAIT_AFTER_RESET => if( is_time_reached(timecounter,10000,CLK_PERIOD) = '1' ) then reset_timecounter <= '1'; - NEXT_STATE <= CHECK_PULSE; + NEXT_STATE <= CHECK_PULSE; end if; -- check if the is a pulse @@ -243,9 +246,9 @@ begin NEXT_STATE <= WRITE_START; if( send_rom = '1' ) then - next_send_bit <= not bitcounter_vector(1); -- this is x33 (READ_ROM_COMMAND), lsb first + next_send_bit <= not bitcounter_vector(1); -- this is x33 (READ_ROM_COMMAND), lsb first else - next_send_bit <= bitcounter_vector(1); -- this is xCC (SKIP_ROM_COMMAND), lsb first + next_send_bit <= bitcounter_vector(1); -- this is xCC (SKIP_ROM_COMMAND), lsb first end if; if( bitcounter_vector(3) = '1' ) then --send 8 bit @@ -262,7 +265,7 @@ begin --sending sensor commands when SEND_CONV_TEMP => next_send_bit <= bitcounter_vector(1) and not bitcounter_vector(0); - --this is x44, lsb first + --this is x44, lsb first inc_bitcounter <= '1'; if( bitcounter_vector(3) = '1' ) then --send 8 bit NEXT_STATE <= READ_CONV_TEMP; @@ -281,7 +284,7 @@ begin end if; inc_bitcounter <= '1'; - + if( bitcounter_vector(3) = '1' ) then --send 8 bit NEXT_STATE <= READ_READ_TEMP; reset_bitcounter <= '1'; @@ -306,7 +309,7 @@ begin when READ_CONV_TEMP => --waiting for end of conversion next_strong_pullup <= '1'; if( is_time_reached(timecounter,1300000000,CLK_PERIOD) = '1' ) then -- reality is 1.3s delay --- if( is_time_reached(timecounter,3000000,CLK_PERIOD) = '1' ) then -- simulation is 3ms delay +-- if( is_time_reached(timecounter,3000000,CLK_PERIOD) = '1' ) then -- simulation is 3ms delay NEXT_STATE <= IDLE; reset_timecounter <= '1'; next_conv_temp <= '0'; @@ -335,7 +338,7 @@ begin next_output_tmp <= '0'; reset_timecounter <= '1'; end if; - + when WRITE_WAIT => if( is_time_reached(timecounter,1200,CLK_PERIOD) = '1' ) then reset_timecounter <= '1'; @@ -361,7 +364,7 @@ begin next_recv_bit_ready <= '1'; NEXT_STATE <= READ_WAIT; end if; - + when READ_WAIT => if( is_time_reached(timecounter,80000,CLK_PERIOD) = '1' ) then reset_timecounter <= '1'; @@ -384,22 +387,22 @@ end process THE_STATE_MACHINE; STATE_DECODE: process( STATE ) begin case STATE is - when START => bsm <= x"00"; - when IDLE => bsm <= x"01"; - when SEND_RESET => bsm <= x"02"; - when WAIT_AFTER_RESET => bsm <= x"03"; - when CHECK_PULSE => bsm <= x"0e"; - when SEND_ROM_COMMAND => bsm <= x"04"; - when READ_WAIT => bsm <= x"05"; - when WRITE_START => bsm <= x"06"; - when WRITE_WAIT => bsm <= x"07"; - when READ_BIT => bsm <= x"08"; - when READ_READ_ROM => bsm <= x"09"; - when SEND_CONV_TEMP => bsm <= x"0a"; - when READ_CONV_TEMP => bsm <= x"0b"; - when SEND_READ_TEMP => bsm <= x"0c"; - when READ_READ_TEMP => bsm <= x"0d"; - when others => bsm <= x"ff"; + when START => bsm <= x"00"; + when IDLE => bsm <= x"01"; + when SEND_RESET => bsm <= x"02"; + when WAIT_AFTER_RESET => bsm <= x"03"; + when CHECK_PULSE => bsm <= x"0e"; + when SEND_ROM_COMMAND => bsm <= x"04"; + when READ_WAIT => bsm <= x"05"; + when WRITE_START => bsm <= x"06"; + when WRITE_WAIT => bsm <= x"07"; + when READ_BIT => bsm <= x"08"; + when READ_READ_ROM => bsm <= x"09"; + when SEND_CONV_TEMP => bsm <= x"0a"; + when READ_CONV_TEMP => bsm <= x"0b"; + when SEND_READ_TEMP => bsm <= x"0c"; + when READ_READ_TEMP => bsm <= x"0d"; + when others => bsm <= x"ff"; end case; end process STATE_DECODE; -------------------------------------------------------------------------------------- @@ -437,7 +440,7 @@ begin if( reset = '1' ) then ram_addr(1 downto 0) <= (others => '0'); ram_wr <= '0'; --- word(i) <= (others => '0'); +-- word(i) <= (others => '0'); else ram_wr <= '0'; -- Shift process for serial / parallel data conversion @@ -457,12 +460,12 @@ begin ram_addr <= "100"; ram_wr <= '1'; for i in 0 to 16 loop - word(i)(11) <= recv_bit(i); + word(i)(11) <= recv_bit(i); word(i)(10 downto 0) <= word(i)(15 downto 5); word(i)(14 downto 12) <= (others => '0'); word(i)(15) <= presence(i); end loop; - + end if; end if; end if; @@ -477,7 +480,7 @@ begin ext_ram_addr <= (others => '0'); elsif( (comb_ext_addr_go = '1') ) then ext_ram_addr <= ext_ram_addr + 1; - end if; + end if; end if; end process THE_EXT_ADDR_PROC; @@ -488,23 +491,23 @@ DATA_MUX_PROC: process(clk) begin if( rising_edge(clk) ) then case ext_ram_addr is - when x"0" => mux_data <= word(0); - when x"1" => mux_data <= word(1); - when x"2" => mux_data <= word(2); - when x"3" => mux_data <= word(3); - when x"4" => mux_data <= word(4); - when x"5" => mux_data <= word(5); - when x"6" => mux_data <= word(6); - when x"7" => mux_data <= word(7); - when x"8" => mux_data <= word(8); - when x"9" => mux_data <= word(9); - when x"a" => mux_data <= word(10); - when x"b" => mux_data <= word(11); - when x"c" => mux_data <= word(12); - when x"d" => mux_data <= word(13); - when x"e" => mux_data <= word(14); - when x"f" => mux_data <= word(15); - when others => mux_data <= x"dead"; + when x"0" => mux_data <= word(0); + when x"1" => mux_data <= word(1); + when x"2" => mux_data <= word(2); + when x"3" => mux_data <= word(3); + when x"4" => mux_data <= word(4); + when x"5" => mux_data <= word(5); + when x"6" => mux_data <= word(6); + when x"7" => mux_data <= word(7); + when x"8" => mux_data <= word(8); + when x"9" => mux_data <= word(9); + when x"a" => mux_data <= word(10); + when x"b" => mux_data <= word(11); + when x"c" => mux_data <= word(12); + when x"d" => mux_data <= word(13); + when x"e" => mux_data <= word(14); + when x"f" => mux_data <= word(15); + when others => mux_data <= x"dead"; end case; mux_addr(2 downto 0) <= ram_addr; mux_addr(6 downto 3) <= ext_ram_addr; diff --git a/src/ped_corr_ctrl.vhd b/src/ped_corr_ctrl.vhd index 4469014..a189201 100755 --- a/src/ped_corr_ctrl.vhd +++ b/src/ped_corr_ctrl.vhd @@ -10,209 +10,237 @@ use work.adcmv3_components.all; -- max_space = (num_frames * 128 + num_frames) = num_frames * 129 entity ped_corr_ctrl is - port( CLK_IN : in std_logic; -- 100MHz local clock - RESET_IN : in std_logic; -- synchronous reset - -- Slow control registers - -- EDS buffer -- back to previous source stage - EDS_DATA_IN : in std_logic_vector(39 downto 0); - EDS_AVAIL_IN : in std_logic; - EDS_DONE_OUT : out std_logic; - EVT_TYPE_IN : in std_logic_vector(2 downto 0); - -- DHDR information -- to next stage - DHDR_DATA_OUT : out std_logic_vector(31 downto 0); - DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0); - DHDR_STORE_OUT : out std_logic; - DHDR_BUF_FULL_IN : in std_logic; - -- data buffers -- from raw_buf_stage - BUF_ADDR_OUT : out std_logic_vector(6 downto 0); - BUF_DONE_OUT : out std_logic; - BUF_TICK_IN : in std_logic_vector(15 downto 0); - BUF_START_IN : in std_logic_vector(15 downto 0); - -- raw data - BUF_0_DATA_IN : in std_logic_vector(37 downto 0); - BUF_1_DATA_IN : in std_logic_vector(37 downto 0); - BUF_2_DATA_IN : in std_logic_vector(37 downto 0); - BUF_3_DATA_IN : in std_logic_vector(37 downto 0); - BUF_4_DATA_IN : in std_logic_vector(37 downto 0); - BUF_5_DATA_IN : in std_logic_vector(37 downto 0); - BUF_6_DATA_IN : in std_logic_vector(37 downto 0); - BUF_7_DATA_IN : in std_logic_vector(37 downto 0); - BUF_8_DATA_IN : in std_logic_vector(37 downto 0); - BUF_9_DATA_IN : in std_logic_vector(37 downto 0); - BUF_10_DATA_IN : in std_logic_vector(37 downto 0); - BUF_11_DATA_IN : in std_logic_vector(37 downto 0); - BUF_12_DATA_IN : in std_logic_vector(37 downto 0); - BUF_13_DATA_IN : in std_logic_vector(37 downto 0); - BUF_14_DATA_IN : in std_logic_vector(37 downto 0); - BUF_15_DATA_IN : in std_logic_vector(37 downto 0); - -- Pedestal data - PED_ADDR_OUT : out std_logic_vector(6 downto 0); - PED_0_DATA_IN : in std_logic_vector(17 downto 0); - PED_1_DATA_IN : in std_logic_vector(17 downto 0); - PED_2_DATA_IN : in std_logic_vector(17 downto 0); - PED_3_DATA_IN : in std_logic_vector(17 downto 0); - PED_4_DATA_IN : in std_logic_vector(17 downto 0); - PED_5_DATA_IN : in std_logic_vector(17 downto 0); - PED_6_DATA_IN : in std_logic_vector(17 downto 0); - PED_7_DATA_IN : in std_logic_vector(17 downto 0); - PED_8_DATA_IN : in std_logic_vector(17 downto 0); - PED_9_DATA_IN : in std_logic_vector(17 downto 0); - PED_10_DATA_IN : in std_logic_vector(17 downto 0); - PED_11_DATA_IN : in std_logic_vector(17 downto 0); - PED_12_DATA_IN : in std_logic_vector(17 downto 0); - PED_13_DATA_IN : in std_logic_vector(17 downto 0); - PED_14_DATA_IN : in std_logic_vector(17 downto 0); - PED_15_DATA_IN : in std_logic_vector(17 downto 0); - -- Threshold data - THR_ADDR_OUT : out std_logic_vector(6 downto 0); - THR_0_DATA_IN : in std_logic_vector(17 downto 0); - THR_1_DATA_IN : in std_logic_vector(17 downto 0); - THR_2_DATA_IN : in std_logic_vector(17 downto 0); - THR_3_DATA_IN : in std_logic_vector(17 downto 0); - THR_4_DATA_IN : in std_logic_vector(17 downto 0); - THR_5_DATA_IN : in std_logic_vector(17 downto 0); - THR_6_DATA_IN : in std_logic_vector(17 downto 0); - THR_7_DATA_IN : in std_logic_vector(17 downto 0); - THR_8_DATA_IN : in std_logic_vector(17 downto 0); - THR_9_DATA_IN : in std_logic_vector(17 downto 0); - THR_10_DATA_IN : in std_logic_vector(17 downto 0); - THR_11_DATA_IN : in std_logic_vector(17 downto 0); - THR_12_DATA_IN : in std_logic_vector(17 downto 0); - THR_13_DATA_IN : in std_logic_vector(17 downto 0); - THR_14_DATA_IN : in std_logic_vector(17 downto 0); - THR_15_DATA_IN : in std_logic_vector(17 downto 0); - -- processed data - FIFO_START_OUT : out std_logic; - FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0); - FIFO_WE_OUT : out std_logic_vector(15 downto 0); - FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs - -- Debug signals - DBG_BSM_OUT : out std_logic_vector(7 downto 0); - DBG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_IN : in std_logic; -- 100MHz local clock + RESET_IN : in std_logic; -- synchronous reset + -- Slow control registers + -- EDS buffer -- back to previous source stage + EDS_DATA_IN : in std_logic_vector(39 downto 0); + EDS_AVAIL_IN : in std_logic; + EDS_DONE_OUT : out std_logic; + -- DHDR information -- to next stage + DHDR_DATA_OUT : out std_logic_vector(31 downto 0); + DHDR_LENGTH_OUT : out std_logic_vector(15 downto 0); + DHDR_STORE_OUT : out std_logic; + DHDR_BUF_FULL_IN : in std_logic; + FIFO_SPACE_REQ_OUT : out std_logic_vector(11 downto 0); + -- data buffers -- from raw_buf_stage + BUF_ADDR_OUT : out std_logic_vector(6 downto 0); + BUF_DONE_OUT : out std_logic; + BUF_TICK_IN : in std_logic_vector(15 downto 0); + BUF_START_IN : in std_logic_vector(15 downto 0); + -- raw data + BUF_0_DATA_IN : in std_logic_vector(37 downto 0); + BUF_1_DATA_IN : in std_logic_vector(37 downto 0); + BUF_2_DATA_IN : in std_logic_vector(37 downto 0); + BUF_3_DATA_IN : in std_logic_vector(37 downto 0); + BUF_4_DATA_IN : in std_logic_vector(37 downto 0); + BUF_5_DATA_IN : in std_logic_vector(37 downto 0); + BUF_6_DATA_IN : in std_logic_vector(37 downto 0); + BUF_7_DATA_IN : in std_logic_vector(37 downto 0); + BUF_8_DATA_IN : in std_logic_vector(37 downto 0); + BUF_9_DATA_IN : in std_logic_vector(37 downto 0); + BUF_10_DATA_IN : in std_logic_vector(37 downto 0); + BUF_11_DATA_IN : in std_logic_vector(37 downto 0); + BUF_12_DATA_IN : in std_logic_vector(37 downto 0); + BUF_13_DATA_IN : in std_logic_vector(37 downto 0); + BUF_14_DATA_IN : in std_logic_vector(37 downto 0); + BUF_15_DATA_IN : in std_logic_vector(37 downto 0); + -- Pedestal data + PED_ADDR_OUT : out std_logic_vector(6 downto 0); + PED_0_DATA_IN : in std_logic_vector(17 downto 0); + PED_1_DATA_IN : in std_logic_vector(17 downto 0); + PED_2_DATA_IN : in std_logic_vector(17 downto 0); + PED_3_DATA_IN : in std_logic_vector(17 downto 0); + PED_4_DATA_IN : in std_logic_vector(17 downto 0); + PED_5_DATA_IN : in std_logic_vector(17 downto 0); + PED_6_DATA_IN : in std_logic_vector(17 downto 0); + PED_7_DATA_IN : in std_logic_vector(17 downto 0); + PED_8_DATA_IN : in std_logic_vector(17 downto 0); + PED_9_DATA_IN : in std_logic_vector(17 downto 0); + PED_10_DATA_IN : in std_logic_vector(17 downto 0); + PED_11_DATA_IN : in std_logic_vector(17 downto 0); + PED_12_DATA_IN : in std_logic_vector(17 downto 0); + PED_13_DATA_IN : in std_logic_vector(17 downto 0); + PED_14_DATA_IN : in std_logic_vector(17 downto 0); + PED_15_DATA_IN : in std_logic_vector(17 downto 0); + -- Threshold data + THR_ADDR_OUT : out std_logic_vector(6 downto 0); + THR_0_DATA_IN : in std_logic_vector(17 downto 0); + THR_1_DATA_IN : in std_logic_vector(17 downto 0); + THR_2_DATA_IN : in std_logic_vector(17 downto 0); + THR_3_DATA_IN : in std_logic_vector(17 downto 0); + THR_4_DATA_IN : in std_logic_vector(17 downto 0); + THR_5_DATA_IN : in std_logic_vector(17 downto 0); + THR_6_DATA_IN : in std_logic_vector(17 downto 0); + THR_7_DATA_IN : in std_logic_vector(17 downto 0); + THR_8_DATA_IN : in std_logic_vector(17 downto 0); + THR_9_DATA_IN : in std_logic_vector(17 downto 0); + THR_10_DATA_IN : in std_logic_vector(17 downto 0); + THR_11_DATA_IN : in std_logic_vector(17 downto 0); + THR_12_DATA_IN : in std_logic_vector(17 downto 0); + THR_13_DATA_IN : in std_logic_vector(17 downto 0); + THR_14_DATA_IN : in std_logic_vector(17 downto 0); + THR_15_DATA_IN : in std_logic_vector(17 downto 0); + -- processed data + FIFO_START_OUT : out std_logic; + FIFO_0_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_1_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_2_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_3_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_4_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_5_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_6_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_7_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_8_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_9_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_10_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_11_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_12_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_13_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_14_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_15_DATA_OUT : out std_logic_vector(39 downto 0); + FIFO_WE_OUT : out std_logic_vector(15 downto 0); + FIFO_DONE_OUT : out std_logic; -- write level information into small FIFOs + -- Debug signals + DBG_BSM_OUT : out std_logic_vector(7 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of ped_corr_ctrl is - -- state machine definitions - type STATES is (SLEEP,LOADFC,DELFC,CHECK,FULL,DEL0,NBERR,EMPTY,CHKFC,FCERR,CHKRW,RWERR,CHKAE,AEERR, - FINIT,FLOAD,FZERO,FREAD,FDONE,FDEL,FDEC,WREDS,ACKEDS,WHDR,EHDR,CCNT,CDEL0,CDEL1,DEL1,DEL2); - signal CURRENT_STATE, NEXT_STATE: STATES; - - -- signals - signal debug : std_logic_vector(15 downto 0); - signal bsm_x : std_logic_vector(7 downto 0); - - -- status signals from TOCs - signal buf_gooddata : std_logic_vector(15 downto 0); - signal buf_baddata : std_logic_vector(15 downto 0); - signal buf_nodata : std_logic_vector(15 downto 0); - signal buf_ready : std_logic_vector(15 downto 0); - - -- local frame counter - signal to_do_ctr : std_logic_vector(3 downto 0); - signal done_ctr : std_logic_vector(3 downto 0); - signal loc_frm_ctr : std_logic_vector(3 downto 0); - signal next_ld_frm_ctr : std_logic; - signal ld_frm_ctr : std_logic; -- load frame counter with EDS start value - signal next_ce_frm_ctr : std_logic; - signal ce_frm_ctr : std_logic; -- increment frame counter - signal next_last_frame : std_logic; - signal last_frame : std_logic; -- all frame buffers have been copied - signal next_cleaned_up : std_logic; - signal cleaned_up : std_logic; -- only relevant in case of errors - signal next_multi_frame : std_logic; - signal multi_frame : std_logic; -- more than one frame requested - signal next_do_hdr : std_logic; - signal do_hdr : std_logic; -- insert debug header (in case of common errors, in case of multiframe) - signal next_do_error : std_logic; - signal do_error : std_logic; -- insert debug header (in case of broken buffer only) - signal next_do_start : std_logic; - signal do_start : std_logic; -- start signal for one event processing - - -- buffer status signals, error signals from checkers - signal buffers_ready : std_logic; -- all buffers are ready for data transport - signal buffers_valid : std_logic; -- at least one buffer has valid data - signal frame_row_error : std_logic; - signal frame_apv_error : std_logic; - signal frame_ctr_error : std_logic; - - signal frame_busy : std_logic; -- from ALU - - -- Buffer read address counter, control signals - signal buf_addr : std_logic_vector(5 downto 0); -- buffer / pedestal read address - signal buf_half : std_logic; - signal next_buf_addr_ce : std_logic; - signal buf_addr_ce : std_logic; - signal next_buf_addr_rst : std_logic; - signal buf_addr_rst : std_logic; - signal next_buf_addr_init : std_logic; -- needed for THR - signal buf_addr_init : std_logic; - signal next_buf_addr_done : std_logic; - signal buf_addr_done : std_logic; - signal next_buf_done : std_logic; - signal buf_done : std_logic; - signal next_frame_valid : std_logic; - signal frame_valid : std_logic; - signal buf_frame_valid : std_logic; - signal raw_addr : std_logic_vector(6 downto 0); - signal buf_raw_addr : std_logic_vector(6 downto 0); - - signal thr_addr : std_logic_vector(6 downto 0); -- threshold read address - signal thr_addr_ce : std_logic; - signal thr_addr_rst : std_logic; - signal dly_thr_addr_ce : std_logic_vector(7 downto 0); - signal dly_thr_addr_rst : std_logic_vector(7 downto 0); - --- signal ped_addr : std_logic_vector(6 downto 0); -- pedestal read address - - -- statemachine signals - signal next_wait_frames : std_logic; - signal wait_frames : std_logic; -- we are in the waiting phase for incoming frames - signal next_eds_wr : std_logic; - signal eds_wr : std_logic; -- copy current EDS into new buffer - signal next_eds_done : std_logic; - signal eds_done : std_logic; -- acknowledge and release old EDS - - -- generate needs arrays... - type raw_data_t is array (0 to 15) of std_logic_vector(37 downto 0); - signal raw_data : raw_data_t; - type fifo_data_t is array (0 to 15) of std_logic_vector(39 downto 0); - signal fifo_data : fifo_data_t; - type sc_data_t is array (0 to 15) of std_logic_vector(17 downto 0); - signal ped_data : sc_data_t; - signal thr_data : sc_data_t; - - signal fifo_we : std_logic_vector(15 downto 0); - - signal errors : std_logic_vector(3 downto 0); - - -- for summing up - signal next_small_0_sum : std_logic_vector(4 downto 0); - signal small_0_sum : std_logic_vector(4 downto 0); - signal next_small_1_sum : std_logic_vector(4 downto 0); - signal small_1_sum : std_logic_vector(4 downto 0); - signal small_sum : std_logic_vector(15 downto 0); - signal total_sum : std_logic_vector(15 downto 0); - signal reset_sum : std_logic; +-- state machine definitions +type STATES is (SLEEP,LOADFC,DELFC,CHECK,FULL,DEL0,NBERR,EMPTY,CHKFC,FCERR,CHKRW,RWERR,CHKAE,AEERR, + FINIT,FLOAD,FZERO,FREAD,FDONE,FDEL,FDEC,WREDS,ACKEDS,WHDR,EHDR,CCNT,CDEL0,CDEL1,DEL1,DEL2); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- signals +signal debug : std_logic_vector(15 downto 0); +signal bsm_x : std_logic_vector(7 downto 0); + +-- status signals from TOCs +signal buf_gooddata : std_logic_vector(15 downto 0); +signal buf_baddata : std_logic_vector(15 downto 0); +signal buf_nodata : std_logic_vector(15 downto 0); +signal buf_ready : std_logic_vector(15 downto 0); + +-- local frame counter +signal to_do_ctr : std_logic_vector(3 downto 0); +signal done_ctr : std_logic_vector(3 downto 0); +signal loc_frm_ctr : std_logic_vector(3 downto 0); +signal next_ld_frm_ctr : std_logic; +signal ld_frm_ctr : std_logic; -- load frame counter with EDS start value +signal next_ce_frm_ctr : std_logic; +signal ce_frm_ctr : std_logic; -- increment frame counter +signal next_last_frame : std_logic; +signal last_frame : std_logic; -- all frame buffers have been copied +signal next_cleaned_up : std_logic; +signal cleaned_up : std_logic; -- only relevant in case of errors +signal next_multi_frame : std_logic; +signal multi_frame : std_logic; -- more than one frame requested +signal next_do_hdr : std_logic; +signal do_hdr : std_logic; -- insert debug header (in case of common errors, in case of multiframe) +signal next_do_error : std_logic; +signal do_error : std_logic; -- insert debug header (in case of broken buffer only) +signal next_do_start : std_logic; +signal do_start : std_logic; -- start signal for one event processing + +-- buffer status signals, error signals from checkers +signal buffers_ready : std_logic; -- all buffers are ready for data transport +signal buffers_valid : std_logic; -- at least one buffer has valid data +signal frame_row_error : std_logic; +signal frame_apv_error : std_logic; +signal frame_ctr_error : std_logic; + +signal frame_busy : std_logic; -- from ALU + +-- Buffer read address counter, control signals +signal buf_addr : std_logic_vector(5 downto 0); -- buffer / pedestal read address +signal buf_half : std_logic; +signal next_buf_addr_ce : std_logic; +signal buf_addr_ce : std_logic; +signal next_buf_addr_rst : std_logic; +signal buf_addr_rst : std_logic; +signal next_buf_addr_init : std_logic; -- needed for THR +signal buf_addr_init : std_logic; +signal next_buf_addr_done : std_logic; +signal buf_addr_done : std_logic; +signal next_buf_done : std_logic; +signal buf_done : std_logic; +signal next_frame_valid : std_logic; +signal frame_valid : std_logic; +signal buf_frame_valid : std_logic; +signal raw_addr : std_logic_vector(6 downto 0); +signal buf_raw_addr : std_logic_vector(6 downto 0); + +-- statemachine signals +signal next_wait_frames : std_logic; +signal wait_frames : std_logic; -- we are in the waiting phase for incoming frames +signal next_eds_wr : std_logic; +signal eds_wr : std_logic; -- copy current EDS into new buffer +signal next_eds_done : std_logic; +signal eds_done : std_logic; -- acknowledge and release old EDS + +-- generate needs arrays... +type raw_data_t is array (0 to 15) of std_logic_vector(37 downto 0); +signal raw_data : raw_data_t; +type fifo_data_t is array (0 to 15) of std_logic_vector(39 downto 0); +signal fifo_data : fifo_data_t; +type sc_data_t is array (0 to 15) of std_logic_vector(17 downto 0); +signal ped_data : sc_data_t; +signal thr_data : sc_data_t; + +signal fifo_we : std_logic_vector(15 downto 0); + +signal errors : std_logic_vector(3 downto 0); + +-- for summing up +signal next_small_0_sum : std_logic_vector(4 downto 0); +signal small_0_sum : std_logic_vector(4 downto 0); +signal next_small_1_sum : std_logic_vector(4 downto 0); +signal small_1_sum : std_logic_vector(4 downto 0); +signal small_sum : std_logic_vector(15 downto 0); +signal total_sum : std_logic_vector(15 downto 0); +signal reset_sum : std_logic; + +signal next_max_num_words : std_logic_vector(11 downto 0); +signal max_num_words : std_logic_vector(11 downto 0); + +signal thr_addr_q : std_logic_vector(6 downto 0); +signal thr_addr_qq : std_logic_vector(6 downto 0); +signal thr_addr_qqq : std_logic_vector(6 downto 0); +begin + +--------------------------------------------------------------------------- +-- "Calculate" the number of words needed in IPU buffer stage +--------------------------------------------------------------------------- + +-- we need three informations: +-- - number of APV data frames => EDS_DATA[35:32] +-- - maximum number of surviving channels (64 or 128) => EDS_DATA[2:0] +-- - number of debug words per APV frame => by design +next_max_num_words(11) <= '0'; +THE_DECIDER_PROC: process( eds_data_in(35 downto 32), eds_data_in(2 downto 0) ) begin + case eds_data_in(2 downto 0) is + when b"000" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - RAW128 + when b"001" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - PED128 + when b"010" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - PED128THR + when b"011" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - RAW64 + when b"100" => next_max_num_words(10 downto 6) <= eds_data_in(35 downto 32) & '0'; -- 128 - NC64PED64 + when b"101" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - NC64 + when b"110" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - NC64GOOD + when b"111" => next_max_num_words(10 downto 6) <= '0' & eds_data_in(35 downto 32); -- 64 - NC64THR + when others => next_max_num_words(10 downto 6) <= (others => '0'); + end case; +end process THE_DECIDER_PROC; + +next_max_num_words(5) <= '0'; +next_max_num_words(4 downto 1) <= eds_data_in(35 downto 32); +next_max_num_words(0) <= '0'; --------------------------------------------------------------------------- -- Aliasing the data streams @@ -273,67 +301,69 @@ thr_data(15) <= thr_15_data_in; -- framecounter check, must be done once per frame --------------------------------------------------------------------------- THE_FRMCTR_CHECK: frmctr_check -port map( CLK_IN => clk_in, - GOODDATA_IN => buf_gooddata, - FRAMECOUNTER_IN => loc_frm_ctr, - FRM_NR_0_IN => raw_data(0)(17 downto 14), - FRM_NR_1_IN => raw_data(1)(17 downto 14), - FRM_NR_2_IN => raw_data(2)(17 downto 14), - FRM_NR_3_IN => raw_data(3)(17 downto 14), - FRM_NR_4_IN => raw_data(4)(17 downto 14), - FRM_NR_5_IN => raw_data(5)(17 downto 14), - FRM_NR_6_IN => raw_data(6)(17 downto 14), - FRM_NR_7_IN => raw_data(7)(17 downto 14), - FRM_NR_8_IN => raw_data(8)(17 downto 14), - FRM_NR_9_IN => raw_data(9)(17 downto 14), - FRM_NR_10_IN => raw_data(10)(17 downto 14), - FRM_NR_11_IN => raw_data(11)(17 downto 14), - FRM_NR_12_IN => raw_data(12)(17 downto 14), - FRM_NR_13_IN => raw_data(13)(17 downto 14), - FRM_NR_14_IN => raw_data(14)(17 downto 14), - FRM_NR_15_IN => raw_data(15)(17 downto 14), - FRC_ERROR_OUT => frame_ctr_error, -- BUG - DBG_OUT => open - ); +port map( + CLK_IN => clk_in, + GOODDATA_IN => buf_gooddata, + FRAMECOUNTER_IN => loc_frm_ctr, + FRM_NR_0_IN => raw_data(0)(17 downto 14), + FRM_NR_1_IN => raw_data(1)(17 downto 14), + FRM_NR_2_IN => raw_data(2)(17 downto 14), + FRM_NR_3_IN => raw_data(3)(17 downto 14), + FRM_NR_4_IN => raw_data(4)(17 downto 14), + FRM_NR_5_IN => raw_data(5)(17 downto 14), + FRM_NR_6_IN => raw_data(6)(17 downto 14), + FRM_NR_7_IN => raw_data(7)(17 downto 14), + FRM_NR_8_IN => raw_data(8)(17 downto 14), + FRM_NR_9_IN => raw_data(9)(17 downto 14), + FRM_NR_10_IN => raw_data(10)(17 downto 14), + FRM_NR_11_IN => raw_data(11)(17 downto 14), + FRM_NR_12_IN => raw_data(12)(17 downto 14), + FRM_NR_13_IN => raw_data(13)(17 downto 14), + FRM_NR_14_IN => raw_data(14)(17 downto 14), + FRM_NR_15_IN => raw_data(15)(17 downto 14), + FRC_ERROR_OUT => frame_ctr_error, -- BUG + DBG_OUT => open +); --------------------------------------------------------------------------- -- framewise ROW and ERROR checker --------------------------------------------------------------------------- THE_REF_ROW_SEL: ref_row_sel -port map( CLK_IN => clk_in, - READY_IN => buf_ready, - GOODDATA_IN => buf_gooddata, - FRAME_0_IN => raw_data(0)(29 downto 18), - FRAME_1_IN => raw_data(1)(29 downto 18), - FRAME_2_IN => raw_data(2)(29 downto 18), - FRAME_3_IN => raw_data(3)(29 downto 18), - FRAME_4_IN => raw_data(4)(29 downto 18), - FRAME_5_IN => raw_data(5)(29 downto 18), - FRAME_6_IN => raw_data(6)(29 downto 18), - FRAME_7_IN => raw_data(7)(29 downto 18), - FRAME_8_IN => raw_data(8)(29 downto 18), - FRAME_9_IN => raw_data(9)(29 downto 18), - FRAME_10_IN => raw_data(10)(29 downto 18), - FRAME_11_IN => raw_data(11)(29 downto 18), - FRAME_12_IN => raw_data(12)(29 downto 18), - FRAME_13_IN => raw_data(13)(29 downto 18), - FRAME_14_IN => raw_data(14)(29 downto 18), - FRAME_15_IN => raw_data(15)(29 downto 18), - VALID_BUFS_OUT => buffers_valid, - READY_OUT => buffers_ready, - ROW_ERROR_OUT => frame_row_error, - APV_ERROR_OUT => frame_apv_error, - APV_ERROR_BITS_OUT => open, -- BUGBUGBUG - REF_ROW_OUT => open, -- selected reference row - DBG_OUT => open - ); +port map( + CLK_IN => clk_in, + READY_IN => buf_ready, + GOODDATA_IN => buf_gooddata, + FRAME_0_IN => raw_data(0)(29 downto 18), + FRAME_1_IN => raw_data(1)(29 downto 18), + FRAME_2_IN => raw_data(2)(29 downto 18), + FRAME_3_IN => raw_data(3)(29 downto 18), + FRAME_4_IN => raw_data(4)(29 downto 18), + FRAME_5_IN => raw_data(5)(29 downto 18), + FRAME_6_IN => raw_data(6)(29 downto 18), + FRAME_7_IN => raw_data(7)(29 downto 18), + FRAME_8_IN => raw_data(8)(29 downto 18), + FRAME_9_IN => raw_data(9)(29 downto 18), + FRAME_10_IN => raw_data(10)(29 downto 18), + FRAME_11_IN => raw_data(11)(29 downto 18), + FRAME_12_IN => raw_data(12)(29 downto 18), + FRAME_13_IN => raw_data(13)(29 downto 18), + FRAME_14_IN => raw_data(14)(29 downto 18), + FRAME_15_IN => raw_data(15)(29 downto 18), + VALID_BUFS_OUT => buffers_valid, + READY_OUT => buffers_ready, + ROW_ERROR_OUT => frame_row_error, + APV_ERROR_OUT => frame_apv_error, + APV_ERROR_BITS_OUT => open, -- BUGBUGBUG + REF_ROW_OUT => open, -- selected reference row + DBG_OUT => open +); --------------------------------------------------------------------------- -- Statemachine --------------------------------------------------------------------------- -- state registers -STATE_MEM: process( clk_in ) +STATE_MEM: process( clk_in ) begin if( rising_edge(clk_in) ) then if( reset_in = '1' ) then @@ -376,8 +406,8 @@ errors(1) <= frame_row_error; errors(0) <= frame_apv_error; -- state transitions -STATE_TRANSFORM: process( CURRENT_STATE, eds_avail_in, dhdr_buf_full_in, last_frame, multi_frame, frame_busy, - buffers_ready, buffers_valid, frame_ctr_error, frame_row_error, frame_apv_error, +STATE_TRANSFORM: process( CURRENT_STATE, eds_avail_in, dhdr_buf_full_in, last_frame, multi_frame, frame_busy, + buffers_ready, buffers_valid, frame_ctr_error, frame_row_error, frame_apv_error, buf_addr_done, buf_half ) begin NEXT_STATE <= SLEEP; -- avoid latches @@ -395,46 +425,48 @@ begin next_do_error <= '0'; next_do_start <= '0'; case CURRENT_STATE is - when SLEEP => if( (eds_avail_in = '1') and (dhdr_buf_full_in = '0') ) then + -- BUG: we need to delay this by some clock cycles to be sure that enough space is available in IPU stage. + -- calculation of max_num_words takes some time. + when SLEEP => if( (eds_avail_in = '1') and (dhdr_buf_full_in = '0') ) then NEXT_STATE <= LOADFC; next_ld_frm_ctr <= '1'; else NEXT_STATE <= SLEEP; end if; - when LOADFC => NEXT_STATE <= DELFC; + when LOADFC => NEXT_STATE <= DELFC; next_do_start <= '1'; - when DELFC => NEXT_STATE <= CHECK; - when CHECK => if( last_frame = '0' ) then + when DELFC => NEXT_STATE <= CHECK; + when CHECK => if( last_frame = '0' ) then NEXT_STATE <= FULL; next_wait_frames <= '1'; else NEXT_STATE <= EMPTY; end if; - when EMPTY => NEXT_STATE <= WREDS; + when EMPTY => NEXT_STATE <= WREDS; next_eds_wr <= '1'; - when FULL => if( buffers_ready = '1' ) then + when FULL => if( buffers_ready = '1' ) then NEXT_STATE <= DEL0; next_do_error <= '1'; -- here broken channels deliver a "I DON'T FEEL GOOD" word... else NEXT_STATE <= FULL; next_wait_frames <= '1'; end if; - when DEL0 => if ( buffers_valid = '1' ) then + when DEL0 => if ( buffers_valid = '1' ) then NEXT_STATE <= CHKFC; else NEXT_STATE <= NBERR; end if; - when CHKFC => if( frame_ctr_error = '0' ) then + when CHKFC => if( frame_ctr_error = '0' ) then NEXT_STATE <= CHKRW; else NEXT_STATE <= FCERR; end if; - when CHKRW => if( frame_row_error = '0' ) then + when CHKRW => if( frame_row_error = '0' ) then NEXT_STATE <= CHKAE; else NEXT_STATE <= RWERR; end if; - when CHKAE => if ( (frame_apv_error = '0') and (multi_frame = '1') ) then + when CHKAE => if ( (frame_apv_error = '0') and (multi_frame = '1') ) then NEXT_STATE <= WHDR; next_do_hdr <= '1'; elsif( (frame_apv_error = '0') and (multi_frame = '0') ) then @@ -443,16 +475,16 @@ begin else NEXT_STATE <= AEERR; end if; - when WHDR => NEXT_STATE <= FINIT; + when WHDR => NEXT_STATE <= FINIT; next_buf_addr_rst <= '1'; - when FINIT => NEXT_STATE <= FLOAD; -- load address x"01"; + when FINIT => NEXT_STATE <= FLOAD; -- load address x"01"; next_buf_addr_ce <= '1'; - when FLOAD => NEXT_STATE <= FZERO; -- load address x"00"; + when FLOAD => NEXT_STATE <= FZERO; -- load address x"00"; next_buf_addr_rst <= '1'; next_buf_addr_init <= not buf_half; - when FZERO => NEXT_STATE <= FREAD; + when FZERO => NEXT_STATE <= FREAD; next_buf_addr_ce <= '1'; - when FREAD => if ( (buf_addr_done = '1') and (buf_half = '1') ) then + when FREAD => if ( (buf_addr_done = '1') and (buf_half = '1') ) then NEXT_STATE <= FDONE; next_ce_frm_ctr <= '1'; next_buf_done <= '1'; @@ -465,33 +497,33 @@ begin next_buf_addr_ce <= '1'; next_frame_valid <= '1'; end if; - when FDONE => if( frame_busy = '1' ) then + when FDONE => if( frame_busy = '1' ) then NEXT_STATE <= FDONE; else NEXT_STATE <= FDEL; end if; - when FDEL => NEXT_STATE <= FDEC; - when FDEC => if( last_frame = '1' ) then + when FDEL => NEXT_STATE <= FDEC; + when FDEC => if( last_frame = '1' ) then NEXT_STATE <= WREDS; -- copy current EDS to new buffer next_eds_wr <= '1'; else NEXT_STATE <= DEL0; -- only for multiframe readout, will not work (needs headers!!!) end if; - when WREDS => NEXT_STATE <= ACKEDS; -- release old EDS + when WREDS => NEXT_STATE <= ACKEDS; -- release old EDS next_eds_done <= '1'; - when ACKEDS => NEXT_STATE <= DEL1; - when DEL1 => NEXT_STATE <= DEL2; - when DEL2 => NEXT_STATE <= SLEEP; - - when NBERR => NEXT_STATE <= EHDR; + when ACKEDS => NEXT_STATE <= DEL1; + when DEL1 => NEXT_STATE <= DEL2; + when DEL2 => NEXT_STATE <= SLEEP; + + when NBERR => NEXT_STATE <= EHDR; next_do_hdr <= '1'; - when FCERR => NEXT_STATE <= EHDR; + when FCERR => NEXT_STATE <= EHDR; next_do_hdr <= '1'; - when RWERR => NEXT_STATE <= EHDR; + when RWERR => NEXT_STATE <= EHDR; next_do_hdr <= '1'; - when AEERR => NEXT_STATE <= EHDR; + when AEERR => NEXT_STATE <= EHDR; next_do_hdr <= '1'; - when EHDR => if( last_frame = '1' ) then + when EHDR => if( last_frame = '1' ) then NEXT_STATE <= WREDS; next_eds_wr <= '1'; else @@ -499,54 +531,54 @@ begin next_ce_frm_ctr <= '1'; next_buf_done <= '1'; end if; - when CCNT => NEXT_STATE <= CDEL0; - when CDEL0 => NEXT_STATE <= CDEL1; - when CDEL1 => if( last_frame = '1' ) then + when CCNT => NEXT_STATE <= CDEL0; + when CDEL0 => NEXT_STATE <= CDEL1; + when CDEL1 => if( last_frame = '1' ) then NEXT_STATE <= WREDS; next_eds_wr <= '1'; else NEXT_STATE <= EHDR; next_do_hdr <= '1'; end if; - when others => NEXT_STATE <= SLEEP; + when others => NEXT_STATE <= SLEEP; end case; -end process STATE_TRANSFORM; +end process STATE_TRANSFORM; -- state decoding (ONLY FOR DEBUGGING!) STATE_DECODE: process( CURRENT_STATE ) begin case CURRENT_STATE is - when SLEEP => bsm_x <= x"00"; - when LOADFC => bsm_x <= x"01"; - when DELFC => bsm_x <= x"02"; - when CHECK => bsm_x <= x"03"; - when FULL => bsm_x <= x"04"; - when EMPTY => bsm_x <= x"05"; - when NBERR => bsm_x <= x"06"; - when CHKFC => bsm_x <= x"07"; - when FCERR => bsm_x <= x"08"; - when CHKRW => bsm_x <= x"09"; - when RWERR => bsm_x <= x"0a"; - when CHKAE => bsm_x <= x"0b"; - when AEERR => bsm_x <= x"0c"; - when FINIT => bsm_x <= x"0d"; - when FLOAD => bsm_x <= x"0e"; - when FZERO => bsm_x <= x"0f"; - when FREAD => bsm_x <= x"10"; - when FDONE => bsm_x <= x"11"; - when FDEL => bsm_x <= x"12"; - when FDEC => bsm_x <= x"13"; - when WREDS => bsm_x <= x"14"; - when ACKEDS => bsm_x <= x"15"; - when EHDR => bsm_x <= x"16"; - when CDEL0 => bsm_x <= x"17"; - when CDEL1 => bsm_x <= x"18"; - when CCNT => bsm_x <= x"19"; - when DEL0 => bsm_x <= x"20"; - when DEL1 => bsm_x <= x"21"; - when DEL2 => bsm_x <= x"22"; - when WHDR => bsm_x <= x"23"; - when others => bsm_x <= x"ff"; + when SLEEP => bsm_x <= x"00"; + when LOADFC => bsm_x <= x"01"; + when DELFC => bsm_x <= x"02"; + when CHECK => bsm_x <= x"03"; + when FULL => bsm_x <= x"04"; + when EMPTY => bsm_x <= x"05"; + when NBERR => bsm_x <= x"06"; + when CHKFC => bsm_x <= x"07"; + when FCERR => bsm_x <= x"08"; + when CHKRW => bsm_x <= x"09"; + when RWERR => bsm_x <= x"0a"; + when CHKAE => bsm_x <= x"0b"; + when AEERR => bsm_x <= x"0c"; + when FINIT => bsm_x <= x"0d"; + when FLOAD => bsm_x <= x"0e"; + when FZERO => bsm_x <= x"0f"; + when FREAD => bsm_x <= x"10"; + when FDONE => bsm_x <= x"11"; + when FDEL => bsm_x <= x"12"; + when FDEC => bsm_x <= x"13"; + when WREDS => bsm_x <= x"14"; + when ACKEDS => bsm_x <= x"15"; + when EHDR => bsm_x <= x"16"; + when CDEL0 => bsm_x <= x"17"; + when CDEL1 => bsm_x <= x"18"; + when CCNT => bsm_x <= x"19"; + when DEL0 => bsm_x <= x"20"; + when DEL1 => bsm_x <= x"21"; + when DEL2 => bsm_x <= x"22"; + when WHDR => bsm_x <= x"23"; + when others => bsm_x <= x"ff"; end case; end process STATE_DECODE; @@ -581,24 +613,6 @@ end process THE_HALF_PROC; raw_addr <= buf_half & buf_addr; ---------------------------------------------------------------------------- --- threshold address counter ---------------------------------------------------------------------------- -THE_THR_ADDR_COUNTER_PROC: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - if ( (thr_addr_rst = '1') or (reset_in = '1') ) then - thr_addr <= (others => '0'); - elsif( thr_addr_ce = '1' ) then - thr_addr <= thr_addr + 1; - end if; - end if; -end process THE_THR_ADDR_COUNTER_PROC; - --- was '3' -thr_addr_ce <= dly_thr_addr_ce(2); -thr_addr_rst <= dly_thr_addr_rst(2); - --------------------------------------------------------------------------- -- local frame counter, loaded / counted by SM for checking --------------------------------------------------------------------------- @@ -641,177 +655,168 @@ begin cleaned_up <= next_cleaned_up; buf_addr_done <= next_buf_addr_done; buf_frame_valid <= frame_valid; - buf_raw_addr <= raw_addr; small_0_sum <= next_small_0_sum; small_1_sum <= next_small_1_sum; - dly_thr_addr_ce(7 downto 0) <= dly_thr_addr_ce(6 downto 0) & buf_addr_ce; - dly_thr_addr_rst(7 downto 0) <= dly_thr_addr_rst(6 downto 0) & buf_addr_init; + max_num_words <= next_max_num_words; + thr_addr_qqq <= thr_addr_qq; + thr_addr_qq <= thr_addr_q; + thr_addr_q <= buf_raw_addr; + buf_raw_addr <= raw_addr; end if; end process THE_SYNC_PROC; --------------------------------------------------------------------------- --- DHDR information assembly ---------------------------------------------------------------------------- -dhdr_data_out(31 downto 29) <= "000"; -- reserved bits -dhdr_data_out(28) <= '1'; -- packbit -dhdr_data_out(27 downto 24) <= eds_data_in(7 downto 4); -dhdr_data_out(23 downto 16) <= eds_data_in(15 downto 8); -dhdr_data_out(15 downto 0) <= eds_data_in(31 downto 16); - -dhdr_length_out <= total_sum; - -dhdr_store_out <= eds_wr; - ---########################################################################## ---########################################################################## - -- generate TimeOutCounters for all 16 APVs +--------------------------------------------------------------------------- GEN_TOC: for i in 0 to 15 generate THE_BUF_TOC: buf_toc - port map( CLK_IN => clk_in, - RESET_IN => reset_in, - BUF_TICK_IN => buf_tick_in(i), - BUF_START_IN => buf_start_in(i), - WAITFRAME_IN => wait_frames, - FRAMES_REQD_IN => eds_data_in(35 downto 32), -- always the same - BUF_LVL_IN => raw_data(i)(37 downto 30), - GOODDATA_OUT => buf_gooddata(i), - BADDATA_OUT => buf_baddata(i), - NODATA_OUT => buf_nodata(i), - READY_OUT => buf_ready(i), - BSM_OUT => open, - DBG_OUT => open - ); + port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + BUF_TICK_IN => buf_tick_in(i), + BUF_START_IN => buf_start_in(i), + WAITFRAME_IN => wait_frames, + FRAMES_REQD_IN => eds_data_in(35 downto 32), -- always the same + BUF_LVL_IN => raw_data(i)(37 downto 30), + GOODDATA_OUT => buf_gooddata(i), + BADDATA_OUT => buf_baddata(i), + NODATA_OUT => buf_nodata(i), + READY_OUT => buf_ready(i), + BSM_OUT => open, + DBG_OUT => open + ); end generate GEN_TOC; +--------------------------------------------------------------------------- -- generate ALUs for all 16 APV data streams +--------------------------------------------------------------------------- GEN_ALU: for i in 0 to 15 generate THE_ALU: apv_pc_nc_alu - port map( CLK_IN => clk_in, - RESET_IN => reset_in, - START_IN => ld_frm_ctr, - MAX_FRAMES_IN => eds_data_in(35 downto 32), - CURR_FRAME_IN => done_ctr, - LOC_FRM_CTR_IN => loc_frm_ctr, -- DEBUG - EDS_FRM_CTR_IN => eds_data_in(39 downto 36), -- DEBUG - BUF_GOOD_IN => buf_gooddata(i), - BUF_BAD_IN => buf_baddata(i), - BUF_IGNORE_IN => buf_nodata(i), - ERROR_IN => errors, - DO_HEADER_IN => do_hdr, - DO_ERROR_IN => do_error, - EVT_TYPE_IN => eds_data_in(6 downto 4), --evt_type_in, -- just a quick fix, does not work lateron! - RAW_ADDR_IN => buf_raw_addr, -- delayed by one cycle - RAW_DATA_IN => raw_data(i), - PED_DATA_IN => ped_data(i), - THR_DATA_IN => thr_data(i), - FRAME_IN => buf_frame_valid, -- delayed by one cycle - FIFO_DATA_OUT => fifo_data(i)(26 downto 0), - WE_OUT => fifo_we(i), - COUNT_OUT => fifo_data(i)(36 downto 27), - ANYDATA_OUT => fifo_data(i)(37), - DBG_OUT => open - ); - fifo_data(i)(39) <= '0'; - fifo_data(i)(38) <= '0'; + port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + START_IN => ld_frm_ctr, + MAX_FRAMES_IN => eds_data_in(35 downto 32), + CURR_FRAME_IN => done_ctr, + LOC_FRM_CTR_IN => loc_frm_ctr, -- DEBUG + EDS_FRM_CTR_IN => eds_data_in(39 downto 36), -- DEBUG + BUF_GOOD_IN => buf_gooddata(i), + BUF_BAD_IN => buf_baddata(i), + BUF_IGNORE_IN => buf_nodata(i), + ERROR_IN => errors, + DO_HEADER_IN => do_hdr, + DO_ERROR_IN => do_error, + SUPPRESS_IN => eds_data_in(3), -- suppress bit + EVT_TYPE_IN => eds_data_in(2 downto 0), -- RICH data configuration bits + RAW_ADDR_IN => buf_raw_addr, -- delayed by one cycle + RAW_DATA_IN => raw_data(i), + PED_DATA_IN => ped_data(i), + THR_DATA_IN => thr_data(i), + FRAME_IN => buf_frame_valid, -- delayed by one cycle + FIFO_DATA_OUT => fifo_data(i)(26 downto 0), + WE_OUT => fifo_we(i), + COUNT_OUT => fifo_data(i)(36 downto 27), + ANYDATA_OUT => fifo_data(i)(37), + DBG_OUT => open + ); + fifo_data(i)(39) <= '0'; + fifo_data(i)(38) <= '0'; end generate GEN_ALU; frame_busy <= fifo_data(0)(26); -- WORKAROUND! ---################################################################################## --------------------------------------------------------------------------- -- Sum up all data words of one event --------------------------------------------------------------------------- THE_DECODER_0: decoder_8bit -port map( ADDRESS => fifo_we(7 downto 0), - Q => next_small_0_sum(3 downto 0) - ); +port map( + ADDRESS => fifo_we(7 downto 0), + Q => next_small_0_sum(3 downto 0) +); next_small_0_sum(4) <= '0'; THE_DECODER_1: decoder_8bit -port map( ADDRESS => fifo_we(15 downto 8), - Q => next_small_1_sum(3 downto 0) - ); +port map( + ADDRESS => fifo_we(15 downto 8), + Q => next_small_1_sum(3 downto 0) +); next_small_1_sum(4) <= '0'; reset_sum <= reset_in or ld_frm_ctr; THE_FIRST_ADDER: adder_5bit -port map( DATAA => small_0_sum, - DATAB => small_1_sum, - CLOCK => clk_in, - RESET => reset_sum, -- BUG - CLOCKEN => '1', - RESULT => small_sum(4 downto 0) - ); +port map( + DATAA => small_0_sum, + DATAB => small_1_sum, + CLOCK => clk_in, + RESET => reset_sum, -- BUG + CLOCKEN => '1', + RESULT => small_sum(4 downto 0) +); small_sum(15 downto 5) <= (others => '0'); THE_ACCUMULATOR: adder_16bit -port map( DATAA => small_sum, - DATAB => total_sum, - CLOCK => clk_in, - RESET => reset_sum, -- BUG - CLOCKEN => '1', - RESULT => total_sum - ); - -fifo_we_out <= fifo_we; -fifo_start_out <= do_start; -fifo_done_out <= eds_wr; ---################################################################################## - - --- Aliasing the data output -fifo_0_data_out <= fifo_data(0); -fifo_1_data_out <= fifo_data(1); -fifo_2_data_out <= fifo_data(2); -fifo_3_data_out <= fifo_data(3); -fifo_4_data_out <= fifo_data(4); -fifo_5_data_out <= fifo_data(5); -fifo_6_data_out <= fifo_data(6); -fifo_7_data_out <= fifo_data(7); -fifo_8_data_out <= fifo_data(8); -fifo_9_data_out <= fifo_data(9); -fifo_10_data_out <= fifo_data(10); -fifo_11_data_out <= fifo_data(11); -fifo_12_data_out <= fifo_data(12); -fifo_13_data_out <= fifo_data(13); -fifo_14_data_out <= fifo_data(14); -fifo_15_data_out <= fifo_data(15); +port map( + DATAA => small_sum, + DATAB => total_sum, + CLOCK => clk_in, + RESET => reset_sum, -- BUG + CLOCKEN => '1', + RESULT => total_sum +); + --------------------------------------------------------------------------- +-- DHDR information assembly --------------------------------------------------------------------------- -debug(15) <= frame_valid; -debug(14) <= buf_frame_valid; -debug(13 downto 0) <= (others => '0'); ---debug(15) <= last_frame; ---debug(14) <= cleaned_up; ---debug(13 downto 12) <= (others => '0'); ---debug(11 downto 8) <= loc_frm_ctr; ---debug(7 downto 4) <= to_do_ctr; ---debug(3 downto 0) <= done_ctr; +DHDR_DATA_OUT(31 downto 29) <= "000"; -- reserved bits +DHDR_DATA_OUT(28) <= '0'; -- packbit, MUST NEVER BE SET IN FEs +DHDR_DATA_OUT(27 downto 24) <= eds_data_in(7 downto 4); +DHDR_DATA_OUT(23 downto 16) <= eds_data_in(15 downto 8); +DHDR_DATA_OUT(15 downto 0) <= eds_data_in(31 downto 16); +DHDR_LENGTH_OUT <= total_sum; +DHDR_STORE_OUT <= eds_wr; + --------------------------------------------------------------------------- +-- Output signals --------------------------------------------------------------------------- - +FIFO_0_DATA_OUT <= fifo_data(0); +FIFO_1_DATA_OUT <= fifo_data(1); +FIFO_2_DATA_OUT <= fifo_data(2); +FIFO_3_DATA_OUT <= fifo_data(3); +FIFO_4_DATA_OUT <= fifo_data(4); +FIFO_5_DATA_OUT <= fifo_data(5); +FIFO_6_DATA_OUT <= fifo_data(6); +FIFO_7_DATA_OUT <= fifo_data(7); +FIFO_8_DATA_OUT <= fifo_data(8); +FIFO_9_DATA_OUT <= fifo_data(9); +FIFO_10_DATA_OUT <= fifo_data(10); +FIFO_11_DATA_OUT <= fifo_data(11); +FIFO_12_DATA_OUT <= fifo_data(12); +FIFO_13_DATA_OUT <= fifo_data(13); +FIFO_14_DATA_OUT <= fifo_data(14); +FIFO_15_DATA_OUT <= fifo_data(15); +FIFO_WE_OUT <= fifo_we; +FIFO_START_OUT <= do_start; +FIFO_DONE_OUT <= eds_wr; +EDS_DONE_OUT <= eds_done; +BUF_DONE_OUT <= buf_done; +BUF_ADDR_OUT <= raw_addr; +PED_ADDR_OUT <= raw_addr; +THR_ADDR_OUT <= thr_addr_qqq; +FIFO_SPACE_REQ_OUT <= max_num_words; --------------------------------------------------------------------------- --- Output signals +-- Debug signals --------------------------------------------------------------------------- -eds_done_out <= eds_done; -buf_done_out <= buf_done; -buf_addr_out <= raw_addr; -ped_addr_out <= raw_addr; -thr_addr_out <= thr_addr; +debug(15) <= frame_valid; +debug(14) <= buf_frame_valid; +debug(13 downto 0) <= (others => '0'); --------------------------------------------------------------------------- -- DEBUG signals --------------------------------------------------------------------------- -dbg_bsm_out <= bsm_x; -dbg_out <= debug; +DBG_BSM_OUT <= bsm_x; +DBG_OUT <= debug; end behavioral; - - - - - diff --git a/src/pulse_stretch.vhd b/src/pulse_stretch.vhd index df8b3a8..27fb8a6 100644 --- a/src/pulse_stretch.vhd +++ b/src/pulse_stretch.vhd @@ -1,29 +1,30 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.adcmv3_components.all; entity pulse_stretch is - port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - START_IN : in std_logic; - PULSE_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + PULSE_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of pulse_stretch is - -- normal signals - signal pulse_cnt : std_logic_vector(3 downto 0); - signal pulse_cnt_ce : std_logic; - signal pulse_x : std_logic; - signal pulse : std_logic; - -begin +-- normal signals +signal pulse_cnt : std_logic_vector(3 downto 0); +signal pulse_cnt_ce : std_logic; +signal pulse_x : std_logic; +signal pulse : std_logic; + +begin -- Pulse length counter THE_PULSE_LENGTH_CTR: process( clk_in ) @@ -50,13 +51,13 @@ begin else pulse <= pulse_x; end if; - end if; + end if; end process THE_SYNC_PROC; -- output signals pulse_out <= pulse; -debug_out(15 downto 4) <= (others => '0'); +debug_out(15 downto 4) <= (others => '0'); debug_out(3 downto 0) <= pulse_cnt; -end behavioral; +end behavioral; diff --git a/src/pulse_sync.vhd b/src/pulse_sync.vhd index 70164f6..dfdd7f4 100644 --- a/src/pulse_sync.vhd +++ b/src/pulse_sync.vhd @@ -7,24 +7,25 @@ library work; use work.adcmv3_components.all; entity pulse_sync is - port( CLK_A_IN : in std_logic; - RESET_A_IN : in std_logic; - PULSE_A_IN : in std_logic; - CLK_B_IN : in std_logic; - RESET_B_IN : in std_logic; - PULSE_B_OUT : out std_logic - ); +port( + CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic +); end; architecture behavioral of pulse_sync is - -- normal signals - signal toggle_ff : std_logic; - signal sync_q : std_logic; - signal sync_qq : std_logic; - signal sync_qqq : std_logic; - signal pulse_b : std_logic; - +-- normal signals +signal toggle_ff : std_logic; +signal sync_q : std_logic; +signal sync_qq : std_logic; +signal sync_qqq : std_logic; +signal pulse_b : std_logic; + begin -- toggle flip flop in clock domain A diff --git a/src/raw_buf_stage_new.vhd b/src/raw_buf_stage_new.vhd index bef706b..55d9745 100755 --- a/src/raw_buf_stage_new.vhd +++ b/src/raw_buf_stage_new.vhd @@ -7,113 +7,114 @@ library work; use work.adcmv3_components.all; entity raw_buf_stage_new is - port( CLK_IN : in std_logic; -- 100MHz local clock - CLK_APV_IN : in std_logic; -- 40MHz APV clock - RESET_IN : in std_logic; -- general reset (100MHz) - -- trigger related signals - APV_RESET_IN : in std_logic; -- APV reset signal (100MHz) - APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz) - APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz) - -- ADC0 signals - ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid - ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0 - ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1 - ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2 - ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3 - ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4 - ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5 - ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6 - ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7 - -- ADC1 signals - ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid - ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0 - ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1 - ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2 - ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3 - ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4 - ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5 - ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6 - ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7 - -- Slow control registers - MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event - BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold - BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold - FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold - FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold - APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control - -- 100MHZ synchronous interface - BUF_FULL_OUT : out std_logic; - BUF_ADDR_IN : in std_logic_vector(6 downto 0); - BUF_DONE_IN : in std_logic; - BUF_TICK_OUT : out std_logic_vector(15 downto 0); - BUF_START_OUT : out std_logic_vector(15 downto 0); - BUF_READY_OUT : out std_logic_vector(15 downto 0); - BUF_0_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_1_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_2_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_3_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_4_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_5_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_6_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_7_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_8_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_9_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_10_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_11_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_12_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_13_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_14_DATA_OUT : out std_logic_vector(37 downto 0); - BUF_15_DATA_OUT : out std_logic_vector(37 downto 0); - -- Debug signals - DEBUG_OUT : out std_logic_vector(63 downto 0) - ); +port( + CLK_IN : in std_logic; -- 100MHz local clock + CLK_APV_IN : in std_logic; -- 40MHz APV clock + RESET_IN : in std_logic; -- general reset (100MHz) + -- trigger related signals + APV_RESET_IN : in std_logic; -- APV reset signal (100MHz) + APV_SYNC_IN : in std_logic; -- APV sync trigger has been sent (40MHz) + APV_FRAME_REQD_IN : in std_logic; -- one APV frame has been requested (100MHz) + -- ADC0 signals + ADC0_VALID_IN : in std_logic; -- 40M reconstructed clock is valid + ADC0_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 0 + ADC0_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 1 + ADC0_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 2 + ADC0_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 3 + ADC0_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 4 + ADC0_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 5 + ADC0_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 6 + ADC0_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC0 channel 7 + -- ADC1 signals + ADC1_VALID_IN : in std_logic; -- 40M reconstructed clock is valid + ADC1_0_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 0 + ADC1_1_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 1 + ADC1_2_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 2 + ADC1_3_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 3 + ADC1_4_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 4 + ADC1_5_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 5 + ADC1_6_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 6 + ADC1_7_DATA_IN : in std_logic_vector(11 downto 0); -- parallel data from ADC1 channel 7 + -- Slow control registers + MAX_TRG_NUM_IN : in std_logic_vector(3 downto 0); -- maximum number of triggers / event + BIT_LOW_IN : in std_logic_vector(11 downto 0); -- "bit low" threshold + BIT_HIGH_IN : in std_logic_vector(11 downto 0); -- "bit high" threshold + FL_LOW_IN : in std_logic_vector(11 downto 0); -- "flatline low" threshold + FL_HIGH_IN : in std_logic_vector(11 downto 0); -- "flatline high" threshold + APV_ON_IN : in std_logic_vector(15 downto 0); -- APV on/off bits from slow control + -- 100MHZ synchronous interface + BUF_FULL_OUT : out std_logic; + BUF_ADDR_IN : in std_logic_vector(6 downto 0); + BUF_DONE_IN : in std_logic; + BUF_TICK_OUT : out std_logic_vector(15 downto 0); + BUF_START_OUT : out std_logic_vector(15 downto 0); + BUF_READY_OUT : out std_logic_vector(15 downto 0); + BUF_0_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_1_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_2_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_3_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_4_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_5_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_6_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_7_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_8_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_9_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_10_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_11_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_12_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_13_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_14_DATA_OUT : out std_logic_vector(37 downto 0); + BUF_15_DATA_OUT : out std_logic_vector(37 downto 0); + -- Debug signals + DEBUG_OUT : out std_logic_vector(63 downto 0) +); end; architecture behavioral of raw_buf_stage_new is - -- Reset signals, combinatorial and registered - signal next_reset_all : std_logic; - signal reset_all : std_logic; -- 40MHz clock domain - signal next_reset : std_logic; - signal reset : std_logic; -- 100MHz clock domain - - -- APV locker signals (arrays / vectors) - type adc_data_t is array (0 to 15) of std_logic_vector(11 downto 0); - signal adc_data : adc_data_t; - type apv_status_t is array (0 to 15) of std_logic_vector(7 downto 0); - signal apv_status : apv_status_t; - type apv_frame_t is array (0 to 15) of std_logic_vector(11 downto 0); - signal apv_frame : apv_frame_t; - type apv_channel_t is array (0 to 15) of std_logic_vector(6 downto 0); - signal apv_channel : apv_channel_t; - type apv_data_t is array (0 to 15) of std_logic_vector(17 downto 0); - signal apv_data : apv_data_t; - - signal apv_analog : std_logic_vector(15 downto 0); - signal apv_start : std_logic_vector(15 downto 0); - signal apv_last : std_logic_vector(15 downto 0); - - -- Buffer signals (arrays / vectors) - type buf_data_t is array (0 to 15) of std_logic_vector(17 downto 0); - signal buf_data : buf_data_t; - type buf_status_t is array (0 to 15) of std_logic_vector(7 downto 0); - signal buf_status : buf_status_t; - type buf_frame_t is array (0 to 15) of std_logic_vector(11 downto 0); - signal buf_frame : buf_frame_t; - type buf_level_t is array (0 to 15) of std_logic_vector(7 downto 0); - signal buf_level : buf_level_t; - - signal buf_tick : std_logic_vector(15 downto 0); - signal buf_start : std_logic_vector(15 downto 0); - signal buf_ready : std_logic_vector(15 downto 0); - signal buf_full : std_logic_vector(15 downto 0); - - signal next_raw_buf_full : std_logic; - signal raw_buf_full : std_logic; - - -- Debug - signal debug : std_logic_vector(63 downto 0); - +-- Reset signals, combinatorial and registered +signal next_reset_all : std_logic; +signal reset_all : std_logic; -- 40MHz clock domain +signal next_reset : std_logic; +signal reset : std_logic; -- 100MHz clock domain + +-- APV locker signals (arrays / vectors) +type adc_data_t is array (0 to 15) of std_logic_vector(11 downto 0); +signal adc_data : adc_data_t; +type apv_status_t is array (0 to 15) of std_logic_vector(7 downto 0); +signal apv_status : apv_status_t; +type apv_frame_t is array (0 to 15) of std_logic_vector(11 downto 0); +signal apv_frame : apv_frame_t; +type apv_channel_t is array (0 to 15) of std_logic_vector(6 downto 0); +signal apv_channel : apv_channel_t; +type apv_data_t is array (0 to 15) of std_logic_vector(17 downto 0); +signal apv_data : apv_data_t; + +signal apv_analog : std_logic_vector(15 downto 0); +signal apv_start : std_logic_vector(15 downto 0); +signal apv_last : std_logic_vector(15 downto 0); + +-- Buffer signals (arrays / vectors) +type buf_data_t is array (0 to 15) of std_logic_vector(17 downto 0); +signal buf_data : buf_data_t; +type buf_status_t is array (0 to 15) of std_logic_vector(7 downto 0); +signal buf_status : buf_status_t; +type buf_frame_t is array (0 to 15) of std_logic_vector(11 downto 0); +signal buf_frame : buf_frame_t; +type buf_level_t is array (0 to 15) of std_logic_vector(7 downto 0); +signal buf_level : buf_level_t; + +signal buf_tick : std_logic_vector(15 downto 0); +signal buf_start : std_logic_vector(15 downto 0); +signal buf_ready : std_logic_vector(15 downto 0); +signal buf_full : std_logic_vector(15 downto 0); + +signal next_raw_buf_full : std_logic; +signal raw_buf_full : std_logic; + +-- Debug +signal debug : std_logic_vector(63 downto 0); + begin --------------------------------------------------------------------------- @@ -140,15 +141,16 @@ debug(3 downto 0) <= apv_data(0)(17 downto 14); --------------------------------------------------------------------------- -- Reset handling --------------------------------------------------------------------------- -next_reset_all <= (reset_in or apv_reset_in); -- 40MHz clock domain +next_reset_all <= (reset_in or apv_reset_in); -- 40MHz clock domain next_reset <= (reset_in or apv_reset_in); -- 100MHz clock domain THE_RESET_SYNC: state_sync -port map( STATE_A_IN => next_reset_all, - CLK_B_IN => clk_apv_in, - RESET_B_IN => '0', - STATE_B_OUT => reset_all - ); +port map( + STATE_A_IN => next_reset_all, + CLK_B_IN => clk_apv_in, + RESET_B_IN => '0', + STATE_B_OUT => reset_all +); --------------------------------------------------------------------------- @@ -184,70 +186,72 @@ GEN_ADC0: for i in 0 to 7 generate -- APV locker, handles synchronisation and all the other stuff THE_APV_LOCKER: apv_locker - port map( CLK_APV_IN => clk_apv_in, - RESET_IN => reset_all, - SYNC_IN => apv_sync_in, - ADC_RAW_IN => adc_data(i), - ADC_VALID_IN => adc0_valid_in, - APV_ON_IN => apv_on_in(i), - BIT_LOW_IN => bit_low_in, - BIT_HIGH_IN => bit_high_in, - FL_LOW_IN => fl_low_in, - FL_HIGH_IN => fl_high_in, - STATUS_IGNORE_OUT => apv_status(i)(1), - STATUS_UNKNOWN_OUT => apv_status(i)(6), - STATUS_BADADC_OUT => apv_status(i)(7), - STATUS_LOCKED_OUT => apv_status(i)(5), - STATUS_LOST_OUT => apv_status(i)(4), - STATUS_NOSYNC_OUT => apv_status(i)(3), - STATUS_MISSING_OUT => apv_status(i)(2), - STATUS_TICKMARK_OUT => apv_status(i)(0), - FRAME_ROW_OUT => apv_frame(i)(7 downto 0), - FRAME_ERROR_OUT => apv_frame(i)(8), - FRAME_OVF_OUT => apv_frame(i)(9), - FRAME_UDF_OUT => apv_frame(i)(10), - FRAME_FLAT_OUT => apv_frame(i)(11), - FRAME_CTR_OUT => apv_data(i)(17 downto 14), - APV_CHANNEL_OUT => apv_channel(i), - APV_OVERFLOW_OUT => apv_data(i)(13), - APV_UNDERFLOW_OUT => apv_data(i)(12), - APV_RAW_OUT => apv_data(i)(11 downto 0), - APV_ANALOG_OUT => apv_analog(i), - APV_START_OUT => apv_start(i), - APV_LAST_OUT => apv_last(i), - DEBUG_OUT => open - ); - + port map( + CLK_APV_IN => clk_apv_in, + RESET_IN => reset_all, + SYNC_IN => apv_sync_in, + ADC_RAW_IN => adc_data(i), + ADC_VALID_IN => adc0_valid_in, + APV_ON_IN => apv_on_in(i), + BIT_LOW_IN => bit_low_in, + BIT_HIGH_IN => bit_high_in, + FL_LOW_IN => fl_low_in, + FL_HIGH_IN => fl_high_in, + STATUS_IGNORE_OUT => apv_status(i)(1), + STATUS_UNKNOWN_OUT => apv_status(i)(6), + STATUS_BADADC_OUT => apv_status(i)(7), + STATUS_LOCKED_OUT => apv_status(i)(5), + STATUS_LOST_OUT => apv_status(i)(4), + STATUS_NOSYNC_OUT => apv_status(i)(3), + STATUS_MISSING_OUT => apv_status(i)(2), + STATUS_TICKMARK_OUT => apv_status(i)(0), + FRAME_ROW_OUT => apv_frame(i)(7 downto 0), + FRAME_ERROR_OUT => apv_frame(i)(8), + FRAME_OVF_OUT => apv_frame(i)(9), + FRAME_UDF_OUT => apv_frame(i)(10), + FRAME_FLAT_OUT => apv_frame(i)(11), + FRAME_CTR_OUT => apv_data(i)(17 downto 14), + APV_CHANNEL_OUT => apv_channel(i), + APV_OVERFLOW_OUT => apv_data(i)(13), + APV_UNDERFLOW_OUT => apv_data(i)(12), + APV_RAW_OUT => apv_data(i)(11 downto 0), + APV_ANALOG_OUT => apv_analog(i), + APV_START_OUT => apv_start(i), + APV_LAST_OUT => apv_last(i), + DEBUG_OUT => open + ); + -- raw buffer, stores frame data, all outputs are 100MHz synchronized THE_APV_RAW_BUFFER: apv_raw_buffer - port map( CLK_APV_IN => clk_apv_in, - RESET_IN => reset_all, - FRM_REQD_IN => apv_frame_reqd_in, - MAX_TRG_NUM_IN => max_trg_num_in, - ADC_ANALOG_IN => apv_analog(i), - ADC_START_IN => apv_start(i), - ADC_LAST_IN => apv_last(i), - ADC_CHANNEL_IN => apv_channel(i), - ADC_RAW_IN => apv_data(i), - ADC_STATUS_IN => apv_status(i), - ADC_FRAME_IN => apv_frame(i), - BUF_CLK_IN => clk_in, - BUF_RESET_IN => reset, - BUF_START_OUT => buf_start(i), - BUF_READY_OUT => buf_ready(i), - BUF_ADDR_IN => buf_addr_in, - BUF_DONE_IN => buf_done_in, - BUF_DATA_OUT => buf_data(i), - BUF_STATUS_OUT => buf_status(i), - BUF_FRAME_OUT => buf_frame(i), - BUF_GOOD_OUT => buf_level(i)(7), - BUF_BROKEN_OUT => buf_level(i)(6), - BUF_IGNORE_OUT => buf_level(i)(5), - BUF_LEVEL_OUT => buf_level(i)(4 downto 0), - BUF_TICKMARK_OUT => buf_tick(i), - BUF_FULL_OUT => buf_full(i), - DEBUG_OUT => open - ); + port map( + CLK_APV_IN => clk_apv_in, + RESET_IN => reset_all, + FRM_REQD_IN => apv_frame_reqd_in, + MAX_TRG_NUM_IN => max_trg_num_in, + ADC_ANALOG_IN => apv_analog(i), + ADC_START_IN => apv_start(i), + ADC_LAST_IN => apv_last(i), + ADC_CHANNEL_IN => apv_channel(i), + ADC_RAW_IN => apv_data(i), + ADC_STATUS_IN => apv_status(i), + ADC_FRAME_IN => apv_frame(i), + BUF_CLK_IN => clk_in, + BUF_RESET_IN => reset, + BUF_START_OUT => buf_start(i), + BUF_READY_OUT => buf_ready(i), + BUF_ADDR_IN => buf_addr_in, + BUF_DONE_IN => buf_done_in, + BUF_DATA_OUT => buf_data(i), + BUF_STATUS_OUT => buf_status(i), + BUF_FRAME_OUT => buf_frame(i), + BUF_GOOD_OUT => buf_level(i)(7), + BUF_BROKEN_OUT => buf_level(i)(6), + BUF_IGNORE_OUT => buf_level(i)(5), + BUF_LEVEL_OUT => buf_level(i)(4 downto 0), + BUF_TICKMARK_OUT => buf_tick(i), + BUF_FULL_OUT => buf_full(i), + DEBUG_OUT => open + ); end generate GEN_ADC0; @@ -270,70 +274,72 @@ GEN_ADC1: for i in 8 to 15 generate -- APV locker, handles synchronisation and all the other stuff THE_APV_LOCKER: apv_locker - port map( CLK_APV_IN => clk_apv_in, - RESET_IN => reset_all, - SYNC_IN => apv_sync_in, - ADC_RAW_IN => adc_data(i), - ADC_VALID_IN => adc1_valid_in, - APV_ON_IN => apv_on_in(i), - BIT_LOW_IN => bit_low_in, - BIT_HIGH_IN => bit_high_in, - FL_LOW_IN => fl_low_in, - FL_HIGH_IN => fl_high_in, - STATUS_IGNORE_OUT => apv_status(i)(1), - STATUS_UNKNOWN_OUT => apv_status(i)(6), - STATUS_BADADC_OUT => apv_status(i)(7), - STATUS_LOCKED_OUT => apv_status(i)(5), - STATUS_LOST_OUT => apv_status(i)(4), - STATUS_NOSYNC_OUT => apv_status(i)(3), - STATUS_MISSING_OUT => apv_status(i)(2), - STATUS_TICKMARK_OUT => apv_status(i)(0), - FRAME_ROW_OUT => apv_frame(i)(7 downto 0), - FRAME_ERROR_OUT => apv_frame(i)(8), - FRAME_OVF_OUT => apv_frame(i)(9), - FRAME_UDF_OUT => apv_frame(i)(10), - FRAME_FLAT_OUT => apv_frame(i)(11), - FRAME_CTR_OUT => apv_data(i)(17 downto 14), - APV_CHANNEL_OUT => apv_channel(i), - APV_OVERFLOW_OUT => apv_data(i)(13), - APV_UNDERFLOW_OUT => apv_data(i)(12), - APV_RAW_OUT => apv_data(i)(11 downto 0), - APV_ANALOG_OUT => apv_analog(i), - APV_START_OUT => apv_start(i), - APV_LAST_OUT => apv_last(i), - DEBUG_OUT => open - ); - + port map( + CLK_APV_IN => clk_apv_in, + RESET_IN => reset_all, + SYNC_IN => apv_sync_in, + ADC_RAW_IN => adc_data(i), + ADC_VALID_IN => adc1_valid_in, + APV_ON_IN => apv_on_in(i), + BIT_LOW_IN => bit_low_in, + BIT_HIGH_IN => bit_high_in, + FL_LOW_IN => fl_low_in, + FL_HIGH_IN => fl_high_in, + STATUS_IGNORE_OUT => apv_status(i)(1), + STATUS_UNKNOWN_OUT => apv_status(i)(6), + STATUS_BADADC_OUT => apv_status(i)(7), + STATUS_LOCKED_OUT => apv_status(i)(5), + STATUS_LOST_OUT => apv_status(i)(4), + STATUS_NOSYNC_OUT => apv_status(i)(3), + STATUS_MISSING_OUT => apv_status(i)(2), + STATUS_TICKMARK_OUT => apv_status(i)(0), + FRAME_ROW_OUT => apv_frame(i)(7 downto 0), + FRAME_ERROR_OUT => apv_frame(i)(8), + FRAME_OVF_OUT => apv_frame(i)(9), + FRAME_UDF_OUT => apv_frame(i)(10), + FRAME_FLAT_OUT => apv_frame(i)(11), + FRAME_CTR_OUT => apv_data(i)(17 downto 14), + APV_CHANNEL_OUT => apv_channel(i), + APV_OVERFLOW_OUT => apv_data(i)(13), + APV_UNDERFLOW_OUT => apv_data(i)(12), + APV_RAW_OUT => apv_data(i)(11 downto 0), + APV_ANALOG_OUT => apv_analog(i), + APV_START_OUT => apv_start(i), + APV_LAST_OUT => apv_last(i), + DEBUG_OUT => open + ); + -- raw buffer, stores frame data, all outputs are 100MHz synchronized THE_APV_RAW_BUFFER: apv_raw_buffer - port map( CLK_APV_IN => clk_apv_in, - RESET_IN => reset_all, - FRM_REQD_IN => apv_frame_reqd_in, - MAX_TRG_NUM_IN => max_trg_num_in, - ADC_ANALOG_IN => apv_analog(i), - ADC_START_IN => apv_start(i), - ADC_LAST_IN => apv_last(i), - ADC_CHANNEL_IN => apv_channel(i), - ADC_RAW_IN => apv_data(i), - ADC_STATUS_IN => apv_status(i), - ADC_FRAME_IN => apv_frame(i), - BUF_CLK_IN => clk_in, - BUF_RESET_IN => reset, - BUF_START_OUT => buf_start(i), - BUF_READY_OUT => buf_ready(i), - BUF_ADDR_IN => buf_addr_in, - BUF_DONE_IN => buf_done_in, - BUF_DATA_OUT => buf_data(i), - BUF_STATUS_OUT => buf_status(i), - BUF_FRAME_OUT => buf_frame(i), - BUF_GOOD_OUT => buf_level(i)(7), - BUF_BROKEN_OUT => buf_level(i)(6), - BUF_IGNORE_OUT => buf_level(i)(5), - BUF_LEVEL_OUT => buf_level(i)(4 downto 0), - BUF_TICKMARK_OUT => buf_tick(i), - BUF_FULL_OUT => buf_full(i), - DEBUG_OUT => open - ); + port map( + CLK_APV_IN => clk_apv_in, + RESET_IN => reset_all, + FRM_REQD_IN => apv_frame_reqd_in, + MAX_TRG_NUM_IN => max_trg_num_in, + ADC_ANALOG_IN => apv_analog(i), + ADC_START_IN => apv_start(i), + ADC_LAST_IN => apv_last(i), + ADC_CHANNEL_IN => apv_channel(i), + ADC_RAW_IN => apv_data(i), + ADC_STATUS_IN => apv_status(i), + ADC_FRAME_IN => apv_frame(i), + BUF_CLK_IN => clk_in, + BUF_RESET_IN => reset, + BUF_START_OUT => buf_start(i), + BUF_READY_OUT => buf_ready(i), + BUF_ADDR_IN => buf_addr_in, + BUF_DONE_IN => buf_done_in, + BUF_DATA_OUT => buf_data(i), + BUF_STATUS_OUT => buf_status(i), + BUF_FRAME_OUT => buf_frame(i), + BUF_GOOD_OUT => buf_level(i)(7), + BUF_BROKEN_OUT => buf_level(i)(6), + BUF_IGNORE_OUT => buf_level(i)(5), + BUF_LEVEL_OUT => buf_level(i)(4 downto 0), + BUF_TICKMARK_OUT => buf_tick(i), + BUF_FULL_OUT => buf_full(i), + DEBUG_OUT => open + ); end generate GEN_ADC1; @@ -343,9 +349,9 @@ end generate GEN_ADC1; --------------------------------------------------------------------------- buf_full_out <= raw_buf_full; -buf_tick_out <= buf_tick; -- needed for TOCs -buf_start_out <= buf_start; -- needed for TOCs -buf_ready_out <= buf_ready; -- debug signal +buf_tick_out <= buf_tick; -- needed for TOCs +buf_start_out <= buf_start; -- needed for TOCs +buf_ready_out <= buf_ready; -- debug signal -- Alias the outputs from generator buf_0_data_out(17 downto 0) <= buf_data(0); @@ -405,6 +411,6 @@ debug_out <= debug; end behavioral; - + diff --git a/src/real_trg_handler.vhd b/src/real_trg_handler.vhd index bb7ed5c..e1d06f5 100755 --- a/src/real_trg_handler.vhd +++ b/src/real_trg_handler.vhd @@ -12,105 +12,108 @@ use work.adcmv3_components.all; -- (2) no more rst_lvl1_counter signal anymore in the CCR. to be replaced! entity real_trg_handler is - port( CLK_IN : in std_logic; -- 100MHz master clock - RESET_IN : in std_logic; - TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs - TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs - APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse) - TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 - TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 - TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 - TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 - TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers - TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint - -- TRB LVL1 channel signals - TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag - TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number - TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 trigger type - TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB - TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger - RST_LVL1_COUNTER_IN : in std_logic; -- reset LVL1 counter - LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); - BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator - -- - APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine - APV_TRGSTART_OUT : out std_logic; -- start an APV trigger state machine - EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data - EDS_WE_OUT : out std_logic; -- EDS write enable (general interface) - EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level - EDS_READY_OUT : out std_logic; -- APV trigger sequence done - DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself - BSM_OUT : out std_logic_vector(7 downto 0); - DEBUG_OUT : out std_logic_vector(63 downto 0) - ); +port( + CLK_IN : in std_logic; -- 100MHz master clock + RESET_IN : in std_logic; + TIME_TRG_IN : in std_logic_vector(3 downto 0); -- timing trigger inputs + TRB_TRG_IN : in std_logic_vector(3 downto 0); -- TRB trigger inputs + APV_TRGDONE_IN : in std_logic; -- APV trigger statemachine finished (one pulse) + TRG_3_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 3 + TRG_2_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 2 + TRG_1_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 1 + TRG_0_TODO_IN : in std_logic_vector(3 downto 0); -- APV triggers on trigger 0 + TRG_SETUP_IN : in std_logic_vector(7 downto 0); -- setup of external triggers + TRG_FOUND_OUT : out std_logic; -- single pulse for endpoint + SECTOR_IN : in std_logic_vector(2 downto 0); -- sector number + -- TRB LVL1 channel signals + TRB_TTAG_IN : in std_logic_vector(15 downto 0); -- LVL1 16bit trigger tag + TRB_TRND_IN : in std_logic_vector(7 downto 0); -- LVL1 8bit random number + TRB_TTYPE_IN : in std_logic_vector(3 downto 0); -- LVL1 4bit trigger type + TRB_TINFO_IN : in std_logic_vector(23 downto 0); -- LVL1 24bit trigger information + TRB_TRGRCVD_IN : in std_logic; -- LVL1 trigger has been received on TRB + TRB_MISSING_OUT : out std_logic; -- LVL1 trigger without timing trigger + LVL1_COUNTER_OUT : out std_logic_vector(15 downto 0); + LVL1_COUNTER_IN : in std_logic_vector(15 downto 0); + LVL1_LD_COUNTER_IN : in std_logic; + BUSY_RELEASE_IN : in std_logic; -- common signal from busy calculator + -- + APV_TRGSEL_OUT : out std_logic_vector(3 downto 0); -- select one APV trigger state machine + APV_TRGSTART_OUT : out std_logic; -- start an APV trigger state machine + EDS_DATA_OUT : out std_logic_vector(39 downto 0); -- EDS data + EDS_WE_OUT : out std_logic; -- EDS write enable (general interface) + EDS_START_OUT : out std_logic; -- separate increment signal for EDS buffer level + EDS_READY_OUT : out std_logic; -- APV trigger sequence done + DBG_FRMCTR_OUT : out std_logic_vector(3 downto 0); -- framecounter itself + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(63 downto 0) +); end; architecture behavioral of real_trg_handler is - -- state machine signals - type STATES is (SLEEP, STORE, START, COUNT, RELAX, CHECK, WAPV, WLVL1, TRBS, COMP, CTAG, STAG, - DTAG, WEDS, WDEL0, WDEL1, WBUSY, DONE, CNTEVT, BADTRG); - signal CURRENT_STATE, NEXT_STATE: STATES; - - -- normal signals - signal trg_comb : std_logic_vector(3 downto 0); -- TRB or hardware inputs - signal trg_q : std_logic_vector(3 downto 0); - signal trg_qq : std_logic_vector(3 downto 0); - signal trg_qqq : std_logic_vector(3 downto 0); - signal trg_qqqq : std_logic_vector(3 downto 0); - signal trg_edge : std_logic_vector(3 downto 0); - signal decoded_trg : std_logic_vector(3 downto 0); - signal todo_start : std_logic_vector(3 downto 0); - signal trg_found : std_logic; - signal trg_pattern : std_logic_vector(3 downto 0); - - signal evtctr : std_logic_vector(15 downto 0); -- event counter - signal ce_evtctr : std_logic; - signal ce_evtctr_x : std_logic; - signal frmctr : std_logic_vector(3 downto 0); -- frame counter - signal ce_frmctr : std_logic; - signal ce_frmctr_x : std_logic; - signal todo_ctr : std_logic_vector(3 downto 0); - signal todo_done_x : std_logic; - signal todo_done : std_logic; - signal apv_trgstart_x : std_logic; - signal apv_trgstart : std_logic; - signal eds_data : std_logic_vector(39 downto 0); - signal eds_start : std_logic; - signal eds_start_x : std_logic; - signal eds_we : std_logic; - signal eds_we_x : std_logic; - signal eds_ready_x : std_logic; - signal eds_ready : std_logic; -- end signal, release busy by sending TERM and clean up misc stuff - signal apv_trg_finished : std_logic; - signal accept_x : std_logic; -- we can accept a trigger - signal accept : std_logic; - signal missed_trg_x : std_logic; - signal missed_trg : std_logic; - signal missing_trg : std_logic; - signal rst_status_x : std_logic; - signal rst_status : std_logic; - - signal time_trg : std_logic_vector(3 downto 0); - - -- Information to be collected for the EDS - signal trb_ttag_reg : std_logic_vector(15 downto 0); -- TRB LVL1 trigger tag (16bit) - signal trb_trnd_reg : std_logic_vector(7 downto 0); -- TRB LVL1 random byte (8bit) - signal trb_ttype_reg : std_logic_vector(3 downto 0); -- TRB LVL1 trigger type (4bit) - signal trg_pattern_reg : std_logic_vector(3 downto 0); -- timing trigger input pattern (4bit) - signal trg_dectrg_reg : std_logic_vector(3 downto 0); -- priority encoded timing trigger (4bit) - signal trg_frmctr_reg : std_logic_vector(3 downto 0); -- frame counter start value (4bit) - signal trg_frmnum_reg : std_logic_vector(3 downto 0); -- number of frames in this event (4bit) - - signal store_local_x : std_logic; - signal store_local : std_logic; - signal store_remote_x : std_logic; - signal store_remote : std_logic; - - signal time_trg_on : std_logic_vector(3 downto 0); - signal time_trg_inv : std_logic_vector(3 downto 0); - - signal bsm_x : std_logic_vector(7 downto 0); +-- state machine signals +type STATES is (SLEEP, STORE, START, COUNT, RELAX, CHECK, WAPV, WLVL1, TRBS, + WEDS, WDEL0, WDEL1, WBUSY, DONE, CNTEVT, BADTRG, TTLTRG); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- normal signals +signal trg_comb : std_logic_vector(3 downto 0); -- TRB or hardware inputs +signal trg_q : std_logic_vector(3 downto 0); +signal trg_qq : std_logic_vector(3 downto 0); +signal trg_qqq : std_logic_vector(3 downto 0); +signal trg_qqqq : std_logic_vector(3 downto 0); +signal trg_edge : std_logic_vector(3 downto 0); +signal decoded_trg : std_logic_vector(3 downto 0); +signal todo_start : std_logic_vector(3 downto 0); +signal trg_found : std_logic; + +signal evtctr : std_logic_vector(15 downto 0); -- event counter +signal ce_evtctr : std_logic; +signal next_ce_evtctr : std_logic; +signal frmctr : std_logic_vector(3 downto 0); -- frame counter +signal ce_frmctr : std_logic; +signal next_ce_frmctr : std_logic; +signal todo_ctr : std_logic_vector(3 downto 0); +signal next_todo_done : std_logic; +signal todo_done : std_logic; +signal next_apv_trgstart : std_logic; +signal apv_trgstart : std_logic; +signal eds_data : std_logic_vector(39 downto 0); +signal eds_start : std_logic; +signal next_eds_start : std_logic; +signal eds_we : std_logic; +signal next_eds_we : std_logic; +signal next_eds_ready : std_logic; +signal eds_ready : std_logic; -- end signal, release busy by sending TERM and clean up misc stuff +signal apv_trg_finished : std_logic; +signal next_accept : std_logic; -- we can accept a trigger +signal accept : std_logic; +signal next_missed_trg : std_logic; +signal missed_trg : std_logic; +signal missing_trg : std_logic; +signal next_rst_status : std_logic; +signal rst_status : std_logic; + +signal time_trg : std_logic_vector(3 downto 0); + +-- Information to be collected for the EDS +signal trg_dectrg_reg : std_logic_vector(3 downto 0); -- priority encoded timing trigger (4bit) +signal trg_frmctr_reg : std_logic_vector(3 downto 0); -- frame counter start value (4bit) +signal trg_frmnum_reg : std_logic_vector(3 downto 0); -- number of frames in this event (4bit) + +signal next_store_local : std_logic; +signal store_local : std_logic; +signal next_rst_local : std_logic; +signal rst_local : std_logic; + +signal time_trg_on : std_logic_vector(3 downto 0); +signal time_trg_inv : std_logic_vector(3 downto 0); + +signal big_event_comb : std_logic; +signal tag_sector_match_comb : std_logic; +signal suppress_data_comb : std_logic; + +signal bsm_x : std_logic_vector(7 downto 0); begin @@ -127,29 +130,33 @@ time_trg_inv(0) <= trg_setup_in(0); ------------------------------------------------------------ -- Synchronize the external trigger inputs THE_TIME_TRG_3_SYNC: state_sync -port map( STATE_A_IN => time_trg_in(3), - CLK_B_IN => clk_in, - RESET_B_IN => reset_in, - STATE_B_OUT => time_trg(3) - ); +port map( + STATE_A_IN => time_trg_in(3), + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + STATE_B_OUT => time_trg(3) +); THE_TIME_TRG_2_SYNC: state_sync -port map( STATE_A_IN => time_trg_in(2), - CLK_B_IN => clk_in, - RESET_B_IN => reset_in, - STATE_B_OUT => time_trg(2) - ); +port map( + STATE_A_IN => time_trg_in(2), + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + STATE_B_OUT => time_trg(2) +); THE_TIME_TRG_1_SYNC: state_sync -port map( STATE_A_IN => time_trg_in(1), - CLK_B_IN => clk_in, - RESET_B_IN => reset_in, - STATE_B_OUT => time_trg(1) - ); +port map( + STATE_A_IN => time_trg_in(1), + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + STATE_B_OUT => time_trg(1) +); THE_TIME_TRG_0_SYNC: state_sync -port map( STATE_A_IN => time_trg_in(0), - CLK_B_IN => clk_in, - RESET_B_IN => reset_in, - STATE_B_OUT => time_trg(0) - ); +port map( + STATE_A_IN => time_trg_in(0), + CLK_B_IN => clk_in, + RESET_B_IN => reset_in, + STATE_B_OUT => time_trg(0) +); ------------------------------------------------------------ -- For all four possible hardware triggers we combine hardware and TRB inputs @@ -196,9 +203,9 @@ begin end if; end process THE_RISING_EDGES_PROC; --- Now we are almost done. +-- Now we are almost done. -- The detected edges are priorized. -THE_TRG_PRIORITY_PROC: process( clk_in ) +THE_TRG_PRIORITY_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then if( reset_in = '1' ) then @@ -223,6 +230,7 @@ begin todo_start <= trg_0_todo_in; trg_found <= '1'; else + -- case of "timingtriggerless trigger"? decoded_trg <= "0000"; todo_start <= "0000"; trg_found <= '0'; @@ -237,13 +245,11 @@ end process THE_TRG_PRIORITY_PROC; THE_LOCALSTORE_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then - if( (reset_in = '1') or (eds_we = '1') ) then - trg_pattern_reg <= (others => '0'); + if( (reset_in = '1') or (rst_local = '1') ) then trg_frmctr_reg <= (others => '0'); trg_frmnum_reg <= (others => '0'); trg_dectrg_reg <= (others => '0'); elsif( (accept = '1') and (trg_found = '1') ) then -- the clock cycle before local_store pulse - trg_pattern_reg <= trg_pattern; -- BUGBUGBUG trg_frmctr_reg <= frmctr; trg_frmnum_reg <= todo_start; trg_dectrg_reg <= decoded_trg; @@ -258,29 +264,14 @@ begin if ( reset_in = '1' ) then todo_ctr <= (others => '0'); elsif( store_local = '1' ) then - todo_ctr <= trg_frmnum_reg; --todo_start; + todo_ctr <= trg_frmnum_reg; elsif( ce_frmctr = '1' ) then todo_ctr <= todo_ctr - 1; end if; end if; end process THE_TODO_COUNTER_PROC; -todo_done_x <= '1' when (todo_ctr = x"0") else '0'; +next_todo_done <= '1' when (todo_ctr = x"0") else '0'; --- We need to store some information for the EDS... from TRBnet LVL1 trigger endpoint -THE_REMOTESTORE_PROC: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - trb_ttag_reg <= (others => '0'); - trb_trnd_reg <= (others => '0'); - trb_ttype_reg <= (others => '0'); - elsif( store_remote = '1' ) then - trb_ttag_reg <= trb_ttag_in; - trb_trnd_reg <= trb_trnd_in; - trb_ttype_reg <= trb_ttype_in; - end if; - end if; -end process THE_REMOTESTORE_PROC; ------------------------------------------------- ------------------------------------------------- @@ -290,11 +281,9 @@ THE_TRG_SYNC_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then if( reset_in = '1' ) then - trg_pattern <= (others => '0'); todo_done <= '0'; else - trg_pattern <= trg_edge; - todo_done <= todo_done_x; + todo_done <= next_todo_done; end if; end if; end process THE_TRG_SYNC_PROC; @@ -316,7 +305,7 @@ end process THE_TRGDONE_PROC; -- A statemachine handles all actions for filling out the trigger information sheet -- state registers -STATE_MEM: process( clk_in ) +STATE_MEM: process( clk_in ) begin if( rising_edge(clk_in) ) then if( reset_in = '1' ) then @@ -326,115 +315,107 @@ begin eds_ready <= '0'; eds_we <= '0'; eds_start <= '0'; + rst_local <= '0'; store_local <= '0'; - store_remote <= '0'; apv_trgstart <= '0'; accept <= '1'; missed_trg <= '0'; rst_status <= '0'; else CURRENT_STATE <= NEXT_STATE; - ce_evtctr <= ce_evtctr_x; - ce_frmctr <= ce_frmctr_x; - eds_ready <= eds_ready_x; - eds_we <= eds_we_x; - eds_start <= eds_start_x; - store_local <= store_local_x; - store_remote <= store_remote_x; - apv_trgstart <= apv_trgstart_x; - accept <= accept_x; - missed_trg <= missed_trg_x; - rst_status <= rst_status_x; + ce_evtctr <= next_ce_evtctr; + ce_frmctr <= next_ce_frmctr; + eds_ready <= next_eds_ready; + eds_we <= next_eds_we; + eds_start <= next_eds_start; + rst_local <= next_rst_local; + store_local <= next_store_local; + apv_trgstart <= next_apv_trgstart; + accept <= next_accept; + missed_trg <= next_missed_trg; + rst_status <= next_rst_status; end if; end if; end process STATE_MEM; -- state transitions -STATE_TRANSFORM: process( CURRENT_STATE, trg_found, todo_done, trb_trgrcvd_in, apv_trg_finished, busy_release_in, missing_trg ) +STATE_TRANSFORM: process( CURRENT_STATE, trg_found, todo_done, trb_trgrcvd_in, apv_trg_finished, + busy_release_in, trb_ttype_in(3), trb_tinfo_in(7) ) begin - NEXT_STATE <= SLEEP; -- avoid latches - ce_evtctr_x <= '0'; - ce_frmctr_x <= '0'; - eds_ready_x <= '0'; - eds_we_x <= '0'; - eds_start_x <= '0'; - store_local_x <= '0'; - store_remote_x <= '0'; - apv_trgstart_x <= '0'; - accept_x <= '0'; - missed_trg_x <= '0'; - rst_status_x <= '0'; + NEXT_STATE <= SLEEP; -- avoid latches + next_ce_evtctr <= '0'; + next_ce_frmctr <= '0'; + next_eds_ready <= '0'; + next_eds_we <= '0'; + next_eds_start <= '0'; + next_rst_local <= '0'; + next_store_local <= '0'; + next_apv_trgstart <= '0'; + next_accept <= '0'; + next_missed_trg <= '0'; + next_rst_status <= '0'; case CURRENT_STATE is -- not good. if no timing trigger was received but a trb trigger arrives, we must do something! - when SLEEP => if ( trg_found = '1' ) then + when SLEEP => if ( trg_found = '1' ) then -- normal way: timing trigger found - NEXT_STATE <= STORE; - store_local_x <= '1'; - eds_start_x <= '1'; - elsif( (trg_found = '0') and (trb_trgrcvd_in = '1') ) then - -- bad way: missing timing trigger - NEXT_STATE <= BADTRG; - missed_trg_x <= '1'; + NEXT_STATE <= STORE; + next_store_local <= '1'; + next_eds_start <= '1'; + elsif( (trg_found = '0') and (trb_trgrcvd_in = '1') and (trb_ttype_in(3) = '1') and (trb_tinfo_in(7) = '1') ) then + NEXT_STATE <= TTLTRG; + elsif( (trg_found = '0') and (trb_trgrcvd_in = '1') and ((trb_ttype_in(3) = '0') or (trb_tinfo_in(7) = '0')) ) then + NEXT_STATE <= BADTRG; + next_missed_trg <= '1'; else - NEXT_STATE <= SLEEP; - accept_x <= '1'; + NEXT_STATE <= SLEEP; + next_accept <= '1'; end if; - when BADTRG => NEXT_STATE <= TRBS; - store_remote_x <= '1'; - when STORE => NEXT_STATE <= START; - apv_trgstart_x <= '1'; - when START => NEXT_STATE <= CHECK; - when CHECK => if( todo_done = '1' ) then + when TTLTRG => NEXT_STATE <= TRBS; + when BADTRG => NEXT_STATE <= TRBS; + when STORE => NEXT_STATE <= START; + next_apv_trgstart <= '1'; + when START => NEXT_STATE <= CHECK; + when CHECK => if( todo_done = '1' ) then NEXT_STATE <= WAPV; else - NEXT_STATE <= COUNT; - ce_frmctr_x <= '1'; + NEXT_STATE <= COUNT; + next_ce_frmctr <= '1'; end if; - when COUNT => NEXT_STATE <= RELAX; - when RELAX => NEXT_STATE <= CHECK; - when WAPV => if( apv_trg_finished = '1' ) then + when COUNT => NEXT_STATE <= RELAX; + when RELAX => NEXT_STATE <= CHECK; + when WAPV => if( apv_trg_finished = '1' ) then NEXT_STATE <= WLVL1; else NEXT_STATE <= WAPV; end if; - when WLVL1 => if( trb_trgrcvd_in = '1' ) then - NEXT_STATE <= TRBS; - store_remote_x <= '1'; + when WLVL1 => if( trb_trgrcvd_in = '1' ) then + NEXT_STATE <= TRBS; else NEXT_STATE <= WLVL1; end if; - when TRBS => NEXT_STATE <= CTAG; - when CTAG => NEXT_STATE <= STAG; - when STAG => NEXT_STATE <= DTAG; - when DTAG => if( missing_trg = '0' ) then - -- everything is fine - NEXT_STATE <= WEDS; - eds_we_x <= '1'; - else - -- we missed a timing trigger, so no EDS was created - NEXT_STATE <= CNTEVT; - ce_evtctr_x <= '1'; - end if; - when WEDS => NEXT_STATE <= CNTEVT; - ce_evtctr_x <= '1'; - when CNTEVT => NEXT_STATE <= WDEL0; - when WDEL0 => NEXT_STATE <= WDEL1; - when WDEL1 => NEXT_STATE <= WBUSY; - when WBUSY => if( busy_release_in = '1' ) then - NEXT_STATE <= DONE; - eds_ready_x <= '1'; + when TRBS => NEXT_STATE <= WEDS; + next_eds_we <= '1'; + next_rst_local <= '1'; + when WEDS => NEXT_STATE <= CNTEVT; + next_ce_evtctr <= '1'; + when CNTEVT => NEXT_STATE <= WDEL0; + when WDEL0 => NEXT_STATE <= WDEL1; + when WDEL1 => NEXT_STATE <= WBUSY; + when WBUSY => if( busy_release_in = '1' ) then + NEXT_STATE <= DONE; + next_eds_ready <= '1'; else NEXT_STATE <= WBUSY; end if; - when DONE => if( trb_trgrcvd_in = '0' ) then -- mind the state synchronizer delay!!! - NEXT_STATE <= SLEEP; - accept_x <= '1'; - rst_status_x <= '1'; + when DONE => if( trb_trgrcvd_in = '0' ) then -- mind the state synchronizer delay!!! + NEXT_STATE <= SLEEP; + next_accept <= '1'; + next_rst_status <= '1'; else NEXT_STATE <= DONE; end if; - when others => NEXT_STATE <= SLEEP; - accept_x <= '1'; + when others => NEXT_STATE <= SLEEP; + next_accept <= '1'; end case; end process STATE_TRANSFORM; @@ -442,26 +423,24 @@ end process STATE_TRANSFORM; STATE_DECODE: process( CURRENT_STATE ) begin case CURRENT_STATE is - when SLEEP => bsm_x <= x"00"; - when STORE => bsm_x <= x"01"; - when START => bsm_x <= x"02"; - when CHECK => bsm_x <= x"03"; - when COUNT => bsm_x <= x"04"; - when RELAX => bsm_x <= x"14"; - when WAPV => bsm_x <= x"05"; - when WLVL1 => bsm_x <= x"06"; - when TRBS => bsm_x <= x"07"; - when CTAG => bsm_x <= x"08"; - when STAG => bsm_x <= x"09"; - when DTAG => bsm_x <= x"0a"; - when WEDS => bsm_x <= x"0b"; - when WDEL0 => bsm_x <= x"0c"; - when WDEL1 => bsm_x <= x"0d"; - when WBUSY => bsm_x <= x"0e"; - when DONE => bsm_x <= x"0f"; - when CNTEVT => bsm_x <= x"10"; - when BADTRG => bsm_x <= x"11"; - when others => bsm_x <= x"ff"; + when SLEEP => bsm_x <= x"00"; + when STORE => bsm_x <= x"01"; + when START => bsm_x <= x"02"; + when CHECK => bsm_x <= x"03"; + when COUNT => bsm_x <= x"04"; + when RELAX => bsm_x <= x"14"; + when WAPV => bsm_x <= x"05"; + when WLVL1 => bsm_x <= x"06"; + when TRBS => bsm_x <= x"07"; + when WEDS => bsm_x <= x"0b"; + when WDEL0 => bsm_x <= x"0c"; + when WDEL1 => bsm_x <= x"0d"; + when WBUSY => bsm_x <= x"0e"; + when DONE => bsm_x <= x"0f"; + when CNTEVT => bsm_x <= x"10"; + when BADTRG => bsm_x <= x"11"; + when TTLTRG => bsm_x <= x"12"; + when others => bsm_x <= x"ff"; end case; end process STATE_DECODE; @@ -470,8 +449,10 @@ end process STATE_DECODE; THE_EVENT_COUNTER_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then - if( (reset_in = '1') or (rst_lvl1_counter_in = '1') ) then + if ( reset_in = '1' ) then evtctr <= (others => '0'); + elsif( lvl1_ld_counter_in = '1' ) then + evtctr <= lvl1_counter_in; -- update with value from TRBnet counter elsif( ce_evtctr = '1' ) then evtctr <= evtctr + 1; end if; @@ -496,19 +477,40 @@ begin if( rising_edge(clk_in) ) then if( (reset_in = '1') or (rst_status = '1') ) then missing_trg <= '0'; - elsif( missed_trg = '1' ) then - missing_trg <= '1'; - end if; + elsif( missed_trg = '1' ) then + missing_trg <= '1'; + end if; end if; end process THE_MISSED_TRG_REG; +-- Now for something completely different: as we have two sectors connected +-- to one GbE hub in the final setup, we must do a trick to stay below 64kB +-- subevent size. +-- So in all cases where 128 channels per event are requested, only those ADCM +-- will produce data where the last bit of sector number and trigger number matches. +-- I.e.: odd sectors fire on odd trigger numbers, even sectors on even trigger numbers. + +-- potentially dangerous (aka big) event +big_event_comb <= '1' when (trb_tinfo_in(10 downto 8) = b"000") or -- RAW128 + (trb_tinfo_in(10 downto 8) = b"001") or -- PED128 + (trb_tinfo_in(10 downto 8) = b"010") or -- PED128THR + (trb_tinfo_in(10 downto 8) = b"100") -- NC64PED64 + else '0'; + +-- sector number matches trigger number +tag_sector_match_comb <= '1' when ( sector_in(0) = trb_ttag_in(0) ) else '0'; + +-- when to drop data +suppress_data_comb <= (big_event_comb and not tag_sector_match_comb) or trb_tinfo_in(0); + -- EDS bits: eds_data(39 downto 36) <= trg_frmctr_reg; eds_data(35 downto 32) <= trg_frmnum_reg; -eds_data(31 downto 16) <= trb_ttag_reg; -eds_data(15 downto 8) <= trb_trnd_reg; -eds_data(7 downto 4) <= trb_ttype_reg; -eds_data(3 downto 0) <= trg_pattern_reg; +eds_data(31 downto 16) <= trb_ttag_in; +eds_data(15 downto 8) <= trb_trnd_in; +eds_data(7 downto 4) <= trb_ttype_in; +eds_data(3) <= suppress_data_comb; --trb_tinfo_in(0); -- suppress output bit +eds_data(2 downto 0) <= trb_tinfo_in(10 downto 8); -- RICH data configuration bits -- output signals apv_trgstart_out <= apv_trgstart; @@ -527,7 +529,7 @@ bsm_out <= bsm_x; debug_out(63 downto 32) <= (others => '0'); debug_out(31 downto 24) <= evtctr(7 downto 0); -debug_out(23 downto 16) <= trb_ttag_reg(7 downto 0); +debug_out(23 downto 16) <= trb_ttag_in(7 downto 0); debug_out(15) <= ce_evtctr; debug_out(14) <= '0'; debug_out(13) <= missing_trg; diff --git a/src/reboot_handler.vhd b/src/reboot_handler.vhd index bfb7059..fb2b890 100644 --- a/src/reboot_handler.vhd +++ b/src/reboot_handler.vhd @@ -1,29 +1,30 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.adcmv3_components.all; entity reboot_handler is - port( RESET_IN : in std_logic; - CLK_IN : in std_logic; - START_IN : in std_logic; - REBOOT_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + RESET_IN : in std_logic; + CLK_IN : in std_logic; + START_IN : in std_logic; + REBOOT_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of reboot_handler is - -- normal signals - signal reboot_counter : std_logic_vector(15 downto 0); - signal reboot_ce : std_logic; - signal reboot_x : std_logic; - signal reboot : std_logic; - -begin +-- normal signals +signal reboot_counter : std_logic_vector(15 downto 0); +signal reboot_ce : std_logic; +signal reboot_x : std_logic; +signal reboot : std_logic; + +begin -- Latch the start pulse THE_START_PULSE: process( clk_in ) @@ -56,6 +57,6 @@ reboot_x <= reboot_counter(15) and reboot_counter(14) and reboot_counter(13); -- output signals reboot_out <= reboot; -debug_out(15 downto 0) <= reboot_counter; +debug_out(15 downto 0) <= reboot_counter; -end behavioral; +end behavioral; diff --git a/src/ref_row_sel.vhd b/src/ref_row_sel.vhd index 3cf165d..3d54ef4 100755 --- a/src/ref_row_sel.vhd +++ b/src/ref_row_sel.vhd @@ -6,7 +6,7 @@ use ieee.std_logic_unsigned.all; library work; use work.adcmv3_components.all; --- This module takes ROW and ERROR information from all sixteen raw buffers, and +-- This module takes ROW and ERROR information from all sixteen raw buffers, and -- checks if the APVs with "good data" buffers are OK. -- APV frame errors are sensed, as well as APV row errors. -- The row error recognition is based somehow on the old RICH RC logic, as it takes @@ -14,61 +14,62 @@ use work.adcmv3_components.all; -- this reference row. entity ref_row_sel is - port( CLK_IN : in std_logic; - READY_IN : in std_logic_vector(15 downto 0); -- buffer ready signals (data or timeout) - GOODDATA_IN : in std_logic_vector(15 downto 0); -- buffer data good signals - FRAME_0_IN : in std_logic_vector(11 downto 0); - FRAME_1_IN : in std_logic_vector(11 downto 0); - FRAME_2_IN : in std_logic_vector(11 downto 0); - FRAME_3_IN : in std_logic_vector(11 downto 0); - FRAME_4_IN : in std_logic_vector(11 downto 0); - FRAME_5_IN : in std_logic_vector(11 downto 0); - FRAME_6_IN : in std_logic_vector(11 downto 0); - FRAME_7_IN : in std_logic_vector(11 downto 0); - FRAME_8_IN : in std_logic_vector(11 downto 0); - FRAME_9_IN : in std_logic_vector(11 downto 0); - FRAME_10_IN : in std_logic_vector(11 downto 0); - FRAME_11_IN : in std_logic_vector(11 downto 0); - FRAME_12_IN : in std_logic_vector(11 downto 0); - FRAME_13_IN : in std_logic_vector(11 downto 0); - FRAME_14_IN : in std_logic_vector(11 downto 0); - FRAME_15_IN : in std_logic_vector(11 downto 0); - READY_OUT : out std_logic; -- all buffers reported being ready for data transport - VALID_BUFS_OUT : out std_logic; -- at least one APV raw buffer has data to fetch - ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong - APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit - APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0); - REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row - DBG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLK_IN : in std_logic; + READY_IN : in std_logic_vector(15 downto 0); -- buffer ready signals (data or timeout) + GOODDATA_IN : in std_logic_vector(15 downto 0); -- buffer data good signals + FRAME_0_IN : in std_logic_vector(11 downto 0); + FRAME_1_IN : in std_logic_vector(11 downto 0); + FRAME_2_IN : in std_logic_vector(11 downto 0); + FRAME_3_IN : in std_logic_vector(11 downto 0); + FRAME_4_IN : in std_logic_vector(11 downto 0); + FRAME_5_IN : in std_logic_vector(11 downto 0); + FRAME_6_IN : in std_logic_vector(11 downto 0); + FRAME_7_IN : in std_logic_vector(11 downto 0); + FRAME_8_IN : in std_logic_vector(11 downto 0); + FRAME_9_IN : in std_logic_vector(11 downto 0); + FRAME_10_IN : in std_logic_vector(11 downto 0); + FRAME_11_IN : in std_logic_vector(11 downto 0); + FRAME_12_IN : in std_logic_vector(11 downto 0); + FRAME_13_IN : in std_logic_vector(11 downto 0); + FRAME_14_IN : in std_logic_vector(11 downto 0); + FRAME_15_IN : in std_logic_vector(11 downto 0); + READY_OUT : out std_logic; -- all buffers reported being ready for data transport + VALID_BUFS_OUT : out std_logic; -- at least one APV raw buffer has data to fetch + ROW_ERROR_OUT : out std_logic; -- at least one row number is wrong + APV_ERROR_OUT : out std_logic; -- at least one APV sent ERROR bit + APV_ERROR_BITS_OUT : out std_logic_vector(15 downto 0); + REF_ROW_OUT : out std_logic_vector(7 downto 0); -- selected reference row + DBG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of ref_row_sel is - -- normal signals - signal debug_x : std_logic_vector(15 downto 0); - - signal next_sel_ref_row : std_logic_vector(3 downto 0); - signal sel_ref_row : std_logic_vector(3 downto 0); - signal next_valid_bufs : std_logic; - signal valid_bufs : std_logic; - signal next_all_ready : std_logic; - signal all_ready : std_logic; - - signal ref_row : std_logic_vector(7 downto 0); -- selected reference row number - - signal next_row_match : std_logic_vector(15 downto 0); - signal row_match : std_logic_vector(15 downto 0); -- APV frame row matches reference number - - signal next_apv_error : std_logic_vector(15 downto 0); - signal apv_error : std_logic_vector(15 downto 0); -- APV frame error is set - - signal next_frame_row_err : std_logic; - signal frame_row_err : std_logic; - signal next_frame_apv_err : std_logic; - signal frame_apv_err : std_logic; - - +-- normal signals +signal debug_x : std_logic_vector(15 downto 0); + +signal next_sel_ref_row : std_logic_vector(3 downto 0); +signal sel_ref_row : std_logic_vector(3 downto 0); +signal next_valid_bufs : std_logic; +signal valid_bufs : std_logic; +signal next_all_ready : std_logic; +signal all_ready : std_logic; + +signal ref_row : std_logic_vector(7 downto 0); -- selected reference row number + +signal next_row_match : std_logic_vector(15 downto 0); +signal row_match : std_logic_vector(15 downto 0); -- APV frame row matches reference number + +signal next_apv_error : std_logic_vector(15 downto 0); +signal apv_error : std_logic_vector(15 downto 0); -- APV frame error is set + +signal next_frame_row_err : std_logic; +signal frame_row_err : std_logic; +signal next_frame_apv_err : std_logic; +signal frame_apv_err : std_logic; + + begin -- Sync process @@ -136,23 +137,23 @@ THE_REF_ROW_SELECT_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then case sel_ref_row is - when "0000" => ref_row <= frame_0_in(7 downto 0); - when "0001" => ref_row <= frame_1_in(7 downto 0); - when "0010" => ref_row <= frame_2_in(7 downto 0); - when "0011" => ref_row <= frame_3_in(7 downto 0); - when "0100" => ref_row <= frame_4_in(7 downto 0); - when "0101" => ref_row <= frame_5_in(7 downto 0); - when "0110" => ref_row <= frame_6_in(7 downto 0); - when "0111" => ref_row <= frame_7_in(7 downto 0); - when "1000" => ref_row <= frame_8_in(7 downto 0); - when "1001" => ref_row <= frame_9_in(7 downto 0); - when "1010" => ref_row <= frame_10_in(7 downto 0); - when "1011" => ref_row <= frame_11_in(7 downto 0); - when "1100" => ref_row <= frame_12_in(7 downto 0); - when "1101" => ref_row <= frame_13_in(7 downto 0); - when "1110" => ref_row <= frame_14_in(7 downto 0); - when "1111" => ref_row <= frame_15_in(7 downto 0); - when others => ref_row <= x"ee"; -- will not be used... all cases are covered. + when "0000" => ref_row <= frame_0_in(7 downto 0); + when "0001" => ref_row <= frame_1_in(7 downto 0); + when "0010" => ref_row <= frame_2_in(7 downto 0); + when "0011" => ref_row <= frame_3_in(7 downto 0); + when "0100" => ref_row <= frame_4_in(7 downto 0); + when "0101" => ref_row <= frame_5_in(7 downto 0); + when "0110" => ref_row <= frame_6_in(7 downto 0); + when "0111" => ref_row <= frame_7_in(7 downto 0); + when "1000" => ref_row <= frame_8_in(7 downto 0); + when "1001" => ref_row <= frame_9_in(7 downto 0); + when "1010" => ref_row <= frame_10_in(7 downto 0); + when "1011" => ref_row <= frame_11_in(7 downto 0); + when "1100" => ref_row <= frame_12_in(7 downto 0); + when "1101" => ref_row <= frame_13_in(7 downto 0); + when "1110" => ref_row <= frame_14_in(7 downto 0); + when "1111" => ref_row <= frame_15_in(7 downto 0); + when others => ref_row <= x"ee"; -- will not be used... all cases are covered. end case; end if; end process THE_REF_ROW_SELECT_PROC; @@ -161,52 +162,52 @@ end process THE_REF_ROW_SELECT_PROC; -- Only channels with GOODDATA are to be taken into account; if the channel is invalid, we ignore it. next_row_match(0) <= '1' when ( (gooddata_in(0) = '0') or - ((gooddata_in(0) = '1') and (frame_0_in(7 downto 0) = ref_row) ) ) - else '0'; + ((gooddata_in(0) = '1') and (frame_0_in(7 downto 0) = ref_row) ) ) + else '0'; next_row_match(1) <= '1' when ( (gooddata_in(1) = '0') or - ((gooddata_in(1) = '1') and (frame_1_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(1) = '1') and (frame_1_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(2) <= '1' when ( (gooddata_in(2) = '0') or - ((gooddata_in(2) = '1') and (frame_2_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(2) = '1') and (frame_2_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(3) <= '1' when ( (gooddata_in(3) = '0') or - ((gooddata_in(3) = '1') and (frame_3_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(3) = '1') and (frame_3_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(4) <= '1' when ( (gooddata_in(4) = '0') or - ((gooddata_in(4) = '1') and (frame_4_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(4) = '1') and (frame_4_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(5) <= '1' when ( (gooddata_in(5) = '0') or - ((gooddata_in(5) = '1') and (frame_5_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(5) = '1') and (frame_5_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(6) <= '1' when ( (gooddata_in(6) = '0') or - ((gooddata_in(6) = '1') and (frame_6_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(6) = '1') and (frame_6_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(7) <= '1' when ( (gooddata_in(7) = '0') or - ((gooddata_in(7) = '1') and (frame_7_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(7) = '1') and (frame_7_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(8) <= '1' when ( (gooddata_in(8) = '0') or - ((gooddata_in(8) = '1') and (frame_8_in(7 downto 0) = ref_row) ) ) - else '0'; + ((gooddata_in(8) = '1') and (frame_8_in(7 downto 0) = ref_row) ) ) + else '0'; next_row_match(9) <= '1' when ( (gooddata_in(9) = '0') or - ((gooddata_in(9) = '1') and (frame_9_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(9) = '1') and (frame_9_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(10) <= '1' when ( (gooddata_in(10) = '0') or - ((gooddata_in(10) = '1') and (frame_10_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(10) = '1') and (frame_10_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(11) <= '1' when ( (gooddata_in(11) = '0') or - ((gooddata_in(11) = '1') and (frame_11_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(11) = '1') and (frame_11_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(12) <= '1' when ( (gooddata_in(12) = '0') or - ((gooddata_in(12) = '1') and (frame_12_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(12) = '1') and (frame_12_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(13) <= '1' when ( (gooddata_in(13) = '0') or - ((gooddata_in(13) = '1') and (frame_13_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(13) = '1') and (frame_13_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(14) <= '1' when ( (gooddata_in(14) = '0') or - ((gooddata_in(14) = '1') and (frame_14_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(14) = '1') and (frame_14_in(7 downto 0) = ref_row) ) ) else '0'; next_row_match(15) <= '1' when ( (gooddata_in(15) = '0') or - ((gooddata_in(15) = '1') and (frame_15_in(7 downto 0) = ref_row) ) ) + ((gooddata_in(15) = '1') and (frame_15_in(7 downto 0) = ref_row) ) ) else '0'; -- APV error recognition - same issue. @@ -232,7 +233,7 @@ next_frame_row_err <= '1' when ( row_match /= x"ffff" ) else '0'; next_frame_apv_err <= '1' when ( apv_error /= x"0000" ) else '0'; -- output signals -valid_bufs_out <= valid_bufs; +valid_bufs_out <= valid_bufs; ready_out <= all_ready; row_error_out <= frame_row_err; apv_error_out <= frame_apv_err; diff --git a/src/reset_handler.vhd b/src/reset_handler.vhd index 8cc8bc5..7177022 100644 --- a/src/reset_handler.vhd +++ b/src/reset_handler.vhd @@ -7,30 +7,31 @@ library work; use work.adcmv3_components.all; entity reset_handler is - port( CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0') - RESET_IN : in std_logic; -- for testing, if not needed, set to '0' - CLK_IN : in std_logic; - TRB_RESET_IN : in std_logic; - RESET_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); +port( + CLEAR_IN : in std_logic; -- async reset from outside, if available (otherwise '0') + RESET_IN : in std_logic; -- for testing, if not needed, set to '0' + CLK_IN : in std_logic; + TRB_RESET_IN : in std_logic; + RESET_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) +); end; architecture behavioral of reset_handler is -- normal signals - signal async_sampler : std_logic_vector(7 downto 0); - signal async_pulse_x : std_logic; - signal async_pulse : std_logic; - signal reset_cnt : std_logic_vector(15 downto 0); - signal debug : std_logic_vector(15 downto 0); - signal reset : std_logic; +signal async_sampler : std_logic_vector(7 downto 0); +signal async_pulse_x : std_logic; +signal async_pulse : std_logic; +signal reset_cnt : std_logic_vector(15 downto 0); +signal debug : std_logic_vector(15 downto 0); +signal reset : std_logic; - attribute syn_preserve : boolean; - attribute syn_preserve of async_sampler : signal is true; - attribute syn_preserve of async_pulse : signal is true; - attribute syn_preserve of reset : signal is true; - attribute syn_preserve of reset_cnt : signal is true; +attribute syn_preserve : boolean; +attribute syn_preserve of async_sampler : signal is true; +attribute syn_preserve of async_pulse : signal is true; +attribute syn_preserve of reset : signal is true; +attribute syn_preserve of reset_cnt : signal is true; begin @@ -48,19 +49,19 @@ async_pulse_x <= '1' when ( async_sampler = x"ff" ) else '0'; -- one global reset counter THE_GLOBAL_RESET_PROC: process( clk_in ) begin - if( rising_edge(clk_in) ) then - if( (async_pulse = '1') or (reset_in = '1') or (trb_reset_in = '1') ) then - reset_cnt <= (others => '0'); - reset <= '1'; - else - reset_cnt <= reset_cnt + 1; - reset <= '1'; - if( reset_cnt = x"001F" ) then - reset <= '0'; - reset_cnt <= x"001F"; - end if; - end if; - end if; + if( rising_edge(clk_in) ) then + if( (async_pulse = '1') or (reset_in = '1') or (trb_reset_in = '1') ) then + reset_cnt <= (others => '0'); + reset <= '1'; + else + reset_cnt <= reset_cnt + 1; + reset <= '1'; + if( reset_cnt = x"001F" ) then + reset <= '0'; + reset_cnt <= x"001F"; + end if; + end if; + end if; end process THE_GLOBAL_RESET_PROC; @@ -70,6 +71,6 @@ debug <= reset_cnt; -- Output signals debug_out <= debug; reset_out <= reset; - + end behavioral; - \ No newline at end of file + \ No newline at end of file diff --git a/src/rich_trb.vhd b/src/rich_trb.vhd index c21020e..d7ae71a 100755 --- a/src/rich_trb.vhd +++ b/src/rich_trb.vhd @@ -10,96 +10,100 @@ use work.trb_net_components.all; use work.adcmv3_components.all; entity rich_trb is -port( CLK100M_IN : in std_logic; -- SerDes exclusive clock - SYSCLK_IN : in std_logic; -- fabric clock - RESET_IN : in std_logic; -- synchronous reset - -- SFP connections - SD_RXD_P_IN : in std_logic; - SD_RXD_N_IN : in std_logic; - SD_TXD_P_OUT : out std_logic; - SD_TXD_N_OUT : out std_logic; - SD_PRESENT_IN : in std_logic; - SD_TXDIS_OUT : out std_logic; - SD_LOS_IN : in std_logic; - ONEWIRE_INOUT : inout std_logic; - -- common regIO status / control registers - COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI - COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI - -- status register input to regIO / control register output from regIO - CONTROL_OUT : out std_logic_vector(63 downto 0); - STATUS_IN : in std_logic_vector(127 downto 0); - -- LVL1 signals - LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); - LVL1_TRG_RECEIVED_OUT : out std_logic; - LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); - LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); - LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); - LVL1_TRG_RELEASE_IN : in std_logic; - TIMING_TRG_FOUND_IN : in std_logic; - -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) - IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag - IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information - IPU_START_READOUT_OUT : out std_logic; -- gimme data! - IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR - IPU_DATAREADY_IN : in std_logic; -- data is valid - IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM - IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle - IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) - IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern - -- regIO bus - REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); - REGIO_READ_ENABLE_OUT : out std_logic; - REGIO_WRITE_ENABLE_OUT : out std_logic; - REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); - REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); - REGIO_DATAREADY_IN : in std_logic; - REGIO_NO_MORE_DATA_IN : in std_logic; - REGIO_WRITE_ACK_IN : in std_logic; - REGIO_UNKNOWN_ADDR_IN : in std_logic; - REGIO_TIMEOUT_OUT : out std_logic; - -- status LEDs - LED_LINK_STAT : out std_logic; - LED_LINK_TXD : out std_logic; - LED_LINK_RXD : out std_logic; - LINK_BSM_OUT : out std_logic_vector(3 downto 0); - RESET_OUT : out std_logic; - -- Debug - DEBUG : out std_logic_vector(63 downto 0) - ); +port( + CLK100M_IN : in std_logic; -- SerDes exclusive clock + SYSCLK_IN : in std_logic; -- fabric clock + RESET_IN : in std_logic; -- synchronous reset + -- SFP connections + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_PRESENT_IN : in std_logic; + SD_TXDIS_OUT : out std_logic; + SD_LOS_IN : in std_logic; + ONEWIRE_INOUT : inout std_logic; + -- common regIO status / control registers + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI + -- status register input to regIO / control register output from regIO + CONTROL_OUT : out std_logic_vector(63 downto 0); + STATUS_IN : in std_logic_vector(127 downto 0); + -- LVL1 signals + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_RECEIVED_OUT : out std_logic; + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_IN : in std_logic; + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_INT_TRG_UPDATE_OUT : out std_logic; + TIMING_TRG_FOUND_IN : in std_logic; + -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-) + IPU_NUMBER_OUT : out std_logic_vector(15 downto 0); -- trigger tag + IPU_INFORMATION_OUT : out std_logic_vector(7 downto 0); -- trigger information + IPU_START_READOUT_OUT : out std_logic; -- gimme data! + IPU_DATA_IN : in std_logic_vector(31 downto 0); -- detector data, equipped with DHDR + IPU_DATAREADY_IN : in std_logic; -- data is valid + IPU_READOUT_FINISHED_IN : in std_logic; -- no more data, end transfer, send TRM + IPU_READ_OUT : out std_logic; -- read strobe, low every second cycle + IPU_LENGTH_IN : in std_logic_vector(15 downto 0); -- length of data packet (32bit words) (?) + IPU_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern + -- regIO bus + REGIO_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0); + REGIO_DATAREADY_IN : in std_logic; + REGIO_NO_MORE_DATA_IN : in std_logic; + REGIO_WRITE_ACK_IN : in std_logic; + REGIO_UNKNOWN_ADDR_IN : in std_logic; + REGIO_TIMEOUT_OUT : out std_logic; + -- status LEDs + LED_LINK_STAT : out std_logic; + LED_LINK_TXD : out std_logic; + LED_LINK_RXD : out std_logic; + LINK_BSM_OUT : out std_logic_vector(3 downto 0); + RESET_OUT : out std_logic; + -- Debug + DEBUG : out std_logic_vector(63 downto 0) +); end entity; architecture rich_arch of rich_trb is - -- Placer Directives - attribute HGROUP : string; - -- for whole architecture - attribute HGROUP of rich_arch : architecture is "RICH_TRB_group"; +-- Placer Directives +attribute HGROUP : string; +-- for whole architecture +attribute HGROUP of rich_arch : architecture is "RICH_TRB_group"; - -- Signals - signal clk_en : std_logic; - signal med_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal med_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal med_dataready_in : std_logic; - signal med_read_out : std_logic; - signal med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal med_dataready_out : std_logic; - signal med_read_in : std_logic; - signal med_stat_debug : std_logic_vector(63 downto 0); - signal med_ctrl_op : std_logic_vector(15 downto 0); - signal med_stat_op : std_logic_vector(15 downto 0); +-- Signals +signal clk_en : std_logic; +signal med_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); +signal med_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); +signal med_dataready_in : std_logic; +signal med_read_out : std_logic; +signal med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); +signal med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); +signal med_dataready_out : std_logic; +signal med_read_in : std_logic; +signal med_stat_debug : std_logic_vector(63 downto 0); +signal med_ctrl_op : std_logic_vector(15 downto 0); +signal med_stat_op : std_logic_vector(15 downto 0); - -- general purpose control and status registers in regIO - signal regio_ctrl_regs : std_logic_vector(32*2-1 downto 0); - signal regio_stat_regs : std_logic_vector(32*4-1 downto 0); - - signal common_stat_reg : std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); - - signal debug_x : std_logic_vector(63 downto 0); - - signal stat_debug_1 : std_logic_vector(31 downto 0); +-- general purpose control and status registers in regIO +signal regio_ctrl_regs : std_logic_vector(32*2-1 downto 0); +signal regio_stat_regs : std_logic_vector(32*4-1 downto 0); + +signal common_stat_reg : std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); +signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); +signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + +signal debug_x : std_logic_vector(63 downto 0); + +signal stat_debug_1 : std_logic_vector(31 downto 0); begin @@ -109,7 +113,7 @@ begin -- Debug debug <= debug_x; - + -- Clock assignment. We don't use CLK_EN really in our designs. clk_en <= '1'; @@ -117,37 +121,41 @@ clk_en <= '1'; -- Serdes ------------------------------------------------------------- THE_MEDIA_INTERFACE : trb_net16_med_ecp_sfp_gbe -generic map( SERDES_NUM => 2 ) -port map( CLK => clk100m_in, - SYSCLK => sysclk_in, - RESET => reset_in, - CLK_EN => clk_en, - --Internal Connection - MED_DATA_IN => med_data_out, - MED_PACKET_NUM_IN => med_packet_num_out, - MED_DATAREADY_IN => med_dataready_out, - MED_READ_OUT => med_read_in, - MED_DATA_OUT => med_data_in, - MED_PACKET_NUM_OUT => med_packet_num_in, - MED_DATAREADY_OUT => med_dataready_in, - MED_READ_IN => med_read_out, - REFCLK2CORE_OUT => open, - --SFP Connection - SD_RXD_P_IN => sd_rxd_p_in, - SD_RXD_N_IN => sd_rxd_n_in, - SD_TXD_P_OUT => sd_txd_p_out, - SD_TXD_N_OUT => sd_txd_n_out, - SD_REFCLK_P_IN => '1', - SD_REFCLK_N_IN => '0', - SD_PRSNT_N_IN => sd_present_in, - SD_LOS_IN => sd_los_in, - SD_TXDIS_OUT => sd_txdis_out, - -- Status and control port - STAT_OP => med_stat_op, - CTRL_OP => med_ctrl_op, -- input - STAT_DEBUG => med_stat_debug, - CTRL_DEBUG => (others => '0') - ); +generic map( + SERDES_NUM => 2 +) +port map( + CLK => clk100m_in, + SYSCLK => sysclk_in, + RESET => reset_in, + CLEAR => '0', + CLK_EN => clk_en, + --Internal Connection + MED_DATA_IN => med_data_out, + MED_PACKET_NUM_IN => med_packet_num_out, + MED_DATAREADY_IN => med_dataready_out, + MED_READ_OUT => med_read_in, + MED_DATA_OUT => med_data_in, + MED_PACKET_NUM_OUT => med_packet_num_in, + MED_DATAREADY_OUT => med_dataready_in, + MED_READ_IN => med_read_out, + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => sd_rxd_p_in, + SD_RXD_N_IN => sd_rxd_n_in, + SD_TXD_P_OUT => sd_txd_p_out, + SD_TXD_N_OUT => sd_txd_n_out, + SD_REFCLK_P_IN => '1', + SD_REFCLK_N_IN => '0', + SD_PRSNT_N_IN => sd_present_in, + SD_LOS_IN => sd_los_in, + SD_TXDIS_OUT => sd_txdis_out, + -- Status and control port + STAT_OP => med_stat_op, + CTRL_OP => med_ctrl_op, -- input + STAT_DEBUG => med_stat_debug, + CTRL_DEBUG => (others => '0') +); --debug_x <= med_stat_debug; @@ -161,124 +169,123 @@ debug_x(19) <= med_dataready_out; -- MED_DATAREADY_IN debug_x(18 downto 16) <= med_packet_num_out; -- MED_PACKET_NUM_IN debug_x(15 downto 0) <= med_data_out; -- MED_DATA_IN --- 16 MED_DATA_IN : in std_logic_vector(15 downto 0); --- 3 MED_PACKET_NUM_IN : in std_logic_vector(2 downto 0); --- 1 MED_DATAREADY_IN : in std_logic; --- 1 MED_READ_OUT : out std_logic; --- 16 MED_DATA_OUT : out std_logic_vector(15 downto 0); --- 3 MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); --- 1 MED_DATAREADY_OUT : out std_logic; --- 1 MED_READ_IN : in std_logic; --- 42 - ------------------------------------------------------------ -- Full featured HADES endpoint ------------------------------------------------------------- THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full -generic map( USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES), - INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before? - REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES), - REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO), - BROADCAST_BITMASK => x"FB", -- RICH uses 0xfffb as subnet mask for broadcasts - REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] - REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] - --standard values for output registers - REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_00000000_00000000", - --set to 0 for unused ctrl registers to save resources - REGIO_USED_CTRL_REGS => "00000001", - --set to 0 for each unused bit in a register - REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & - x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", - REGIO_USE_DAT_PORT => c_YES, - REGIO_INIT_ADDRESS => x"fb00", - REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f", - REGIO_INIT_BOARD_INFO => x"5aa5_3cc3", - REGIO_INIT_ENDPOINT_ID => x"0001", - REGIO_COMPILE_TIME => VERSION_NUMBER_TIME, - REGIO_COMPILE_VERSION => x"0003", - REGIO_HARDWARE_VERSION => x"0002_0000", - REGIO_USE_1WIRE_INTERFACE => c_YES, - CLOCK_FREQUENCY => 100 - ) -port map( CLK => sysclk_in, - RESET => reset_in, - CLK_EN => clk_en, - -- Media direction port - MED_DATAREADY_OUT => med_dataready_out, - MED_DATA_OUT => med_data_out, - MED_PACKET_NUM_OUT => med_packet_num_out, - MED_READ_IN => med_read_in, - MED_DATAREADY_IN => med_dataready_in, - MED_DATA_IN => med_data_in, - MED_PACKET_NUM_IN => med_packet_num_in, - MED_READ_OUT => med_read_out, - MED_STAT_OP_IN => med_stat_op, - MED_CTRL_OP_OUT => med_ctrl_op, - -- LVL1 trigger APL - LVL1_TRG_TYPE_OUT => lvl1_trg_type_out, - LVL1_TRG_RECEIVED_OUT => lvl1_trg_received_out, - LVL1_TRG_NUMBER_OUT => lvl1_trg_number_out, - LVL1_TRG_CODE_OUT => lvl1_trg_code_out, - LVL1_TRG_INFORMATION_OUT => lvl1_trg_information_out, - LVL1_ERROR_PATTERN_IN => lvl1_error_pattern_in, - LVL1_TRG_RELEASE_IN => lvl1_trg_release_in, - LVL1_INT_TRG_NUMBER_OUT => open, -- unknown!!! - -- IPU Port - IPU_NUMBER_OUT => ipu_number_out, - IPU_READOUT_TYPE_OUT => open, -- 4bit readout type - IPU_INFORMATION_OUT => ipu_information_out, - IPU_START_READOUT_OUT => ipu_start_readout_out, - IPU_DATA_IN => ipu_data_in, - IPU_DATAREADY_IN => ipu_dataready_in, - IPU_READOUT_FINISHED_IN => ipu_readout_finished_in, - IPU_READ_OUT => ipu_read_out, - IPU_LENGTH_IN => ipu_length_in, - IPU_ERROR_PATTERN_IN => ipu_error_pattern_in, - -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => common_stat_reg, - REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, - REGIO_REGISTERS_IN => regio_stat_regs, - REGIO_REGISTERS_OUT => regio_ctrl_regs, - COMMON_STAT_REG_STROBE => open, --: out std_logic_vector(std_COMSTATREG-1 downto 0); - COMMON_CTRL_REG_STROBE => open, --: out std_logic_vector(std_COMCTRLREG-1 downto 0); - STAT_REG_STROBE => open, --: out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); - CTRL_REG_STROBE => open, --: out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); - --following ports only used when using internal data port - REGIO_ADDR_OUT => regio_addr_out, - REGIO_READ_ENABLE_OUT => regio_read_enable_out, - REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, - REGIO_DATA_OUT => regio_data_out, - REGIO_DATA_IN => regio_data_in, - REGIO_DATAREADY_IN => regio_dataready_in, - REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, - REGIO_WRITE_ACK_IN => regio_write_ack_in, - REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, - REGIO_TIMEOUT_OUT => regio_timeout_out, - --IDRAM is used if no 1-wire interface, onewire used otherwise - REGIO_IDRAM_DATA_IN => x"0000", -- not used - REGIO_IDRAM_DATA_OUT => open, -- not used - REGIO_IDRAM_ADDR_IN => "000", -- not used - REGIO_IDRAM_WR_IN => '0', -- not used - REGIO_ONEWIRE_INOUT => onewire_inout, - REGIO_ONEWIRE_MONITOR_IN => '1', -- not used - REGIO_ONEWIRE_MONITOR_OUT => open, -- not used - -- New stuff?!? - TRIGGER_MONITOR_IN => timing_trg_found_in, - GLOBAL_TIME_OUT => open, - LOCAL_TIME_OUT => open, - TIME_SINCE_LAST_TRG_OUT => open, - TIMER_US_TICK_OUT => open, - -- Status and debug - STAT_DEBUG_IPU => open, - STAT_DEBUG_1 => stat_debug_1, --open, - STAT_DEBUG_2 => open, - MED_STAT_OP => open, - CTRL_MPLEX => x"00000000", - IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000", - STAT_ONEWIRE => open, - STAT_ADDR_DEBUG => open - ); +generic map( + USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES), + INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before? + REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES), + REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO), + BROADCAST_BITMASK => x"fb", -- RICH uses 0xfffb as subnet mask for broadcasts + REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] + REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0] + --standard values for output registers + REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000", + --set to 0 for unused ctrl registers to save resources + REGIO_USED_CTRL_REGS => "0000000000000001", + --set to 0 for each unused bit in a register + REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", + REGIO_USE_DAT_PORT => c_YES, + REGIO_INIT_ADDRESS => x"fb00", -- useless, as no preload is done in this register! + REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f", + REGIO_INIT_BOARD_INFO => x"5aa5_3cc3", + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_COMPILE_TIME => VERSION_NUMBER_TIME, + REGIO_COMPILE_VERSION => x"0003", + REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature + REGIO_USE_1WIRE_INTERFACE => c_YES, + CLOCK_FREQUENCY => 100 +) +port map( + CLK => sysclk_in, + RESET => reset_in, + CLK_EN => clk_en, + -- Media direction port + MED_DATAREADY_OUT => med_dataready_out, + MED_DATA_OUT => med_data_out, + MED_PACKET_NUM_OUT => med_packet_num_out, + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + -- LVL1 trigger APL + LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received + LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received + LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...) + LVL1_TRG_DATA_VALID_OUT => lvl1_trg_received_out, + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_found_in, + LVL1_TRG_TYPE_OUT => lvl1_trg_type_out, + LVL1_TRG_NUMBER_OUT => lvl1_trg_number_out, + LVL1_TRG_CODE_OUT => lvl1_trg_code_out, + LVL1_TRG_INFORMATION_OUT => lvl1_trg_information_out, + LVL1_ERROR_PATTERN_IN => lvl1_error_pattern_in, + LVL1_TRG_RELEASE_IN => lvl1_trg_release_in, + LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint + -- IPU Port + IPU_NUMBER_OUT => ipu_number_out, + IPU_READOUT_TYPE_OUT => open, -- 4bit readout type + IPU_INFORMATION_OUT => ipu_information_out, + IPU_START_READOUT_OUT => ipu_start_readout_out, + IPU_DATA_IN => ipu_data_in, + IPU_DATAREADY_IN => ipu_dataready_in, + IPU_READOUT_FINISHED_IN => ipu_readout_finished_in, + IPU_READ_OUT => ipu_read_out, + IPU_LENGTH_IN => ipu_length_in, + IPU_ERROR_PATTERN_IN => ipu_error_pattern_in, + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, + REGIO_REGISTERS_IN => regio_stat_regs, + REGIO_REGISTERS_OUT => regio_ctrl_regs, + COMMON_STAT_REG_STROBE => open, + COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number + STAT_REG_STROBE => open, + CTRL_REG_STROBE => open, + --following ports only used when using internal data port + REGIO_ADDR_OUT => regio_addr_out, + REGIO_READ_ENABLE_OUT => regio_read_enable_out, + REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, + REGIO_DATA_OUT => regio_data_out, + REGIO_DATA_IN => regio_data_in, + REGIO_DATAREADY_IN => regio_dataready_in, + REGIO_NO_MORE_DATA_IN => regio_no_more_data_in, + REGIO_WRITE_ACK_IN => regio_write_ack_in, + REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in, + REGIO_TIMEOUT_OUT => regio_timeout_out, + --IDRAM is used if no 1-wire interface, onewire used otherwise + REGIO_IDRAM_DATA_IN => x"0000", -- not used + REGIO_IDRAM_DATA_OUT => open, -- not used + REGIO_IDRAM_ADDR_IN => "000", -- not used + REGIO_IDRAM_WR_IN => '0', -- not used + REGIO_ONEWIRE_INOUT => onewire_inout, + REGIO_ONEWIRE_MONITOR_IN => '1', -- not used + REGIO_ONEWIRE_MONITOR_OUT => open, -- not used + -- New stuff?!? + GLOBAL_TIME_OUT => open, + LOCAL_TIME_OUT => open, + TIME_SINCE_LAST_TRG_OUT => open, + TIMER_TICKS_OUT => open, + -- Status and debug + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => stat_debug_1, --open, + STAT_DEBUG_2 => open, + MED_STAT_OP => open, + CTRL_MPLEX => x"00000000", + IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000", + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open +); -- Control register assignment @@ -291,15 +298,17 @@ common_stat_reg(19 downto 0) <= common_stat_reg_in(19 downto common_ctrl_reg_out <= common_ctrl_reg; -- User status register -regio_stat_regs <= status_in; -control_out <= regio_ctrl_regs; +regio_stat_regs <= status_in; +control_out <= regio_ctrl_regs; +lvl1_int_trg_update_out <= common_ctrl_reg_strobe(1); +lvl1_int_trg_number_out <= common_ctrl_reg(47 downto 32); -- FPGA LEDs led_link_stat <= not med_stat_op(9); -- link status -led_link_rxd <= not med_stat_op(10); -- not med_packet_num_in(2); -- data receive +led_link_rxd <= not med_stat_op(10); -- not med_packet_num_in(2); -- data receive led_link_txd <= not med_stat_op(11); -- data transmit link_bsm_out <= med_stat_op(7 downto 4); -- LSM state bits reset_out <= med_stat_op(13); -- TRB generated reset end architecture; - \ No newline at end of file + \ No newline at end of file diff --git a/src/slave_bus.vhd b/src/slave_bus.vhd index 1560432..82f8856 100644 --- a/src/slave_bus.vhd +++ b/src/slave_bus.vhd @@ -10,741 +10,769 @@ use work.adcmv3_components.all; entity slave_bus is -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- RegIO signals - REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus - REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint - REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint - REGIO_READ_ENABLE_IN : in std_logic; -- read pulse - REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse - REGIO_TIMEOUT_IN : in std_logic; -- access timed out - REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested - REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted - REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now - REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request - -- I2C connections - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; - -- 1Wire connections - ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse) - ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); - BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane - -- SPI connections - SPI_CS_OUT : out std_logic; - SPI_SCK_OUT : out std_logic; - SPI_SDI_IN : in std_logic; - SPI_SDO_OUT : out std_logic; - -- ADC 0 SPI connections - SPI_ADC0_CS_OUT : out std_logic; - SPI_ADC0_SCK_OUT : out std_logic; - SPI_ADC0_SDO_OUT : out std_logic; - ADC0_PLL_LOCKED_IN : in std_logic; - ADC0_PD_OUT : out std_logic; - ADC0_RST_OUT : out std_logic; - ADC0_DEL_OUT : out std_logic_vector(3 downto 0); - ADC0_CLK_IN : in std_logic; - ADC0_DATA_IN : in std_logic_vector(11 downto 0); - ADC0_SEL_OUT : out std_logic_vector(2 downto 0); - APV0_RST_OUT : out std_logic; - -- ADC 1 SPI connections - SPI_ADC1_CS_OUT : out std_logic; - SPI_ADC1_SCK_OUT : out std_logic; - SPI_ADC1_SDO_OUT : out std_logic; - ADC1_PLL_LOCKED_IN : in std_logic; - ADC1_PD_OUT : out std_logic; - ADC1_RST_OUT : out std_logic; - ADC1_DEL_OUT : out std_logic_vector(3 downto 0); - ADC1_CLK_IN : in std_logic; - ADC1_DATA_IN : in std_logic_vector(11 downto 0); - ADC1_SEL_OUT : out std_logic_vector(2 downto 0); - APV1_RST_OUT : out std_logic; - -- User specific inputs / outputs - BACKPLANE_IN : in std_logic_vector(2 downto 0); - -- pedestal interface - PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers - PED_DATA_0_OUT : out std_logic_vector(17 downto 0); - PED_DATA_1_OUT : out std_logic_vector(17 downto 0); - PED_DATA_2_OUT : out std_logic_vector(17 downto 0); - PED_DATA_3_OUT : out std_logic_vector(17 downto 0); - PED_DATA_4_OUT : out std_logic_vector(17 downto 0); - PED_DATA_5_OUT : out std_logic_vector(17 downto 0); - PED_DATA_6_OUT : out std_logic_vector(17 downto 0); - PED_DATA_7_OUT : out std_logic_vector(17 downto 0); - PED_DATA_8_OUT : out std_logic_vector(17 downto 0); - PED_DATA_9_OUT : out std_logic_vector(17 downto 0); - PED_DATA_10_OUT : out std_logic_vector(17 downto 0); - PED_DATA_11_OUT : out std_logic_vector(17 downto 0); - PED_DATA_12_OUT : out std_logic_vector(17 downto 0); - PED_DATA_13_OUT : out std_logic_vector(17 downto 0); - PED_DATA_14_OUT : out std_logic_vector(17 downto 0); - PED_DATA_15_OUT : out std_logic_vector(17 downto 0); - -- threshold interface - THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers - THR_DATA_0_OUT : out std_logic_vector(17 downto 0); - THR_DATA_1_OUT : out std_logic_vector(17 downto 0); - THR_DATA_2_OUT : out std_logic_vector(17 downto 0); - THR_DATA_3_OUT : out std_logic_vector(17 downto 0); - THR_DATA_4_OUT : out std_logic_vector(17 downto 0); - THR_DATA_5_OUT : out std_logic_vector(17 downto 0); - THR_DATA_6_OUT : out std_logic_vector(17 downto 0); - THR_DATA_7_OUT : out std_logic_vector(17 downto 0); - THR_DATA_8_OUT : out std_logic_vector(17 downto 0); - THR_DATA_9_OUT : out std_logic_vector(17 downto 0); - THR_DATA_10_OUT : out std_logic_vector(17 downto 0); - THR_DATA_11_OUT : out std_logic_vector(17 downto 0); - THR_DATA_12_OUT : out std_logic_vector(17 downto 0); - THR_DATA_13_OUT : out std_logic_vector(17 downto 0); - THR_DATA_14_OUT : out std_logic_vector(17 downto 0); - THR_DATA_15_OUT : out std_logic_vector(17 downto 0); - -- APV control / status - CTRL_0_OUT : out std_logic_vector(15 downto 0); - CTRL_1_OUT : out std_logic_vector(15 downto 0); - CTRL_2_OUT : out std_logic_vector(15 downto 0); - CTRL_3_OUT : out std_logic_vector(15 downto 0); - CTRL_4_OUT : out std_logic_vector(15 downto 0); - CTRL_5_OUT : out std_logic_vector(15 downto 0); - CTRL_6_OUT : out std_logic_vector(15 downto 0); - CTRL_7_OUT : out std_logic_vector(15 downto 0); - CTRL_8_OUT : out std_logic_vector(15 downto 0); - CTRL_9_OUT : out std_logic_vector(15 downto 0); - CTRL_10_OUT : out std_logic_vector(15 downto 0); - CTRL_11_OUT : out std_logic_vector(15 downto 0); - CTRL_12_OUT : out std_logic_vector(15 downto 0); - CTRL_13_OUT : out std_logic_vector(15 downto 0); - CTRL_14_OUT : out std_logic_vector(15 downto 0); - CTRL_15_OUT : out std_logic_vector(15 downto 0); - STAT_0_IN : in std_logic_vector(15 downto 0); - STAT_1_IN : in std_logic_vector(15 downto 0); - STAT_2_IN : in std_logic_vector(15 downto 0); - STAT_3_IN : in std_logic_vector(15 downto 0); - STAT_4_IN : in std_logic_vector(15 downto 0); - STAT_5_IN : in std_logic_vector(15 downto 0); - STAT_6_IN : in std_logic_vector(15 downto 0); - STAT_7_IN : in std_logic_vector(15 downto 0); - STAT_8_IN : in std_logic_vector(15 downto 0); - STAT_9_IN : in std_logic_vector(15 downto 0); - STAT_10_IN : in std_logic_vector(15 downto 0); - STAT_11_IN : in std_logic_vector(15 downto 0); - STAT_12_IN : in std_logic_vector(15 downto 0); - STAT_13_IN : in std_logic_vector(15 downto 0); - STAT_14_IN : in std_logic_vector(15 downto 0); - STAT_15_IN : in std_logic_vector(15 downto 0); - -- some control signals - CTRL_LVL_OUT : out std_logic_vector(31 downto 0); - CTRL_TRG_OUT : out std_logic_vector(31 downto 0); - CTRL_PLL_OUT : out std_logic_vector(15 downto 0); - STATUS_PLL_IN : in std_logic_vector(15 downto 0); - -- temporary stuff - TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing! - TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing! - -- Debug - DEBUG_OUT : out std_logic_vector(63 downto 0); - STAT : out std_logic_vector(31 downto 0) - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- RegIO signals + REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus + REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint + REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint + REGIO_READ_ENABLE_IN : in std_logic; -- read pulse + REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse + REGIO_TIMEOUT_IN : in std_logic; -- access timed out + REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested + REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted + REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now + REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request + -- I2C connections + SDA_IN : in std_logic; + SDA_OUT : out std_logic; + SCL_IN : in std_logic; + SCL_OUT : out std_logic; + -- 1Wire connections + ONEWIRE_START_IN : in std_logic; -- start 1Wire scan (pulse) + ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); + BP_ONEWIRE_INOUT : inout std_logic; -- 1Wire ID on backplane + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + SPI_SDI_IN : in std_logic; + SPI_SDO_OUT : out std_logic; + -- ADC 0 SPI connections + SPI_ADC0_CS_OUT : out std_logic; + SPI_ADC0_SCK_OUT : out std_logic; + SPI_ADC0_SDO_OUT : out std_logic; + ADC0_PLL_LOCKED_IN : in std_logic; + ADC0_PD_OUT : out std_logic; + ADC0_RST_OUT : out std_logic; + ADC0_DEL_OUT : out std_logic_vector(3 downto 0); + ADC0_CLK_IN : in std_logic; + ADC0_DATA_IN : in std_logic_vector(11 downto 0); + ADC0_SEL_OUT : out std_logic_vector(2 downto 0); + APV0_RST_OUT : out std_logic; + -- ADC 1 SPI connections + SPI_ADC1_CS_OUT : out std_logic; + SPI_ADC1_SCK_OUT : out std_logic; + SPI_ADC1_SDO_OUT : out std_logic; + ADC1_PLL_LOCKED_IN : in std_logic; + ADC1_PD_OUT : out std_logic; + ADC1_RST_OUT : out std_logic; + ADC1_DEL_OUT : out std_logic_vector(3 downto 0); + ADC1_CLK_IN : in std_logic; + ADC1_DATA_IN : in std_logic_vector(11 downto 0); + ADC1_SEL_OUT : out std_logic_vector(2 downto 0); + APV1_RST_OUT : out std_logic; + -- User specific inputs / outputs + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- pedestal interface + PED_ADDR_IN : in std_logic_vector(6 downto 0); -- pedestal addressing from data handlers + PED_DATA_0_OUT : out std_logic_vector(17 downto 0); + PED_DATA_1_OUT : out std_logic_vector(17 downto 0); + PED_DATA_2_OUT : out std_logic_vector(17 downto 0); + PED_DATA_3_OUT : out std_logic_vector(17 downto 0); + PED_DATA_4_OUT : out std_logic_vector(17 downto 0); + PED_DATA_5_OUT : out std_logic_vector(17 downto 0); + PED_DATA_6_OUT : out std_logic_vector(17 downto 0); + PED_DATA_7_OUT : out std_logic_vector(17 downto 0); + PED_DATA_8_OUT : out std_logic_vector(17 downto 0); + PED_DATA_9_OUT : out std_logic_vector(17 downto 0); + PED_DATA_10_OUT : out std_logic_vector(17 downto 0); + PED_DATA_11_OUT : out std_logic_vector(17 downto 0); + PED_DATA_12_OUT : out std_logic_vector(17 downto 0); + PED_DATA_13_OUT : out std_logic_vector(17 downto 0); + PED_DATA_14_OUT : out std_logic_vector(17 downto 0); + PED_DATA_15_OUT : out std_logic_vector(17 downto 0); + -- threshold interface + THR_ADDR_IN : in std_logic_vector(6 downto 0); -- threshold addressing from data handlers + THR_DATA_0_OUT : out std_logic_vector(17 downto 0); + THR_DATA_1_OUT : out std_logic_vector(17 downto 0); + THR_DATA_2_OUT : out std_logic_vector(17 downto 0); + THR_DATA_3_OUT : out std_logic_vector(17 downto 0); + THR_DATA_4_OUT : out std_logic_vector(17 downto 0); + THR_DATA_5_OUT : out std_logic_vector(17 downto 0); + THR_DATA_6_OUT : out std_logic_vector(17 downto 0); + THR_DATA_7_OUT : out std_logic_vector(17 downto 0); + THR_DATA_8_OUT : out std_logic_vector(17 downto 0); + THR_DATA_9_OUT : out std_logic_vector(17 downto 0); + THR_DATA_10_OUT : out std_logic_vector(17 downto 0); + THR_DATA_11_OUT : out std_logic_vector(17 downto 0); + THR_DATA_12_OUT : out std_logic_vector(17 downto 0); + THR_DATA_13_OUT : out std_logic_vector(17 downto 0); + THR_DATA_14_OUT : out std_logic_vector(17 downto 0); + THR_DATA_15_OUT : out std_logic_vector(17 downto 0); + -- APV control / status + CTRL_0_OUT : out std_logic_vector(15 downto 0); + CTRL_1_OUT : out std_logic_vector(15 downto 0); + CTRL_2_OUT : out std_logic_vector(15 downto 0); + CTRL_3_OUT : out std_logic_vector(15 downto 0); + CTRL_4_OUT : out std_logic_vector(15 downto 0); + CTRL_5_OUT : out std_logic_vector(15 downto 0); + CTRL_6_OUT : out std_logic_vector(15 downto 0); + CTRL_7_OUT : out std_logic_vector(15 downto 0); + CTRL_8_OUT : out std_logic_vector(15 downto 0); + CTRL_9_OUT : out std_logic_vector(15 downto 0); + CTRL_10_OUT : out std_logic_vector(15 downto 0); + CTRL_11_OUT : out std_logic_vector(15 downto 0); + CTRL_12_OUT : out std_logic_vector(15 downto 0); + CTRL_13_OUT : out std_logic_vector(15 downto 0); + CTRL_14_OUT : out std_logic_vector(15 downto 0); + CTRL_15_OUT : out std_logic_vector(15 downto 0); + STAT_0_IN : in std_logic_vector(15 downto 0); + STAT_1_IN : in std_logic_vector(15 downto 0); + STAT_2_IN : in std_logic_vector(15 downto 0); + STAT_3_IN : in std_logic_vector(15 downto 0); + STAT_4_IN : in std_logic_vector(15 downto 0); + STAT_5_IN : in std_logic_vector(15 downto 0); + STAT_6_IN : in std_logic_vector(15 downto 0); + STAT_7_IN : in std_logic_vector(15 downto 0); + STAT_8_IN : in std_logic_vector(15 downto 0); + STAT_9_IN : in std_logic_vector(15 downto 0); + STAT_10_IN : in std_logic_vector(15 downto 0); + STAT_11_IN : in std_logic_vector(15 downto 0); + STAT_12_IN : in std_logic_vector(15 downto 0); + STAT_13_IN : in std_logic_vector(15 downto 0); + STAT_14_IN : in std_logic_vector(15 downto 0); + STAT_15_IN : in std_logic_vector(15 downto 0); + -- some control signals + CTRL_LVL_OUT : out std_logic_vector(31 downto 0); + CTRL_TRG_OUT : out std_logic_vector(31 downto 0); + CTRL_PLL_OUT : out std_logic_vector(15 downto 0); + STATUS_PLL_IN : in std_logic_vector(15 downto 0); + -- temporary stuff + TEST_REG_IN : in std_logic_vector(31 downto 0); -- just for testing! + TEST_REG_OUT : out std_logic_vector(31 downto 0); -- just for testing! + -- Debug + DEBUG_OUT : out std_logic_vector(63 downto 0); + STAT : out std_logic_vector(31 downto 0) +); end entity; architecture Behavioral of slave_bus is - -- Signals - signal slv_read : std_logic_vector(15-1 downto 0); - signal slv_write : std_logic_vector(15-1 downto 0); - signal slv_busy : std_logic_vector(15-1 downto 0); - signal slv_ack : std_logic_vector(15-1 downto 0); - signal slv_addr : std_logic_vector(15*16-1 downto 0); - signal slv_data_rd : std_logic_vector(15*32-1 downto 0); - signal slv_data_wr : std_logic_vector(15*32-1 downto 0); - - -- SPI controller BRAM lines - signal spi_bram_addr : std_logic_vector(7 downto 0); - signal spi_bram_wr_d : std_logic_vector(7 downto 0); - signal spi_bram_rd_d : std_logic_vector(7 downto 0); - signal spi_bram_we : std_logic; - - signal spi_cs : std_logic; - signal spi_sck : std_logic; - signal spi_sdi : std_logic; - signal spi_sdo : std_logic; - signal spi_debug : std_logic_vector(31 downto 0); - - signal ctrl_lvl : std_logic_vector(31 downto 0); - signal ctrl_trg : std_logic_vector(31 downto 0); - signal ctrl_pll : std_logic_vector(15 downto 0); - - signal debug : std_logic_vector(63 downto 0); - signal onewire_debug : std_logic_vector(63 downto 0); - +-- Signals +signal slv_read : std_logic_vector(15-1 downto 0); +signal slv_write : std_logic_vector(15-1 downto 0); +signal slv_busy : std_logic_vector(15-1 downto 0); +signal slv_ack : std_logic_vector(15-1 downto 0); +signal slv_addr : std_logic_vector(15*16-1 downto 0); +signal slv_data_rd : std_logic_vector(15*32-1 downto 0); +signal slv_data_wr : std_logic_vector(15*32-1 downto 0); + +-- SPI controller BRAM lines +signal spi_bram_addr : std_logic_vector(7 downto 0); +signal spi_bram_wr_d : std_logic_vector(7 downto 0); +signal spi_bram_rd_d : std_logic_vector(7 downto 0); +signal spi_bram_we : std_logic; + +signal spi_cs : std_logic; +signal spi_sck : std_logic; +signal spi_sdi : std_logic; +signal spi_sdo : std_logic; +signal spi_debug : std_logic_vector(31 downto 0); + +signal ctrl_lvl : std_logic_vector(31 downto 0); +signal ctrl_trg : std_logic_vector(31 downto 0); +signal ctrl_pll : std_logic_vector(15 downto 0); + +signal debug : std_logic_vector(63 downto 0); +signal onewire_debug : std_logic_vector(63 downto 0); + begin -- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus THE_BUS_HANDLER: trb_net16_regio_bus_handler -generic map( PORT_NUMBER => 15, - PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories - 1 => x"a800", -- threshold memories - 2 => x"8040", -- I2C master - 3 => x"c000", -- 1Wire master + memory - 4 => x"d000", -- SPI master - 5 => x"d100", -- SPI data memory - 6 => x"d010", -- ADC0 SPI - 7 => x"d020", -- ADC1 SPI - 8 => x"b000", -- APV control / status - 9 => x"b010", -- ADC level settings - 10 => x"b020", -- trigger settings - 11 => x"b030", -- PLL settings - 12 => x"f000", -- ADC 0 snooper - 13 => x"f800", -- ADC 1 snooper - 14 => x"8000", -- test register (busy) - others => x"0000"), - PORT_ADDR_MASK => ( 0 => 11, -- pedestal memories - 1 => 11, -- threshold memories - 2 => 0, -- I2C master - 3 => 6, -- 1Wire master + memory - 4 => 1, -- SPI master - 5 => 6, -- SPI data memory - 6 => 0, -- ADC0 SPI - 7 => 0, -- ADC1 SPI - 8 => 4, -- APV control / status - 9 => 0, -- ADC level settings - 10 => 0, -- trigger settings - 11 => 0, -- PLL settings - 12 => 10, -- ADC 0 snooper - 13 => 10, -- ADC 1 snooper - 14 => 0, -- test register (normal) - others => 0) - ) -port map( CLK => clk_in, - RESET => reset_in, - DAT_ADDR_IN => regio_addr_in, - DAT_DATA_IN => regio_data_in, - DAT_DATA_OUT => regio_data_out, - DAT_READ_ENABLE_IN => regio_read_enable_in, - DAT_WRITE_ENABLE_IN => regio_write_enable_in, - DAT_TIMEOUT_IN => regio_timeout_in, - DAT_DATAREADY_OUT => regio_dataready_out, - DAT_WRITE_ACK_OUT => regio_write_ack_out, - DAT_NO_MORE_DATA_OUT => regio_no_more_data_out, - DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_out, - -- pedestal memories - BUS_READ_ENABLE_OUT(0) => slv_read(0), - BUS_WRITE_ENABLE_OUT(0) => slv_write(0), - BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32), - BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32), - BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16), - BUS_TIMEOUT_OUT(0) => open, - BUS_DATAREADY_IN(0) => slv_ack(0), - BUS_WRITE_ACK_IN(0) => slv_ack(0), - BUS_NO_MORE_DATA_IN(0) => slv_busy(0), - BUS_UNKNOWN_ADDR_IN(0) => '0', - -- threshold memories - BUS_READ_ENABLE_OUT(1) => slv_read(1), - BUS_WRITE_ENABLE_OUT(1) => slv_write(1), - BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32), - BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32), - BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16), - BUS_TIMEOUT_OUT(1) => open, - BUS_DATAREADY_IN(1) => slv_ack(1), - BUS_WRITE_ACK_IN(1) => slv_ack(1), - BUS_NO_MORE_DATA_IN(1) => slv_busy(1), - BUS_UNKNOWN_ADDR_IN(1) => '0', - -- I2C master - BUS_READ_ENABLE_OUT(2) => slv_read(2), - BUS_WRITE_ENABLE_OUT(2) => slv_write(2), - BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32), - BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32), - BUS_ADDR_OUT(2*16+15 downto 2*16) => open, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATAREADY_IN(2) => slv_ack(2), - BUS_WRITE_ACK_IN(2) => slv_ack(2), - BUS_NO_MORE_DATA_IN(2) => slv_busy(2), - BUS_UNKNOWN_ADDR_IN(2) => '0', - -- OneWire master - BUS_READ_ENABLE_OUT(3) => slv_read(3), - BUS_WRITE_ENABLE_OUT(3) => slv_write(3), - BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32), - BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32), - BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16), - BUS_TIMEOUT_OUT(3) => open, - BUS_DATAREADY_IN(3) => slv_ack(3), - BUS_WRITE_ACK_IN(3) => slv_ack(3), - BUS_NO_MORE_DATA_IN(3) => slv_busy(3), - BUS_UNKNOWN_ADDR_IN(3) => '0', - -- SPI control registers - BUS_READ_ENABLE_OUT(4) => slv_read(4), - BUS_WRITE_ENABLE_OUT(4) => slv_write(4), - BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32), - BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32), - BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16), - BUS_TIMEOUT_OUT(4) => open, - BUS_DATAREADY_IN(4) => slv_ack(4), - BUS_WRITE_ACK_IN(4) => slv_ack(4), - BUS_NO_MORE_DATA_IN(4) => slv_busy(4), - BUS_UNKNOWN_ADDR_IN(4) => '0', - -- SPI data memory - BUS_READ_ENABLE_OUT(5) => slv_read(5), - BUS_WRITE_ENABLE_OUT(5) => slv_write(5), - BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32), - BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32), - BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16), - BUS_TIMEOUT_OUT(5) => open, - BUS_DATAREADY_IN(5) => slv_ack(5), - BUS_WRITE_ACK_IN(5) => slv_ack(5), - BUS_NO_MORE_DATA_IN(5) => slv_busy(5), - BUS_UNKNOWN_ADDR_IN(5) => '0', - -- ADC 0 SPI control registers - BUS_READ_ENABLE_OUT(6) => slv_read(6), - BUS_WRITE_ENABLE_OUT(6) => slv_write(6), - BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32), - BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32), - BUS_ADDR_OUT(6*16+15 downto 6*16) => open, - BUS_TIMEOUT_OUT(6) => open, - BUS_DATAREADY_IN(6) => slv_ack(6), - BUS_WRITE_ACK_IN(6) => slv_ack(6), - BUS_NO_MORE_DATA_IN(6) => slv_busy(6), - BUS_UNKNOWN_ADDR_IN(6) => '0', - -- ADC 1 SPI control registers - BUS_READ_ENABLE_OUT(7) => slv_read(7), - BUS_WRITE_ENABLE_OUT(7) => slv_write(7), - BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32), - BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32), - BUS_ADDR_OUT(7*16+15 downto 7*16) => open, - BUS_TIMEOUT_OUT(7) => open, - BUS_DATAREADY_IN(7) => slv_ack(7), - BUS_WRITE_ACK_IN(7) => slv_ack(7), - BUS_NO_MORE_DATA_IN(7) => slv_busy(7), - BUS_UNKNOWN_ADDR_IN(7) => '0', - -- APV control / status registers - BUS_READ_ENABLE_OUT(8) => slv_read(8), - BUS_WRITE_ENABLE_OUT(8) => slv_write(8), - BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32), - BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32), - BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16), - BUS_TIMEOUT_OUT(8) => open, - BUS_DATAREADY_IN(8) => slv_ack(8), - BUS_WRITE_ACK_IN(8) => slv_ack(8), - BUS_NO_MORE_DATA_IN(8) => slv_busy(8), - BUS_UNKNOWN_ADDR_IN(8) => '0', - -- ADC / PLL / trigger ctrl register - BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9), - BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9), - BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32), - BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32), - BUS_ADDR_OUT(11*16+15 downto 9*16) => open, - BUS_TIMEOUT_OUT(11 downto 9) => open, - BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9), - BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9), - BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9), - BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'), - -- ADC0 snooper - BUS_READ_ENABLE_OUT(12) => slv_read(12), - BUS_WRITE_ENABLE_OUT(12) => slv_write(12), - BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32), - BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32), - BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16), - BUS_TIMEOUT_OUT(12) => open, - BUS_DATAREADY_IN(12) => slv_ack(12), - BUS_WRITE_ACK_IN(12) => slv_ack(12), - BUS_NO_MORE_DATA_IN(12) => slv_busy(12), - BUS_UNKNOWN_ADDR_IN(12) => '0', - -- ADC1 snooper - BUS_READ_ENABLE_OUT(13) => slv_read(13), - BUS_WRITE_ENABLE_OUT(13) => slv_write(13), - BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32), - BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32), - BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16), - BUS_TIMEOUT_OUT(13) => open, - BUS_DATAREADY_IN(13) => slv_ack(13), - BUS_WRITE_ACK_IN(13) => slv_ack(13), - BUS_NO_MORE_DATA_IN(13) => slv_busy(13), - BUS_UNKNOWN_ADDR_IN(13) => '0', - -- Test register - BUS_READ_ENABLE_OUT(14) => slv_read(14), - BUS_WRITE_ENABLE_OUT(14) => slv_write(14), - BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32), - BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32), - BUS_ADDR_OUT(14*16+15 downto 14*16) => open, - BUS_TIMEOUT_OUT(14) => open, - BUS_DATAREADY_IN(14) => slv_ack(14), - BUS_WRITE_ACK_IN(14) => slv_ack(14), - BUS_NO_MORE_DATA_IN(14) => slv_busy(14), - BUS_UNKNOWN_ADDR_IN(14) => '0', - -- debug - STAT_DEBUG => stat - ); +generic map( + PORT_NUMBER => 15, + PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories + 1 => x"a800", -- threshold memories + 2 => x"8040", -- I2C master + 3 => x"c000", -- 1Wire master + memory + 4 => x"d000", -- SPI master + 5 => x"d100", -- SPI data memory + 6 => x"d010", -- ADC0 SPI + 7 => x"d020", -- ADC1 SPI + 8 => x"b000", -- APV control / status + 9 => x"b010", -- ADC level settings + 10 => x"b020", -- trigger settings + 11 => x"b030", -- PLL settings + 12 => x"f000", -- ADC 0 snooper + 13 => x"f800", -- ADC 1 snooper + 14 => x"8000", -- test register (busy) + others => x"0000"), + PORT_ADDR_MASK => ( 0 => 11, -- pedestal memories + 1 => 11, -- threshold memories + 2 => 0, -- I2C master + 3 => 6, -- 1Wire master + memory + 4 => 1, -- SPI master + 5 => 6, -- SPI data memory + 6 => 0, -- ADC0 SPI + 7 => 0, -- ADC1 SPI + 8 => 4, -- APV control / status + 9 => 0, -- ADC level settings + 10 => 0, -- trigger settings + 11 => 0, -- PLL settings + 12 => 10, -- ADC 0 snooper + 13 => 10, -- ADC 1 snooper + 14 => 0, -- test register (normal) + others => 0) +) +port map( + CLK => clk_in, + RESET => reset_in, + DAT_ADDR_IN => regio_addr_in, + DAT_DATA_IN => regio_data_in, + DAT_DATA_OUT => regio_data_out, + DAT_READ_ENABLE_IN => regio_read_enable_in, + DAT_WRITE_ENABLE_IN => regio_write_enable_in, + DAT_TIMEOUT_IN => regio_timeout_in, + DAT_DATAREADY_OUT => regio_dataready_out, + DAT_WRITE_ACK_OUT => regio_write_ack_out, + DAT_NO_MORE_DATA_OUT => regio_no_more_data_out, + DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_out, + -- pedestal memories + BUS_READ_ENABLE_OUT(0) => slv_read(0), + BUS_WRITE_ENABLE_OUT(0) => slv_write(0), + BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32), + BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32), + BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16), + BUS_TIMEOUT_OUT(0) => open, + BUS_DATAREADY_IN(0) => slv_ack(0), + BUS_WRITE_ACK_IN(0) => slv_ack(0), + BUS_NO_MORE_DATA_IN(0) => slv_busy(0), + BUS_UNKNOWN_ADDR_IN(0) => '0', + -- threshold memories + BUS_READ_ENABLE_OUT(1) => slv_read(1), + BUS_WRITE_ENABLE_OUT(1) => slv_write(1), + BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32), + BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32), + BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16), + BUS_TIMEOUT_OUT(1) => open, + BUS_DATAREADY_IN(1) => slv_ack(1), + BUS_WRITE_ACK_IN(1) => slv_ack(1), + BUS_NO_MORE_DATA_IN(1) => slv_busy(1), + BUS_UNKNOWN_ADDR_IN(1) => '0', + -- I2C master + BUS_READ_ENABLE_OUT(2) => slv_read(2), + BUS_WRITE_ENABLE_OUT(2) => slv_write(2), + BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32), + BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32), + BUS_ADDR_OUT(2*16+15 downto 2*16) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATAREADY_IN(2) => slv_ack(2), + BUS_WRITE_ACK_IN(2) => slv_ack(2), + BUS_NO_MORE_DATA_IN(2) => slv_busy(2), + BUS_UNKNOWN_ADDR_IN(2) => '0', + -- OneWire master + BUS_READ_ENABLE_OUT(3) => slv_read(3), + BUS_WRITE_ENABLE_OUT(3) => slv_write(3), + BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32), + BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32), + BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16), + BUS_TIMEOUT_OUT(3) => open, + BUS_DATAREADY_IN(3) => slv_ack(3), + BUS_WRITE_ACK_IN(3) => slv_ack(3), + BUS_NO_MORE_DATA_IN(3) => slv_busy(3), + BUS_UNKNOWN_ADDR_IN(3) => '0', + -- SPI control registers + BUS_READ_ENABLE_OUT(4) => slv_read(4), + BUS_WRITE_ENABLE_OUT(4) => slv_write(4), + BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32), + BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32), + BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16), + BUS_TIMEOUT_OUT(4) => open, + BUS_DATAREADY_IN(4) => slv_ack(4), + BUS_WRITE_ACK_IN(4) => slv_ack(4), + BUS_NO_MORE_DATA_IN(4) => slv_busy(4), + BUS_UNKNOWN_ADDR_IN(4) => '0', + -- SPI data memory + BUS_READ_ENABLE_OUT(5) => slv_read(5), + BUS_WRITE_ENABLE_OUT(5) => slv_write(5), + BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32), + BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32), + BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16), + BUS_TIMEOUT_OUT(5) => open, + BUS_DATAREADY_IN(5) => slv_ack(5), + BUS_WRITE_ACK_IN(5) => slv_ack(5), + BUS_NO_MORE_DATA_IN(5) => slv_busy(5), + BUS_UNKNOWN_ADDR_IN(5) => '0', + -- ADC 0 SPI control registers + BUS_READ_ENABLE_OUT(6) => slv_read(6), + BUS_WRITE_ENABLE_OUT(6) => slv_write(6), + BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32), + BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32), + BUS_ADDR_OUT(6*16+15 downto 6*16) => open, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATAREADY_IN(6) => slv_ack(6), + BUS_WRITE_ACK_IN(6) => slv_ack(6), + BUS_NO_MORE_DATA_IN(6) => slv_busy(6), + BUS_UNKNOWN_ADDR_IN(6) => '0', + -- ADC 1 SPI control registers + BUS_READ_ENABLE_OUT(7) => slv_read(7), + BUS_WRITE_ENABLE_OUT(7) => slv_write(7), + BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32), + BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32), + BUS_ADDR_OUT(7*16+15 downto 7*16) => open, + BUS_TIMEOUT_OUT(7) => open, + BUS_DATAREADY_IN(7) => slv_ack(7), + BUS_WRITE_ACK_IN(7) => slv_ack(7), + BUS_NO_MORE_DATA_IN(7) => slv_busy(7), + BUS_UNKNOWN_ADDR_IN(7) => '0', + -- APV control / status registers + BUS_READ_ENABLE_OUT(8) => slv_read(8), + BUS_WRITE_ENABLE_OUT(8) => slv_write(8), + BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32), + BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32), + BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16), + BUS_TIMEOUT_OUT(8) => open, + BUS_DATAREADY_IN(8) => slv_ack(8), + BUS_WRITE_ACK_IN(8) => slv_ack(8), + BUS_NO_MORE_DATA_IN(8) => slv_busy(8), + BUS_UNKNOWN_ADDR_IN(8) => '0', + -- ADC / PLL / trigger ctrl register + BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9), + BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9), + BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32), + BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32), + BUS_ADDR_OUT(11*16+15 downto 9*16) => open, + BUS_TIMEOUT_OUT(11 downto 9) => open, + BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9), + BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9), + BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9), + BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'), + -- ADC0 snooper + BUS_READ_ENABLE_OUT(12) => slv_read(12), + BUS_WRITE_ENABLE_OUT(12) => slv_write(12), + BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32), + BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32), + BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16), + BUS_TIMEOUT_OUT(12) => open, + BUS_DATAREADY_IN(12) => slv_ack(12), + BUS_WRITE_ACK_IN(12) => slv_ack(12), + BUS_NO_MORE_DATA_IN(12) => slv_busy(12), + BUS_UNKNOWN_ADDR_IN(12) => '0', + -- ADC1 snooper + BUS_READ_ENABLE_OUT(13) => slv_read(13), + BUS_WRITE_ENABLE_OUT(13) => slv_write(13), + BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32), + BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32), + BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16), + BUS_TIMEOUT_OUT(13) => open, + BUS_DATAREADY_IN(13) => slv_ack(13), + BUS_WRITE_ACK_IN(13) => slv_ack(13), + BUS_NO_MORE_DATA_IN(13) => slv_busy(13), + BUS_UNKNOWN_ADDR_IN(13) => '0', + -- Test register + BUS_READ_ENABLE_OUT(14) => slv_read(14), + BUS_WRITE_ENABLE_OUT(14) => slv_write(14), + BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32), + BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32), + BUS_ADDR_OUT(14*16+15 downto 14*16) => open, + BUS_TIMEOUT_OUT(14) => open, + BUS_DATAREADY_IN(14) => slv_ack(14), + BUS_WRITE_ACK_IN(14) => slv_ack(14), + BUS_NO_MORE_DATA_IN(14) => slv_busy(14), + BUS_UNKNOWN_ADDR_IN(14) => '0', + -- debug + STAT_DEBUG => stat +); ------------------------------------------------------------------------------------ -- pedestal memories (16x128 = 2048, 18bit) ------------------------------------------------------------------------------------ THE_PED_MEM: slv_ped_thr_mem -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- Slave bus - SLV_ADDR_IN => slv_addr(0*16+10 downto 0*16), - SLV_READ_IN => slv_read(0), - SLV_WRITE_IN => slv_write(0), - SLV_ACK_OUT => slv_ack(0), - SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32), - SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32), - -- backplane identifier - BACKPLANE_IN => backplane_in, - -- I/O to the backend - MEM_CLK_IN => clk_in, - MEM_ADDR_IN => ped_addr_in, - MEM_0_D_OUT => ped_data_0_out, - MEM_1_D_OUT => ped_data_1_out, - MEM_2_D_OUT => ped_data_2_out, - MEM_3_D_OUT => ped_data_3_out, - MEM_4_D_OUT => ped_data_4_out, - MEM_5_D_OUT => ped_data_5_out, - MEM_6_D_OUT => ped_data_6_out, - MEM_7_D_OUT => ped_data_7_out, - MEM_8_D_OUT => ped_data_8_out, - MEM_9_D_OUT => ped_data_9_out, - MEM_10_D_OUT => ped_data_10_out, - MEM_11_D_OUT => ped_data_11_out, - MEM_12_D_OUT => ped_data_12_out, - MEM_13_D_OUT => ped_data_13_out, - MEM_14_D_OUT => ped_data_14_out, - MEM_15_D_OUT => ped_data_15_out, - -- Status lines - STAT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(0*16+10 downto 0*16), + SLV_READ_IN => slv_read(0), + SLV_WRITE_IN => slv_write(0), + SLV_ACK_OUT => slv_ack(0), + SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32), + SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32), + -- backplane identifier + BACKPLANE_IN => backplane_in, + -- I/O to the backend + MEM_CLK_IN => clk_in, + MEM_ADDR_IN => ped_addr_in, + MEM_0_D_OUT => ped_data_0_out, + MEM_1_D_OUT => ped_data_1_out, + MEM_2_D_OUT => ped_data_2_out, + MEM_3_D_OUT => ped_data_3_out, + MEM_4_D_OUT => ped_data_4_out, + MEM_5_D_OUT => ped_data_5_out, + MEM_6_D_OUT => ped_data_6_out, + MEM_7_D_OUT => ped_data_7_out, + MEM_8_D_OUT => ped_data_8_out, + MEM_9_D_OUT => ped_data_9_out, + MEM_10_D_OUT => ped_data_10_out, + MEM_11_D_OUT => ped_data_11_out, + MEM_12_D_OUT => ped_data_12_out, + MEM_13_D_OUT => ped_data_13_out, + MEM_14_D_OUT => ped_data_14_out, + MEM_15_D_OUT => ped_data_15_out, + -- Status lines + STAT => open +); slv_busy(0) <= '0'; ------------------------------------------------------------------------------------ -- threshold memories (16x128 = 2048, 18bit) ------------------------------------------------------------------------------------ THE_THR_MEM: slv_ped_thr_mem -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- Slave bus - SLV_ADDR_IN => slv_addr(1*16+10 downto 1*16), - SLV_READ_IN => slv_read(1), - SLV_WRITE_IN => slv_write(1), - SLV_ACK_OUT => slv_ack(1), - SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32), - SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32), - -- backplane identifier - BACKPLANE_IN => backplane_in, - -- I/O to the backend - MEM_CLK_IN => clk_in, - MEM_ADDR_IN => thr_addr_in, - MEM_0_D_OUT => thr_data_0_out, - MEM_1_D_OUT => thr_data_1_out, - MEM_2_D_OUT => thr_data_2_out, - MEM_3_D_OUT => thr_data_3_out, - MEM_4_D_OUT => thr_data_4_out, - MEM_5_D_OUT => thr_data_5_out, - MEM_6_D_OUT => thr_data_6_out, - MEM_7_D_OUT => thr_data_7_out, - MEM_8_D_OUT => thr_data_8_out, - MEM_9_D_OUT => thr_data_9_out, - MEM_10_D_OUT => thr_data_10_out, - MEM_11_D_OUT => thr_data_11_out, - MEM_12_D_OUT => thr_data_12_out, - MEM_13_D_OUT => thr_data_13_out, - MEM_14_D_OUT => thr_data_14_out, - MEM_15_D_OUT => thr_data_15_out, - -- Status lines - STAT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(1*16+10 downto 1*16), + SLV_READ_IN => slv_read(1), + SLV_WRITE_IN => slv_write(1), + SLV_ACK_OUT => slv_ack(1), + SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32), + SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32), + -- backplane identifier + BACKPLANE_IN => backplane_in, + -- I/O to the backend + MEM_CLK_IN => clk_in, + MEM_ADDR_IN => thr_addr_in, + MEM_0_D_OUT => thr_data_0_out, + MEM_1_D_OUT => thr_data_1_out, + MEM_2_D_OUT => thr_data_2_out, + MEM_3_D_OUT => thr_data_3_out, + MEM_4_D_OUT => thr_data_4_out, + MEM_5_D_OUT => thr_data_5_out, + MEM_6_D_OUT => thr_data_6_out, + MEM_7_D_OUT => thr_data_7_out, + MEM_8_D_OUT => thr_data_8_out, + MEM_9_D_OUT => thr_data_9_out, + MEM_10_D_OUT => thr_data_10_out, + MEM_11_D_OUT => thr_data_11_out, + MEM_12_D_OUT => thr_data_12_out, + MEM_13_D_OUT => thr_data_13_out, + MEM_14_D_OUT => thr_data_14_out, + MEM_15_D_OUT => thr_data_15_out, + -- Status lines + STAT => open +); slv_busy(1) <= '0'; ------------------------------------------------------------------------------------ -- I2C master block for accessing APVs ------------------------------------------------------------------------------------ THE_I2C_MASTER: i2c_master -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- Slave bus - SLV_READ_IN => slv_read(2), - SLV_WRITE_IN => slv_write(2), - SLV_BUSY_OUT => slv_busy(2), - SLV_ACK_OUT => slv_ack(2), - SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32), - SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32), - -- I2C connections - SDA_IN => sda_in, - SDA_OUT => sda_out, - SCL_IN => scl_in, - SCL_OUT => scl_out, - -- Status lines - STAT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_READ_IN => slv_read(2), + SLV_WRITE_IN => slv_write(2), + SLV_BUSY_OUT => slv_busy(2), + SLV_ACK_OUT => slv_ack(2), + SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32), + SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32), + -- I2C connections + SDA_IN => sda_in, + SDA_OUT => sda_out, + SCL_IN => scl_in, + SCL_OUT => scl_out, + -- Status lines + STAT => open +); ------------------------------------------------------------------------------------ -- 1Wire master including status memory ------------------------------------------------------------------------------------ THE_ONEWIRE_MEMORY: slv_onewire_memory -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- Slave bus - SLV_ADDR_IN => slv_addr(3*16+5 downto 3*16), - SLV_READ_IN => slv_read(3), - SLV_WRITE_IN => slv_write(3), - SLV_ACK_OUT => slv_ack(3), - SLV_BUSY_OUT => open, - SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32), - -- backplane identifier - BACKPLANE_IN => backplane_in, - -- 1Wire lines - ONEWIRE_START_IN => onewire_start_in, -- not used yet - ONEWIRE_INOUT => onewire_inout, - BP_ONEWIRE_INOUT => bp_onewire_inout, - -- Status lines - STAT => onewire_debug --open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(3*16+5 downto 3*16), + SLV_READ_IN => slv_read(3), + SLV_WRITE_IN => slv_write(3), + SLV_ACK_OUT => slv_ack(3), + SLV_BUSY_OUT => open, + SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32), + -- backplane identifier + BACKPLANE_IN => backplane_in, + -- 1Wire lines + ONEWIRE_START_IN => onewire_start_in, -- not used yet + ONEWIRE_INOUT => onewire_inout, + BP_ONEWIRE_INOUT => bp_onewire_inout, + -- Status lines + STAT => onewire_debug --open +); slv_busy(3) <= '0'; ------------------------------------------------------------------------------------ -- SPI master ------------------------------------------------------------------------------------ THE_SPI_MASTER: spi_master -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- Slave bus - BUS_READ_IN => slv_read(4), - BUS_WRITE_IN => slv_write(4), - BUS_BUSY_OUT => slv_busy(4), - BUS_ACK_OUT => slv_ack(4), - BUS_ADDR_IN => slv_addr(4*16+0 downto 4*16), - BUS_DATA_IN => slv_data_wr(4*32+31 downto 4*32), - BUS_DATA_OUT => slv_data_rd(4*32+31 downto 4*32), - -- SPI connections - SPI_CS_OUT => spi_cs, - SPI_SDI_IN => spi_sdi, - SPI_SDO_OUT => spi_sdo, - SPI_SCK_OUT => spi_sck, - -- BRAM for read/write data - BRAM_A_OUT => spi_bram_addr, - BRAM_WR_D_IN => spi_bram_wr_d, - BRAM_RD_D_OUT => spi_bram_rd_d, - BRAM_WE_OUT => spi_bram_we, - -- Status lines - STAT => spi_debug --open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + BUS_READ_IN => slv_read(4), + BUS_WRITE_IN => slv_write(4), + BUS_BUSY_OUT => slv_busy(4), + BUS_ACK_OUT => slv_ack(4), + BUS_ADDR_IN => slv_addr(4*16+0 downto 4*16), + BUS_DATA_IN => slv_data_wr(4*32+31 downto 4*32), + BUS_DATA_OUT => slv_data_rd(4*32+31 downto 4*32), + -- SPI connections + SPI_CS_OUT => spi_cs, + SPI_SDI_IN => spi_sdi, + SPI_SDO_OUT => spi_sdo, + SPI_SCK_OUT => spi_sck, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => spi_debug --open +); ------------------------------------------------------------------------------------ -- data memory for SPI accesses ------------------------------------------------------------------------------------ THE_SPI_MEMORY: spi_databus_memory -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- Slave bus - BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16), - BUS_READ_IN => slv_read(5), - BUS_WRITE_IN => slv_write(5), - BUS_ACK_OUT => slv_ack(5), - BUS_DATA_IN => slv_data_wr(5*32+31 downto 5*32), - BUS_DATA_OUT => slv_data_rd(5*32+31 downto 5*32), - -- state machine connections - BRAM_ADDR_IN => spi_bram_addr, - BRAM_WR_D_OUT => spi_bram_wr_d, - BRAM_RD_D_IN => spi_bram_rd_d, - BRAM_WE_IN => spi_bram_we, - -- Status lines - STAT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16), + BUS_READ_IN => slv_read(5), + BUS_WRITE_IN => slv_write(5), + BUS_ACK_OUT => slv_ack(5), + BUS_DATA_IN => slv_data_wr(5*32+31 downto 5*32), + BUS_DATA_OUT => slv_data_rd(5*32+31 downto 5*32), + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open +); slv_busy(5) <= '0'; ------------------------------------------------------------------------------------ -- ADC0 SPI master ------------------------------------------------------------------------------------ THE_SPI_ADC0_MASTER: spi_adc_master -generic map( RESET_VALUE_CTRL => x"60" ) -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- Slave bus - SLV_READ_IN => slv_read(6), - SLV_WRITE_IN => slv_write(6), - SLV_BUSY_OUT => slv_busy(6), - SLV_ACK_OUT => slv_ack(6), - SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32), - SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32), - -- SPI connections - SPI_CS_OUT => spi_adc0_cs_out, - SPI_SDO_OUT => spi_adc0_sdo_out, - SPI_SCK_OUT => spi_adc0_sck_out, - -- ADC connections - ADC_LOCKED_IN => adc0_pll_locked_in, - ADC_PD_OUT => adc0_pd_out, - ADC_RST_OUT => adc0_rst_out, - ADC_DEL_OUT => adc0_del_out, - -- APV connections - APV_RST_OUT => apv0_rst_out, - -- Status lines - STAT => open - ); +generic map( + RESET_VALUE_CTRL => x"60" +) +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_READ_IN => slv_read(6), + SLV_WRITE_IN => slv_write(6), + SLV_BUSY_OUT => slv_busy(6), + SLV_ACK_OUT => slv_ack(6), + SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32), + SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32), + -- SPI connections + SPI_CS_OUT => spi_adc0_cs_out, + SPI_SDO_OUT => spi_adc0_sdo_out, + SPI_SCK_OUT => spi_adc0_sck_out, + -- ADC connections + ADC_LOCKED_IN => adc0_pll_locked_in, + ADC_PD_OUT => adc0_pd_out, + ADC_RST_OUT => adc0_rst_out, + ADC_DEL_OUT => adc0_del_out, + -- APV connections + APV_RST_OUT => apv0_rst_out, + -- Status lines + STAT => open +); ------------------------------------------------------------------------------------ -- ADC1 SPI master ------------------------------------------------------------------------------------ THE_SPI_ADC1_MASTER: spi_adc_master -generic map( RESET_VALUE_CTRL => x"60" ) -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- Slave bus - SLV_READ_IN => slv_read(7), - SLV_WRITE_IN => slv_write(7), - SLV_BUSY_OUT => slv_busy(7), - SLV_ACK_OUT => slv_ack(7), - SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32), - SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32), - -- SPI connections - SPI_CS_OUT => spi_adc1_cs_out, - SPI_SDO_OUT => spi_adc1_sdo_out, - SPI_SCK_OUT => spi_adc1_sck_out, - -- ADC connections - ADC_LOCKED_IN => adc1_pll_locked_in, - ADC_PD_OUT => adc1_pd_out, - ADC_RST_OUT => adc1_rst_out, - ADC_DEL_OUT => adc1_del_out, - -- APV connections - APV_RST_OUT => apv1_rst_out, - -- Status lines - STAT => open - ); +generic map( + RESET_VALUE_CTRL => x"60" +) +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_READ_IN => slv_read(7), + SLV_WRITE_IN => slv_write(7), + SLV_BUSY_OUT => slv_busy(7), + SLV_ACK_OUT => slv_ack(7), + SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32), + SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32), + -- SPI connections + SPI_CS_OUT => spi_adc1_cs_out, + SPI_SDO_OUT => spi_adc1_sdo_out, + SPI_SCK_OUT => spi_adc1_sck_out, + -- ADC connections + ADC_LOCKED_IN => adc1_pll_locked_in, + ADC_PD_OUT => adc1_pd_out, + ADC_RST_OUT => adc1_rst_out, + ADC_DEL_OUT => adc1_del_out, + -- APV connections + APV_RST_OUT => apv1_rst_out, + -- Status lines + STAT => open +); ------------------------------------------------------------------------------------ -- APV control / status registers ------------------------------------------------------------------------------------ THE_SLV_REGISTER_BANK: slv_register_bank -generic map( RESET_VALUE => x"0001" ) -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- Slave bus - SLV_ADDR_IN => slv_addr(8*16+3 downto 8*16), - SLV_READ_IN => slv_read(8), - SLV_WRITE_IN => slv_write(8), - SLV_ACK_OUT => slv_ack(8), - SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32), - SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32), - -- I/O to the backend - BACKPLANE_IN => backplane_in, - CTRL_0_OUT => ctrl_0_out, - CTRL_1_OUT => ctrl_1_out, - CTRL_2_OUT => ctrl_2_out, - CTRL_3_OUT => ctrl_3_out, - CTRL_4_OUT => ctrl_4_out, - CTRL_5_OUT => ctrl_5_out, - CTRL_6_OUT => ctrl_6_out, - CTRL_7_OUT => ctrl_7_out, - CTRL_8_OUT => ctrl_8_out, - CTRL_9_OUT => ctrl_9_out, - CTRL_10_OUT => ctrl_10_out, - CTRL_11_OUT => ctrl_11_out, - CTRL_12_OUT => ctrl_12_out, - CTRL_13_OUT => ctrl_13_out, - CTRL_14_OUT => ctrl_14_out, - CTRL_15_OUT => ctrl_15_out, - STAT_0_IN => stat_0_in, - STAT_1_IN => stat_1_in, - STAT_2_IN => stat_2_in, - STAT_3_IN => stat_3_in, - STAT_4_IN => stat_4_in, - STAT_5_IN => stat_5_in, - STAT_6_IN => stat_6_in, - STAT_7_IN => stat_7_in, - STAT_8_IN => stat_8_in, - STAT_9_IN => stat_9_in, - STAT_10_IN => stat_10_in, - STAT_11_IN => stat_11_in, - STAT_12_IN => stat_12_in, - STAT_13_IN => stat_13_in, - STAT_14_IN => stat_14_in, - STAT_15_IN => stat_15_in, - -- Status lines - STAT => open - ); +generic map( + RESET_VALUE => x"0001" +) +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(8*16+3 downto 8*16), + SLV_READ_IN => slv_read(8), + SLV_WRITE_IN => slv_write(8), + SLV_ACK_OUT => slv_ack(8), + SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32), + SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32), + -- I/O to the backend + BACKPLANE_IN => backplane_in, + CTRL_0_OUT => ctrl_0_out, + CTRL_1_OUT => ctrl_1_out, + CTRL_2_OUT => ctrl_2_out, + CTRL_3_OUT => ctrl_3_out, + CTRL_4_OUT => ctrl_4_out, + CTRL_5_OUT => ctrl_5_out, + CTRL_6_OUT => ctrl_6_out, + CTRL_7_OUT => ctrl_7_out, + CTRL_8_OUT => ctrl_8_out, + CTRL_9_OUT => ctrl_9_out, + CTRL_10_OUT => ctrl_10_out, + CTRL_11_OUT => ctrl_11_out, + CTRL_12_OUT => ctrl_12_out, + CTRL_13_OUT => ctrl_13_out, + CTRL_14_OUT => ctrl_14_out, + CTRL_15_OUT => ctrl_15_out, + STAT_0_IN => stat_0_in, + STAT_1_IN => stat_1_in, + STAT_2_IN => stat_2_in, + STAT_3_IN => stat_3_in, + STAT_4_IN => stat_4_in, + STAT_5_IN => stat_5_in, + STAT_6_IN => stat_6_in, + STAT_7_IN => stat_7_in, + STAT_8_IN => stat_8_in, + STAT_9_IN => stat_9_in, + STAT_10_IN => stat_10_in, + STAT_11_IN => stat_11_in, + STAT_12_IN => stat_12_in, + STAT_13_IN => stat_13_in, + STAT_14_IN => stat_14_in, + STAT_15_IN => stat_15_in, + -- Status lines + STAT => open +); slv_busy(8) <= '0'; ------------------------------------------------------------------------------------ -- ADC level register ------------------------------------------------------------------------------------ THE_ADC_LVL_REG: slv_register -generic map( RESET_VALUE => x"d0_20_78_88" ) -port map( CLK_IN => clk_in, - RESET_IN => reset_in, -- general reset - BUSY_IN => '0', - -- Slave bus - SLV_READ_IN => slv_read(9), - SLV_WRITE_IN => slv_write(9), - SLV_BUSY_OUT => slv_busy(9), - SLV_ACK_OUT => slv_ack(9), - SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32), - SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32), - -- I/O to the backend - REG_DATA_IN => ctrl_lvl, - REG_DATA_OUT => ctrl_lvl, - -- Status lines - STAT => open - ); +generic map( + RESET_VALUE => x"d0_20_78_88" +) +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, -- general reset + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => slv_read(9), + SLV_WRITE_IN => slv_write(9), + SLV_BUSY_OUT => slv_busy(9), + SLV_ACK_OUT => slv_ack(9), + SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32), + SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32), + -- I/O to the backend + REG_DATA_IN => ctrl_lvl, + REG_DATA_OUT => ctrl_lvl, + -- Status lines + STAT => open +); ------------------------------------------------------------------------------------ -- trigger control register ------------------------------------------------------------------------------------ THE_TRG_CTRL_REG: slv_register -generic map( RESET_VALUE => x"10_10_10_10" ) -port map( CLK_IN => clk_in, - RESET_IN => reset_in, -- general reset - BUSY_IN => '0', - -- Slave bus - SLV_READ_IN => slv_read(10), - SLV_WRITE_IN => slv_write(10), - SLV_BUSY_OUT => slv_busy(10), - SLV_ACK_OUT => slv_ack(10), - SLV_DATA_IN => slv_data_wr(10*32+31 downto 10*32), - SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32), - -- I/O to the backend - REG_DATA_IN => ctrl_trg, - REG_DATA_OUT => ctrl_trg, - -- Status lines - STAT => open - ); +generic map( + RESET_VALUE => x"10_10_10_10" +) +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, -- general reset + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => slv_read(10), + SLV_WRITE_IN => slv_write(10), + SLV_BUSY_OUT => slv_busy(10), + SLV_ACK_OUT => slv_ack(10), + SLV_DATA_IN => slv_data_wr(10*32+31 downto 10*32), + SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32), + -- I/O to the backend + REG_DATA_IN => ctrl_trg, + REG_DATA_OUT => ctrl_trg, + -- Status lines + STAT => open +); ------------------------------------------------------------------------------------ -- PLL control register ------------------------------------------------------------------------------------ THE_PLL_CTRL_REG: slv_half_register -generic map( RESET_VALUE => x"00_02" ) -port map( CLK_IN => clk_in, - RESET_IN => reset_in, -- general reset - -- Slave bus - SLV_READ_IN => slv_read(11), - SLV_WRITE_IN => slv_write(11), - SLV_ACK_OUT => slv_ack(11), - SLV_DATA_IN => slv_data_wr(11*32+31 downto 11*32), - SLV_DATA_OUT => slv_data_rd(11*32+31 downto 11*32), - -- I/O to the backend - STATUS_REG_IN => status_pll_in, - CTRL_REG_OUT => ctrl_pll, - -- Status lines - STAT => open - ); +generic map( + RESET_VALUE => x"00_02" +) +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, -- general reset + -- Slave bus + SLV_READ_IN => slv_read(11), + SLV_WRITE_IN => slv_write(11), + SLV_ACK_OUT => slv_ack(11), + SLV_DATA_IN => slv_data_wr(11*32+31 downto 11*32), + SLV_DATA_OUT => slv_data_rd(11*32+31 downto 11*32), + -- I/O to the backend + STATUS_REG_IN => status_pll_in, + CTRL_REG_OUT => ctrl_pll, + -- Status lines + STAT => open +); slv_busy(11) <= '0'; ------------------------------------------------------------------------------------ -- ADC0 snooper ------------------------------------------------------------------------------------ THE_ADC0_SNOOPER: slv_adc_snoop -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- Slave bus - SLV_ADDR_IN => slv_addr(12*16+9 downto 12*16), - SLV_READ_IN => slv_read(12), - SLV_WRITE_IN => slv_write(12), - SLV_ACK_OUT => slv_ack(12), - SLV_DATA_IN => slv_data_wr(12*32+31 downto 12*32), - SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32), - -- I/O to the backend - ADC_SEL_OUT => adc0_sel_out, - ADC_CLK_IN => adc0_clk_in, - ADC_DATA_IN => adc0_data_in, - -- Status lines - STAT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(12*16+9 downto 12*16), + SLV_READ_IN => slv_read(12), + SLV_WRITE_IN => slv_write(12), + SLV_ACK_OUT => slv_ack(12), + SLV_DATA_IN => slv_data_wr(12*32+31 downto 12*32), + SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32), + -- I/O to the backend + ADC_SEL_OUT => adc0_sel_out, + ADC_CLK_IN => adc0_clk_in, + ADC_DATA_IN => adc0_data_in, + -- Status lines + STAT => open +); slv_busy(12) <= '0'; @@ -752,46 +780,50 @@ slv_busy(12) <= '0'; -- ADC1 snooper ------------------------------------------------------------------------------------ THE_ADC1_SNOOPER: slv_adc_snoop -port map( CLK_IN => clk_in, - RESET_IN => reset_in, - -- Slave bus - SLV_ADDR_IN => slv_addr(13*16+9 downto 13*16), - SLV_READ_IN => slv_read(13), - SLV_WRITE_IN => slv_write(13), - SLV_ACK_OUT => slv_ack(13), - SLV_DATA_IN => slv_data_wr(13*32+31 downto 13*32), - SLV_DATA_OUT => slv_data_rd(13*32+31 downto 13*32), - -- I/O to the backend - ADC_SEL_OUT => adc1_sel_out, - ADC_CLK_IN => adc1_clk_in, - ADC_DATA_IN => adc1_data_in, - -- Status lines - STAT => open - ); +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, + -- Slave bus + SLV_ADDR_IN => slv_addr(13*16+9 downto 13*16), + SLV_READ_IN => slv_read(13), + SLV_WRITE_IN => slv_write(13), + SLV_ACK_OUT => slv_ack(13), + SLV_DATA_IN => slv_data_wr(13*32+31 downto 13*32), + SLV_DATA_OUT => slv_data_rd(13*32+31 downto 13*32), + -- I/O to the backend + ADC_SEL_OUT => adc1_sel_out, + ADC_CLK_IN => adc1_clk_in, + ADC_DATA_IN => adc1_data_in, + -- Status lines + STAT => open +); slv_busy(13) <= '0'; - + ------------------------------------------------------------------------------------ -- test register (normal) ------------------------------------------------------------------------------------ THE_GOOD_TEST_REG: slv_register -generic map( RESET_VALUE => x"dead_beef" ) -port map( CLK_IN => clk_in, - RESET_IN => reset_in, -- general reset - BUSY_IN => '0', - -- Slave bus - SLV_READ_IN => slv_read(14), - SLV_WRITE_IN => slv_write(14), - SLV_BUSY_OUT => slv_busy(14), - SLV_ACK_OUT => slv_ack(14), - SLV_DATA_IN => slv_data_wr(14*32+31 downto 14*32), - SLV_DATA_OUT => slv_data_rd(14*32+31 downto 14*32), - -- I/O to the backend - REG_DATA_IN => test_reg_in, --x"5a3c_87e1", - REG_DATA_OUT => test_reg_out, - -- Status lines - STAT => open - ); +generic map( + RESET_VALUE => x"dead_beef" +) +port map( + CLK_IN => clk_in, + RESET_IN => reset_in, -- general reset + BUSY_IN => '0', + -- Slave bus + SLV_READ_IN => slv_read(14), + SLV_WRITE_IN => slv_write(14), + SLV_BUSY_OUT => slv_busy(14), + SLV_ACK_OUT => slv_ack(14), + SLV_DATA_IN => slv_data_wr(14*32+31 downto 14*32), + SLV_DATA_OUT => slv_data_rd(14*32+31 downto 14*32), + -- I/O to the backend + REG_DATA_IN => test_reg_in, --x"5a3c_87e1", + REG_DATA_OUT => test_reg_out, + -- Status lines + STAT => open +); diff --git a/src/slv_adc_la.vhd b/src/slv_adc_la.vhd index ba109d2..67fc84c 100644 --- a/src/slv_adc_la.vhd +++ b/src/slv_adc_la.vhd @@ -8,62 +8,62 @@ use work.adcmv3_components.all; entity slv_adc_la is -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(9 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from - ADC_CLK_IN : in std_logic; -- ADC reconstructed clock - ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(9 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from + ADC_CLK_IN : in std_logic; -- ADC reconstructed clock + ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); end entity; architecture Behavioral of slv_adc_la is -- Signals +type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- slave bus signals +signal slv_ack_x : std_logic; +signal slv_ack : std_logic; +signal store_wr_x : std_logic; +signal store_wr : std_logic; +signal store_rd_x : std_logic; +signal store_rd : std_logic; + +signal arm_x : std_logic; +signal trg_x : std_logic; + +signal ctrl_reg : std_logic_vector(15 downto 0); +signal status_reg : std_logic_vector(31 downto 0); + +signal rd_data : std_logic_vector(15 downto 0); + +-- 40MHz clock domain!!! +signal wr_data : std_logic_vector(15 downto 0); +signal wr_addr : std_logic_vector(9 downto 0); +signal wr_we : std_logic; +signal reset_40mhz : std_logic; +signal arm_40mhz : std_logic; +signal trg_40mhz : std_logic; + +signal sm_clear : std_logic; +signal sm_run : std_logic; +signal sm_sample : std_logic; +signal sm_ready : std_logic; +signal sm_last : std_logic; +signal sm_bsm : std_logic_vector(3 downto 0); - type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - -- slave bus signals - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; - - signal arm_x : std_logic; - signal trg_x : std_logic; - - signal ctrl_reg : std_logic_vector(15 downto 0); - signal status_reg : std_logic_vector(31 downto 0); - - signal rd_data : std_logic_vector(15 downto 0); - - -- 40MHz clock domain!!! - signal wr_data : std_logic_vector(15 downto 0); - signal wr_addr : std_logic_vector(9 downto 0); - signal wr_we : std_logic; - signal reset_40mhz : std_logic; - signal arm_40mhz : std_logic; - signal trg_40mhz : std_logic; - - signal sm_clear : std_logic; - signal sm_run : std_logic; - signal sm_sample : std_logic; - signal sm_ready : std_logic; - signal sm_last : std_logic; - signal sm_bsm : std_logic_vector(3 downto 0); - begin -- Fake @@ -105,38 +105,38 @@ begin store_wr_x <= '0'; store_rd_x <= '0'; case CURRENT_STATE is - when SLEEP => if ( slv_read_in = '1' ) then + when SLEEP => if ( slv_read_in = '1' ) then NEXT_STATE <= RD_DEL0; store_rd_x <= '1'; elsif( slv_write_in = '1' ) then NEXT_STATE <= WR_DEL0; store_wr_x <= '1'; - else + else NEXT_STATE <= SLEEP; end if; - when RD_DEL0 => NEXT_STATE <= RD_DEL1; - when RD_DEL1 => NEXT_STATE <= RD_RDY; - when RD_RDY => NEXT_STATE <= RD_ACK; - when RD_ACK => if( slv_read_in = '0' ) then + when RD_DEL0 => NEXT_STATE <= RD_DEL1; + when RD_DEL1 => NEXT_STATE <= RD_RDY; + when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_ACK => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; slv_ack_x <= '1'; else NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; end if; - when WR_DEL0 => NEXT_STATE <= WR_DEL1; - when WR_DEL1 => NEXT_STATE <= WR_RDY; - when WR_RDY => NEXT_STATE <= WR_ACK; - when WR_ACK => if( slv_write_in = '0' ) then + when WR_DEL0 => NEXT_STATE <= WR_DEL1; + when WR_DEL1 => NEXT_STATE <= WR_RDY; + when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_ACK => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; slv_ack_x <= '1'; else NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; @@ -145,54 +145,58 @@ end process TRANSFORM; --------------------------------------------------------- THE_RST_SYNC: state_sync -port map( STATE_A_IN => reset_in, - CLK_B_IN => adc_clk_in, - RESET_B_IN => '0', - STATE_B_OUT => reset_40mhz - ); +port map( + STATE_A_IN => reset_in, + CLK_B_IN => adc_clk_in, + RESET_B_IN => '0', + STATE_B_OUT => reset_40mhz +); arm_x <= slv_data_in(30) and store_wr; THE_ARM_PULSE_SYNC: pulse_sync -port map( CLK_A_IN => clk_in, - RESET_A_IN => reset_in, - PULSE_A_IN => arm_x, - CLK_B_IN => adc_clk_in, - RESET_B_IN => reset_40mhz, - PULSE_B_OUT => arm_40mhz - ); +port map( + CLK_A_IN => clk_in, + RESET_A_IN => reset_in, + PULSE_A_IN => arm_x, + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset_40mhz, + PULSE_B_OUT => arm_40mhz +); trg_x <= slv_data_in(31) and store_wr; THE_TRG_PULSE_SYNC: pulse_sync -port map( CLK_A_IN => clk_in, - RESET_A_IN => reset_in, - PULSE_A_IN => trg_x, - CLK_B_IN => adc_clk_in, - RESET_B_IN => reset_40mhz, - PULSE_B_OUT => trg_40mhz - ); +port map( + CLK_A_IN => clk_in, + RESET_A_IN => reset_in, + PULSE_A_IN => trg_x, + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset_40mhz, + PULSE_B_OUT => trg_40mhz +); THE_LOGIC_ANALYZER: logic_analyzer -port map( CLK_IN => adc_clk_in, - RESET_IN => reset_40mhz, - -- control signals - ARM_IN => arm_40mhz, -- BUGBUGBUG - TRG_IN => trg_40mhz, -- BUGBUGBUG - MAX_SAMPLE_IN => ctrl_reg(9 downto 0), - -- status signals - SM_ADDR_OUT => wr_addr, - SM_CE_OUT => open, - SM_WE_OUT => wr_we, - CLEAR_OUT => sm_clear, - RUN_OUT => sm_run, - SAMPLE_OUT => sm_sample, - READY_OUT => sm_ready, - LAST_OUT => sm_last, - -- Status lines - BSM_OUT => sm_bsm, - STAT => open - ); +port map( + CLK_IN => adc_clk_in, + RESET_IN => reset_40mhz, + -- control signals + ARM_IN => arm_40mhz, -- BUGBUGBUG + TRG_IN => trg_40mhz, -- BUGBUGBUG + MAX_SAMPLE_IN => ctrl_reg(9 downto 0), + -- status signals + SM_ADDR_OUT => wr_addr, + SM_CE_OUT => open, + SM_WE_OUT => wr_we, + CLEAR_OUT => sm_clear, + RUN_OUT => sm_run, + SAMPLE_OUT => sm_sample, + READY_OUT => sm_ready, + LAST_OUT => sm_last, + -- Status lines + BSM_OUT => sm_bsm, + STAT => open +); wr_data(15) <= sm_clear; wr_data(14) <= sm_run; @@ -201,17 +205,18 @@ wr_data(12) <= sm_last; wr_data(11 downto 0) <= adc_data_in; THE_ADC0_SNOOP_MEM: adc_snoop_mem -port map( WRADDRESS => wr_addr, - DATA => wr_data, - WE => wr_we, - WRCLOCK => adc_clk_in, - WRCLOCKEN => '1', - RDADDRESS => slv_addr_in, - RDCLOCK => clk_in, - RDCLOCKEN => '1', - RESET => reset_in, - Q => rd_data - ); +port map( + WRADDRESS => wr_addr, + DATA => wr_data, + WE => wr_we, + WRCLOCK => adc_clk_in, + WRCLOCKEN => '1', + RDADDRESS => slv_addr_in, + RDCLOCK => clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + Q => rd_data +); -- register write THE_WRITE_REG_PROC: process( clk_in ) diff --git a/src/slv_adc_snoop.vhd b/src/slv_adc_snoop.vhd index d130d70..0543e15 100644 --- a/src/slv_adc_snoop.vhd +++ b/src/slv_adc_snoop.vhd @@ -8,50 +8,50 @@ use work.adcmv3_components.all; entity slv_adc_snoop is -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(9 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from - ADC_CLK_IN : in std_logic; -- ADC reconstructed clock - ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(9 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + ADC_SEL_OUT : out std_logic_vector(2 downto 0); -- selects the ADC channel to snoop from + ADC_CLK_IN : in std_logic; -- ADC reconstructed clock + ADC_DATA_IN : in std_logic_vector(11 downto 0); -- ADC selected channel data + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); end entity; architecture Behavioral of slv_adc_snoop is -- Signals +type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; - type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; +-- slave bus signals +signal slv_ack_x : std_logic; +signal slv_ack : std_logic; +signal store_wr_x : std_logic; +signal store_wr : std_logic; +signal store_rd_x : std_logic; +signal store_rd : std_logic; - -- slave bus signals - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; +signal ctrl_reg : std_logic_vector(15 downto 0); +signal status_reg : std_logic_vector(31 downto 0); - signal ctrl_reg : std_logic_vector(15 downto 0); - signal status_reg : std_logic_vector(31 downto 0); +signal rd_data : std_logic_vector(15 downto 0); - signal rd_data : std_logic_vector(15 downto 0); - - -- 40MHz clock domain!!! - signal wr_data : std_logic_vector(15 downto 0); - signal wr_ctr : std_logic_vector(9 downto 0); - signal rst_wr_ctr : std_logic; - signal ce_wr_ctr : std_logic; - signal reset : std_logic; +-- 40MHz clock domain!!! +signal wr_data : std_logic_vector(15 downto 0); +signal wr_ctr : std_logic_vector(9 downto 0); +signal rst_wr_ctr : std_logic; +signal ce_wr_ctr : std_logic; +signal reset : std_logic; begin @@ -60,7 +60,7 @@ stat(31 downto 18) <= (others => '0'); stat(17) <= rst_wr_ctr; stat(16) <= ce_wr_ctr; stat(15 downto 0) <= ctrl_reg; - + --------------------------------------------------------- -- Statemachine -- --------------------------------------------------------- @@ -90,38 +90,38 @@ begin store_wr_x <= '0'; store_rd_x <= '0'; case CURRENT_STATE is - when SLEEP => if ( slv_read_in = '1' ) then + when SLEEP => if ( slv_read_in = '1' ) then NEXT_STATE <= RD_DEL0; store_rd_x <= '1'; elsif( slv_write_in = '1' ) then NEXT_STATE <= WR_DEL0; store_wr_x <= '1'; - else + else NEXT_STATE <= SLEEP; end if; - when RD_DEL0 => NEXT_STATE <= RD_DEL1; - when RD_DEL1 => NEXT_STATE <= RD_RDY; - when RD_RDY => NEXT_STATE <= RD_ACK; - when RD_ACK => if( slv_read_in = '0' ) then + when RD_DEL0 => NEXT_STATE <= RD_DEL1; + when RD_DEL1 => NEXT_STATE <= RD_RDY; + when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_ACK => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; slv_ack_x <= '1'; else NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; end if; - when WR_DEL0 => NEXT_STATE <= WR_DEL1; - when WR_DEL1 => NEXT_STATE <= WR_RDY; - when WR_RDY => NEXT_STATE <= WR_ACK; - when WR_ACK => if( slv_write_in = '0' ) then + when WR_DEL0 => NEXT_STATE <= WR_DEL1; + when WR_DEL1 => NEXT_STATE <= WR_RDY; + when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_ACK => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; slv_ack_x <= '1'; else NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; @@ -130,25 +130,28 @@ end process TRANSFORM; --------------------------------------------------------- THE_RESET_SYNC: state_sync -port map( STATE_A_IN => reset_in, - CLK_B_IN => adc_clk_in, - RESET_B_IN => '0', - STATE_B_OUT => reset - ); +port map( + STATE_A_IN => reset_in, + CLK_B_IN => adc_clk_in, + RESET_B_IN => '0', + STATE_B_OUT => reset +); THE_RST_SYNC: state_sync -port map( STATE_A_IN => ctrl_reg(15), - CLK_B_IN => adc_clk_in, - RESET_B_IN => reset, - STATE_B_OUT => rst_wr_ctr - ); +port map( + STATE_A_IN => ctrl_reg(15), + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset, + STATE_B_OUT => rst_wr_ctr +); THE_CE_SYNC: state_sync -port map( STATE_A_IN => ctrl_reg(14), - CLK_B_IN => adc_clk_in, - RESET_B_IN => reset, - STATE_B_OUT => ce_wr_ctr - ); +port map( + STATE_A_IN => ctrl_reg(14), + CLK_B_IN => adc_clk_in, + RESET_B_IN => reset, + STATE_B_OUT => ce_wr_ctr +); THE_WR_CTR_PROC: process( adc_clk_in ) begin @@ -164,17 +167,18 @@ end process THE_WR_CTR_PROC; wr_data <= x"0" & adc_data_in; THE_ADC0_SNOOP_MEM: adc_snoop_mem -port map( WRADDRESS => wr_ctr, - DATA => wr_data, - WE => ce_wr_ctr, - WRCLOCK => adc_clk_in, - WRCLOCKEN => '1', - RDADDRESS => slv_addr_in, - RDCLOCK => clk_in, - RDCLOCKEN => '1', - RESET => reset_in, - Q => rd_data - ); +port map( + WRADDRESS => wr_ctr, + DATA => wr_data, + WE => ce_wr_ctr, + WRCLOCK => adc_clk_in, + WRCLOCKEN => '1', + RDADDRESS => slv_addr_in, + RDCLOCK => clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + Q => rd_data +); -- register write THE_WRITE_REG_PROC: process( clk_in ) diff --git a/src/slv_half_register.vhd b/src/slv_half_register.vhd index a4a1723..d035292 100644 --- a/src/slv_half_register.vhd +++ b/src/slv_half_register.vhd @@ -8,41 +8,43 @@ use work.adcmv3_components.all; entity slv_half_register is -generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" ); -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - STATUS_REG_IN : in std_logic_vector(15 downto 0); - CTRL_REG_OUT : out std_logic_vector(15 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); +generic( + RESET_VALUE : std_logic_vector(15 downto 0) := x"0000" +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + STATUS_REG_IN : in std_logic_vector(15 downto 0); + CTRL_REG_OUT : out std_logic_vector(15 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); end entity; architecture Behavioral of slv_half_register is -- Signals +type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; - type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; +-- slave bus signals +signal slv_ack_x : std_logic; +signal slv_ack : std_logic; +signal store_wr_x : std_logic; +signal store_wr : std_logic; +signal store_rd_x : std_logic; +signal store_rd : std_logic; - -- slave bus signals - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; +signal ctrl_reg : std_logic_vector(15 downto 0); - signal ctrl_reg : std_logic_vector(15 downto 0); - - signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data +signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data begin @@ -78,34 +80,34 @@ begin store_wr_x <= '0'; store_rd_x <= '0'; case CURRENT_STATE is - when SLEEP => if ( slv_read_in = '1' ) then + when SLEEP => if ( slv_read_in = '1' ) then NEXT_STATE <= RD_RDY; store_rd_x <= '1'; elsif( slv_write_in = '1' ) then NEXT_STATE <= WR_RDY; store_wr_x <= '1'; - else + else NEXT_STATE <= SLEEP; end if; - when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_RDY => NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; - when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_RDY => NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; - when RD_ACK => if( slv_read_in = '0' ) then + when RD_ACK => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; end if; - when WR_ACK => if( slv_write_in = '0' ) then + when WR_ACK => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; diff --git a/src/slv_onewire_memory.vhd b/src/slv_onewire_memory.vhd index 2c23121..48ad04f 100644 --- a/src/slv_onewire_memory.vhd +++ b/src/slv_onewire_memory.vhd @@ -7,57 +7,57 @@ library work; use work.adcmv3_components.all; entity slv_onewire_memory is -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(5 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- backplane identifier - BACKPLANE_IN : in std_logic_vector(2 downto 0); - -- 1Wire lines - ONEWIRE_START_IN : in std_logic; - ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); - BP_ONEWIRE_INOUT : inout std_logic; - -- Status lines - STAT : out std_logic_vector(63 downto 0) -- DEBUG - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(5 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- backplane identifier + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- 1Wire lines + ONEWIRE_START_IN : in std_logic; + ONEWIRE_INOUT : inout std_logic_vector(15 downto 0); + BP_ONEWIRE_INOUT : inout std_logic; + -- Status lines + STAT : out std_logic_vector(63 downto 0) -- DEBUG +); end entity; architecture Behavioral of slv_onewire_memory is -- Signals - type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - -- slave bus signals - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal slv_busy : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; - - -- for replacing the lost FE with BP data - signal wr_addr_q : std_logic_vector(6 downto 0); -- some bits are masked - signal wr_data_q : std_logic_vector(15 downto 0); - signal wr_we_q : std_logic; - - signal wr_addr : std_logic_vector(6 downto 0); -- some bits are masked - signal wr_bp_data : std_logic_vector(15 downto 0); - signal wr_data : std_logic_vector(15 downto 0); - signal wr_we : std_logic; - signal buf_slv_data_out : std_logic_vector(31 downto 0); - - signal read_address : std_logic_vector(5 downto 0); - signal missing_one : std_logic_vector(3 downto 0); -- missing APV FE <-> backplane - signal overlay : std_logic; - - signal onewire_bsm : std_logic_vector(7 downto 0); +type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- slave bus signals +signal slv_ack_x : std_logic; +signal slv_ack : std_logic; +signal slv_busy : std_logic; +signal store_wr_x : std_logic; +signal store_wr : std_logic; +signal store_rd_x : std_logic; +signal store_rd : std_logic; + +-- for replacing the lost FE with BP data +signal wr_addr_q : std_logic_vector(6 downto 0); -- some bits are masked +signal wr_data_q : std_logic_vector(15 downto 0); +signal wr_we_q : std_logic; +signal wr_addr : std_logic_vector(6 downto 0); -- some bits are masked +signal wr_bp_data : std_logic_vector(15 downto 0); +signal wr_data : std_logic_vector(15 downto 0); +signal wr_we : std_logic; +signal buf_slv_data_out : std_logic_vector(31 downto 0); + +signal read_address : std_logic_vector(5 downto 0); +signal missing_one : std_logic_vector(3 downto 0); -- missing APV FE <-> backplane +signal overlay : std_logic; + +signal onewire_bsm : std_logic_vector(7 downto 0); begin @@ -79,23 +79,24 @@ stat(3 downto 0) <= onewire_bsm(3 downto 0); -- Remap the 1Wire chips to Luigi's world THE_ADC_ONEWIRE_MAP_MEM: adc_onewire_map_mem -port map( ADDRESS(6 downto 4) => backplane_in, - ADDRESS(3 downto 0) => slv_addr_in(5 downto 2), - Q => read_address(5 downto 2) - ); +port map( + ADDRESS(6 downto 4) => backplane_in, + ADDRESS(3 downto 0) => slv_addr_in(5 downto 2), + Q => read_address(5 downto 2) +); read_address(1 downto 0) <= slv_addr_in(1 downto 0); --- One APV FE connector is missing ("Roman's FE"), and replace the +-- One APV FE connector is missing ("Roman's FE"), and replace the -- 1Wire ID by the backplane THE_ONEWIRE_SPARE_ONE: onewire_spare_one -port map( ADDRESS => backplane_in, - Q => missing_one - ); +port map( + ADDRESS => backplane_in, + Q => missing_one +); -- Check if we need to replace data overlay <= '1' when (wr_addr(6 downto 3) = missing_one) else '0'; - --------------------------------------------------------- -- Statemachine -- --------------------------------------------------------- @@ -125,34 +126,34 @@ begin store_wr_x <= '0'; store_rd_x <= '0'; case CURRENT_STATE is - when SLEEP => if ( (slv_read_in = '1') ) then + when SLEEP => if ( (slv_read_in = '1') ) then NEXT_STATE <= RD_RDY; store_rd_x <= '1'; elsif( (slv_write_in = '1') ) then NEXT_STATE <= WR_RDY; store_wr_x <= '1'; - else + else NEXT_STATE <= SLEEP; end if; - when RD_RDY => NEXT_STATE <= RD_ACK; - when WR_RDY => NEXT_STATE <= WR_ACK; - when RD_ACK => if( slv_read_in = '0' ) then + when RD_RDY => NEXT_STATE <= RD_ACK; + when WR_RDY => NEXT_STATE <= WR_ACK; + when RD_ACK => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; slv_ack_x <= '1'; else NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; end if; - when WR_ACK => if( slv_write_in = '0' ) then + when WR_ACK => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; slv_ack_x <= '1'; else NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; @@ -161,23 +162,24 @@ end process TRANSFORM; -- 1 Wire master -- --------------------------------------------------------- THE_ONEWIRE_MASTER: onewire_master -generic map( CLK_PERIOD => 10 ) -port map( CLK => clk_in, - RESET => reset_in, - READOUT_ENABLE_IN => store_wr, - -- connection to 1-wire interface (16 APV FEs) - ONEWIRE => onewire_inout, - BP_ONEWIRE => bp_onewire_inout, - -- connection to external DPRAM for slow control readout - BP_DATA_OUT => wr_bp_data, - DATA_OUT => wr_data, - ADDR_OUT => wr_addr, - WRITE_OUT => wr_we, - BUSY_OUT => slv_busy, -- could be used... - -- debug - BSM_OUT => onewire_bsm, - STAT => open - ); +generic map( CLK_PERIOD => 10 ) +port map( + CLK => clk_in, + RESET => reset_in, + READOUT_ENABLE_IN => store_wr, + -- connection to 1-wire interface (16 APV FEs) + ONEWIRE => onewire_inout, + BP_ONEWIRE => bp_onewire_inout, + -- connection to external DPRAM for slow control readout + BP_DATA_OUT => wr_bp_data, + DATA_OUT => wr_data, + ADDR_OUT => wr_addr, + WRITE_OUT => wr_we, + BUSY_OUT => slv_busy, -- could be used... + -- debug + BSM_OUT => onewire_bsm, + STAT => open +); --------------------------------------------------------- -- data replacing -- @@ -199,17 +201,18 @@ end process THE_DATA_REPLACE_PROC; -- data handling -- --------------------------------------------------------- THE_SLV_ONEWIRE_DPRAM: slv_onewire_dpram -port map( WRADDRESS => wr_addr_q, - RDADDRESS => read_address, - DATA => wr_data_q, - WE => wr_we_q, - RDCLOCK => clk_in, - RDCLOCKEN => '1', - RESET => reset_in, - WRCLOCK => clk_in, - WRCLOCKEN => '1', - Q => buf_slv_data_out - ); +port map( + WRADDRESS => wr_addr_q, + RDADDRESS => read_address, + DATA => wr_data_q, + WE => wr_we_q, + RDCLOCK => clk_in, + RDCLOCKEN => '1', + RESET => reset_in, + WRCLOCK => clk_in, + WRCLOCKEN => '1', + Q => buf_slv_data_out +); diff --git a/src/slv_ped_thr_mem.vhd b/src/slv_ped_thr_mem.vhd index 12c2e3c..a6b2866 100644 --- a/src/slv_ped_thr_mem.vhd +++ b/src/slv_ped_thr_mem.vhd @@ -7,115 +7,117 @@ library work; use work.adcmv3_components.all; entity slv_ped_thr_mem is -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(10 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- backplane identifier - BACKPLANE_IN : in std_logic_vector(2 downto 0); - -- I/O to the backend - MEM_CLK_IN : in std_logic; - MEM_ADDR_IN : in std_logic_vector(6 downto 0); - MEM_0_D_OUT : out std_logic_vector(17 downto 0); - MEM_1_D_OUT : out std_logic_vector(17 downto 0); - MEM_2_D_OUT : out std_logic_vector(17 downto 0); - MEM_3_D_OUT : out std_logic_vector(17 downto 0); - MEM_4_D_OUT : out std_logic_vector(17 downto 0); - MEM_5_D_OUT : out std_logic_vector(17 downto 0); - MEM_6_D_OUT : out std_logic_vector(17 downto 0); - MEM_7_D_OUT : out std_logic_vector(17 downto 0); - MEM_8_D_OUT : out std_logic_vector(17 downto 0); - MEM_9_D_OUT : out std_logic_vector(17 downto 0); - MEM_10_D_OUT : out std_logic_vector(17 downto 0); - MEM_11_D_OUT : out std_logic_vector(17 downto 0); - MEM_12_D_OUT : out std_logic_vector(17 downto 0); - MEM_13_D_OUT : out std_logic_vector(17 downto 0); - MEM_14_D_OUT : out std_logic_vector(17 downto 0); - MEM_15_D_OUT : out std_logic_vector(17 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(10 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- backplane identifier + BACKPLANE_IN : in std_logic_vector(2 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(6 downto 0); + MEM_0_D_OUT : out std_logic_vector(17 downto 0); + MEM_1_D_OUT : out std_logic_vector(17 downto 0); + MEM_2_D_OUT : out std_logic_vector(17 downto 0); + MEM_3_D_OUT : out std_logic_vector(17 downto 0); + MEM_4_D_OUT : out std_logic_vector(17 downto 0); + MEM_5_D_OUT : out std_logic_vector(17 downto 0); + MEM_6_D_OUT : out std_logic_vector(17 downto 0); + MEM_7_D_OUT : out std_logic_vector(17 downto 0); + MEM_8_D_OUT : out std_logic_vector(17 downto 0); + MEM_9_D_OUT : out std_logic_vector(17 downto 0); + MEM_10_D_OUT : out std_logic_vector(17 downto 0); + MEM_11_D_OUT : out std_logic_vector(17 downto 0); + MEM_12_D_OUT : out std_logic_vector(17 downto 0); + MEM_13_D_OUT : out std_logic_vector(17 downto 0); + MEM_14_D_OUT : out std_logic_vector(17 downto 0); + MEM_15_D_OUT : out std_logic_vector(17 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); end entity; architecture Behavioral of slv_ped_thr_mem is -- Signals - type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; +type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- statemachine signals +signal slv_ack_x : std_logic; +signal slv_ack : std_logic; +signal store_wr_x : std_logic; +signal store_wr : std_logic; +signal store_rd_x : std_logic; +signal store_rd : std_logic; - -- statemachine signals - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; +signal block_addr : std_logic_vector(3 downto 0); - signal block_addr : std_logic_vector(3 downto 0); +type ped_data_t is array (0 to 15) of std_logic_vector(17 downto 0); +signal ped_data : ped_data_t; +signal mem_data : ped_data_t; - type ped_data_t is array (0 to 15) of std_logic_vector(17 downto 0); - signal ped_data : ped_data_t; - signal mem_data : ped_data_t; +signal mem_wr_x : std_logic_vector(15 downto 0); +signal mem_wr : std_logic_vector(15 downto 0); +signal mem_sel : std_logic_vector(15 downto 0); - signal mem_wr_x : std_logic_vector(15 downto 0); - signal mem_wr : std_logic_vector(15 downto 0); - signal mem_sel : std_logic_vector(15 downto 0); +signal rdback_data : std_logic_vector(17 downto 0); - signal rdback_data : std_logic_vector(17 downto 0); - begin --------------------------------------------------------- -- Mapping of backplanes -- --------------------------------------------------------- THE_APV_ADC_MAP_MEM: apv_adc_map_mem -port map( ADDRESS(6 downto 4) => backplane_in, - ADDRESS(3 downto 0) => slv_addr_in(10 downto 7), - Q => block_addr - ); +port map( + ADDRESS(6 downto 4) => backplane_in, + ADDRESS(3 downto 0) => slv_addr_in(10 downto 7), + Q => block_addr +); THE_MEM_SEL_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then case block_addr is - when x"0" => mem_sel <= b"0000_0000_0000_0001"; + when x"0" => mem_sel <= b"0000_0000_0000_0001"; rdback_data <= mem_data(0); - when x"1" => mem_sel <= b"0000_0000_0000_0010"; + when x"1" => mem_sel <= b"0000_0000_0000_0010"; rdback_data <= mem_data(1); - when x"2" => mem_sel <= b"0000_0000_0000_0100"; + when x"2" => mem_sel <= b"0000_0000_0000_0100"; rdback_data <= mem_data(2); - when x"3" => mem_sel <= b"0000_0000_0000_1000"; + when x"3" => mem_sel <= b"0000_0000_0000_1000"; rdback_data <= mem_data(3); - when x"4" => mem_sel <= b"0000_0000_0001_0000"; + when x"4" => mem_sel <= b"0000_0000_0001_0000"; rdback_data <= mem_data(4); - when x"5" => mem_sel <= b"0000_0000_0010_0000"; + when x"5" => mem_sel <= b"0000_0000_0010_0000"; rdback_data <= mem_data(5); - when x"6" => mem_sel <= b"0000_0000_0100_0000"; + when x"6" => mem_sel <= b"0000_0000_0100_0000"; rdback_data <= mem_data(6); - when x"7" => mem_sel <= b"0000_0000_1000_0000"; + when x"7" => mem_sel <= b"0000_0000_1000_0000"; rdback_data <= mem_data(7); - when x"8" => mem_sel <= b"0000_0001_0000_0000"; + when x"8" => mem_sel <= b"0000_0001_0000_0000"; rdback_data <= mem_data(8); - when x"9" => mem_sel <= b"0000_0010_0000_0000"; + when x"9" => mem_sel <= b"0000_0010_0000_0000"; rdback_data <= mem_data(9); - when x"a" => mem_sel <= b"0000_0100_0000_0000"; + when x"a" => mem_sel <= b"0000_0100_0000_0000"; rdback_data <= mem_data(10); - when x"b" => mem_sel <= b"0000_1000_0000_0000"; + when x"b" => mem_sel <= b"0000_1000_0000_0000"; rdback_data <= mem_data(11); - when x"c" => mem_sel <= b"0001_0000_0000_0000"; + when x"c" => mem_sel <= b"0001_0000_0000_0000"; rdback_data <= mem_data(12); - when x"d" => mem_sel <= b"0010_0000_0000_0000"; + when x"d" => mem_sel <= b"0010_0000_0000_0000"; rdback_data <= mem_data(13); - when x"e" => mem_sel <= b"0100_0000_0000_0000"; + when x"e" => mem_sel <= b"0100_0000_0000_0000"; rdback_data <= mem_data(14); - when x"f" => mem_sel <= b"1000_0000_0000_0000"; + when x"f" => mem_sel <= b"1000_0000_0000_0000"; rdback_data <= mem_data(15); - when others => mem_sel <= b"0000_0000_0000_0000"; -- never used + when others => mem_sel <= b"0000_0000_0000_0000"; -- never used rdback_data <= (others => '0'); end case; end if; @@ -150,63 +152,64 @@ begin store_wr_x <= '0'; store_rd_x <= '0'; case CURRENT_STATE is - when SLEEP => if ( slv_read_in = '1' ) then + when SLEEP => if ( slv_read_in = '1' ) then NEXT_STATE <= RD_DEL0; store_rd_x <= '1'; elsif( slv_write_in = '1' ) then NEXT_STATE <= WR_DEL0; store_wr_x <= '1'; - else + else NEXT_STATE <= SLEEP; end if; - when RD_DEL0 => NEXT_STATE <= RD_DEL1; - when RD_DEL1 => NEXT_STATE <= RD_RDY; - when RD_RDY => NEXT_STATE <= RD_ACK; - when RD_ACK => if( slv_read_in = '0' ) then + when RD_DEL0 => NEXT_STATE <= RD_DEL1; + when RD_DEL1 => NEXT_STATE <= RD_RDY; + when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_ACK => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; slv_ack_x <= '1'; else NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; end if; - when WR_DEL0 => NEXT_STATE <= WR_DEL1; - when WR_DEL1 => NEXT_STATE <= WR_RDY; - when WR_RDY => NEXT_STATE <= WR_ACK; - when WR_ACK => if( slv_write_in = '0' ) then + when WR_DEL0 => NEXT_STATE <= WR_DEL1; + when WR_DEL1 => NEXT_STATE <= WR_RDY; + when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_ACK => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; slv_ack_x <= '1'; else NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; --------------------------------------------------------- -- block memories -- --------------------------------------------------------- -GEN_PED_MEM: for i in 0 to 15 generate +GEN_PED_MEM: for i in 0 to 15 generate -- Port A: SLV_BUS -- Port B: state machine - THE_PED_MEM: ped_thr_true - port map( DATAINA => slv_data_in(17 downto 0), - DATAINB => b"00_0000_0000_0000_0000", - ADDRESSA => slv_addr_in(6 downto 0), - ADDRESSB => mem_addr_in, - CLOCKA => clk_in, - CLOCKB => mem_clk_in, - CLOCKENA => '1', - CLOCKENB => '1', - WRA => mem_wr(i), -- BUGBUGBUG - WRB => '0', -- state machine never writes! - RESETA => reset_in, - RESETB => reset_in, - QA => mem_data(i), - QB => ped_data(i) - ); + THE_PED_MEM: ped_thr_true + port map( + DATAINA => slv_data_in(17 downto 0), + DATAINB => b"00_0000_0000_0000_0000", + ADDRESSA => slv_addr_in(6 downto 0), + ADDRESSB => mem_addr_in, + CLOCKA => clk_in, + CLOCKB => mem_clk_in, + CLOCKENA => '1', + CLOCKENB => '1', + WRA => mem_wr(i), -- BUGBUGBUG + WRB => '0', -- state machine never writes! + RESETA => reset_in, + RESETB => reset_in, + QA => mem_data(i), + QB => ped_data(i) + ); -- Write signals mem_wr_x(i) <= '1' when ( (mem_sel(i) = '1') and (store_wr = '1') ) else '0'; end generate GEN_PED_MEM; diff --git a/src/slv_register.vhd b/src/slv_register.vhd index f851ca7..00ba296 100644 --- a/src/slv_register.vhd +++ b/src/slv_register.vhd @@ -8,45 +8,47 @@ use work.adcmv3_components.all; entity slv_register is -generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" ); -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - BUSY_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - REG_DATA_IN : in std_logic_vector(31 downto 0); - REG_DATA_OUT : out std_logic_vector(31 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); +generic( + RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + REG_DATA_IN : in std_logic_vector(31 downto 0); + REG_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); end entity; architecture Behavioral of slv_register is -- Signals - - type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - -- slave bus signals - signal slv_busy_x : std_logic; - signal slv_busy : std_logic; - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; - - signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input - signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data - signal reg_busy : std_logic; +type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- slave bus signals +signal slv_busy_x : std_logic; +signal slv_busy : std_logic; +signal slv_ack_x : std_logic; +signal slv_ack : std_logic; +signal store_wr_x : std_logic; +signal store_wr : std_logic; +signal store_rd_x : std_logic; +signal store_rd : std_logic; + +signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input +signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data +signal reg_busy : std_logic; begin @@ -86,7 +88,7 @@ begin store_wr_x <= '0'; store_rd_x <= '0'; case CURRENT_STATE is - when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then + when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then NEXT_STATE <= RD_RDY; store_rd_x <= '1'; elsif( (reg_busy = '0') and (slv_write_in = '1') ) then @@ -98,40 +100,40 @@ begin elsif( (reg_busy = '1') and (slv_write_in = '1') ) then NEXT_STATE <= WR_BSY; slv_busy_x <= '1'; -- added 23022009 - else + else NEXT_STATE <= SLEEP; end if; - when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_RDY => NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; - when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_RDY => NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; - when RD_ACK => if( slv_read_in = '0' ) then + when RD_ACK => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; end if; - when WR_ACK => if( slv_write_in = '0' ) then + when WR_ACK => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; end if; - when RD_BSY => if( slv_read_in = '0' ) then + when RD_BSY => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= RD_BSY; slv_busy_x <= '1'; end if; - when WR_BSY => if( slv_write_in = '0' ) then + when WR_BSY => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= WR_BSY; slv_busy_x <= '1'; end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; diff --git a/src/slv_register_bank.vhd b/src/slv_register_bank.vhd index 5baa67d..f22805f 100644 --- a/src/slv_register_bank.vhd +++ b/src/slv_register_bank.vhd @@ -7,78 +7,81 @@ library work; use work.adcmv3_components.all; entity slv_register_bank is -generic( RESET_VALUE : std_logic_vector(15 downto 0) := x"0001" ); -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(3 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- I/O to the backend - BACKPLANE_IN : in std_logic_vector(2 downto 0); - CTRL_0_OUT : out std_logic_vector(15 downto 0); - CTRL_1_OUT : out std_logic_vector(15 downto 0); - CTRL_2_OUT : out std_logic_vector(15 downto 0); - CTRL_3_OUT : out std_logic_vector(15 downto 0); - CTRL_4_OUT : out std_logic_vector(15 downto 0); - CTRL_5_OUT : out std_logic_vector(15 downto 0); - CTRL_6_OUT : out std_logic_vector(15 downto 0); - CTRL_7_OUT : out std_logic_vector(15 downto 0); - CTRL_8_OUT : out std_logic_vector(15 downto 0); - CTRL_9_OUT : out std_logic_vector(15 downto 0); - CTRL_10_OUT : out std_logic_vector(15 downto 0); - CTRL_11_OUT : out std_logic_vector(15 downto 0); - CTRL_12_OUT : out std_logic_vector(15 downto 0); - CTRL_13_OUT : out std_logic_vector(15 downto 0); - CTRL_14_OUT : out std_logic_vector(15 downto 0); - CTRL_15_OUT : out std_logic_vector(15 downto 0); - STAT_0_IN : in std_logic_vector(15 downto 0); - STAT_1_IN : in std_logic_vector(15 downto 0); - STAT_2_IN : in std_logic_vector(15 downto 0); - STAT_3_IN : in std_logic_vector(15 downto 0); - STAT_4_IN : in std_logic_vector(15 downto 0); - STAT_5_IN : in std_logic_vector(15 downto 0); - STAT_6_IN : in std_logic_vector(15 downto 0); - STAT_7_IN : in std_logic_vector(15 downto 0); - STAT_8_IN : in std_logic_vector(15 downto 0); - STAT_9_IN : in std_logic_vector(15 downto 0); - STAT_10_IN : in std_logic_vector(15 downto 0); - STAT_11_IN : in std_logic_vector(15 downto 0); - STAT_12_IN : in std_logic_vector(15 downto 0); - STAT_13_IN : in std_logic_vector(15 downto 0); - STAT_14_IN : in std_logic_vector(15 downto 0); - STAT_15_IN : in std_logic_vector(15 downto 0); - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); +generic( + RESET_VALUE : std_logic_vector(15 downto 0) := x"0001" +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(3 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + BACKPLANE_IN : in std_logic_vector(2 downto 0); + CTRL_0_OUT : out std_logic_vector(15 downto 0); + CTRL_1_OUT : out std_logic_vector(15 downto 0); + CTRL_2_OUT : out std_logic_vector(15 downto 0); + CTRL_3_OUT : out std_logic_vector(15 downto 0); + CTRL_4_OUT : out std_logic_vector(15 downto 0); + CTRL_5_OUT : out std_logic_vector(15 downto 0); + CTRL_6_OUT : out std_logic_vector(15 downto 0); + CTRL_7_OUT : out std_logic_vector(15 downto 0); + CTRL_8_OUT : out std_logic_vector(15 downto 0); + CTRL_9_OUT : out std_logic_vector(15 downto 0); + CTRL_10_OUT : out std_logic_vector(15 downto 0); + CTRL_11_OUT : out std_logic_vector(15 downto 0); + CTRL_12_OUT : out std_logic_vector(15 downto 0); + CTRL_13_OUT : out std_logic_vector(15 downto 0); + CTRL_14_OUT : out std_logic_vector(15 downto 0); + CTRL_15_OUT : out std_logic_vector(15 downto 0); + STAT_0_IN : in std_logic_vector(15 downto 0); + STAT_1_IN : in std_logic_vector(15 downto 0); + STAT_2_IN : in std_logic_vector(15 downto 0); + STAT_3_IN : in std_logic_vector(15 downto 0); + STAT_4_IN : in std_logic_vector(15 downto 0); + STAT_5_IN : in std_logic_vector(15 downto 0); + STAT_6_IN : in std_logic_vector(15 downto 0); + STAT_7_IN : in std_logic_vector(15 downto 0); + STAT_8_IN : in std_logic_vector(15 downto 0); + STAT_9_IN : in std_logic_vector(15 downto 0); + STAT_10_IN : in std_logic_vector(15 downto 0); + STAT_11_IN : in std_logic_vector(15 downto 0); + STAT_12_IN : in std_logic_vector(15 downto 0); + STAT_13_IN : in std_logic_vector(15 downto 0); + STAT_14_IN : in std_logic_vector(15 downto 0); + STAT_15_IN : in std_logic_vector(15 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); end entity; architecture Behavioral of slv_register_bank is -- Signals - type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; - - signal adc_addr : std_logic_vector(3 downto 0); -- ADC address after mapping - signal reg_sel : std_logic_vector(15 downto 0); - signal reg_wr : std_logic_vector(15 downto 0); - signal reg_wr_x : std_logic_vector(15 downto 0); - - type ctrl_reg_t is array (0 to 15) of std_logic_vector(15 downto 0); - signal ctrl_reg : ctrl_reg_t; - - signal rdback_data : std_logic_vector(31 downto 0); - +type STATES is (SLEEP,RD_RDY,RD_DEL0,RD_DEL1,WR_DEL0,WR_DEL1,WR_RDY,RD_ACK,WR_ACK,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +signal slv_ack_x : std_logic; +signal slv_ack : std_logic; +signal store_wr_x : std_logic; +signal store_wr : std_logic; +signal store_rd_x : std_logic; +signal store_rd : std_logic; + +signal adc_addr : std_logic_vector(3 downto 0); -- ADC address after mapping +signal reg_sel : std_logic_vector(15 downto 0); +signal reg_wr : std_logic_vector(15 downto 0); +signal reg_wr_x : std_logic_vector(15 downto 0); + +type ctrl_reg_t is array (0 to 15) of std_logic_vector(15 downto 0); +signal ctrl_reg : ctrl_reg_t; + +signal rdback_data : std_logic_vector(31 downto 0); + begin -- Fake @@ -88,48 +91,49 @@ stat <= (others => '0'); -- Mapping of backplanes -- --------------------------------------------------------- THE_APV_ADC_MAP_MEM: apv_adc_map_mem -port map( ADDRESS(6 downto 4) => backplane_in, - ADDRESS(3 downto 0) => slv_addr_in, - Q => adc_addr - ); +port map( + ADDRESS(6 downto 4) => backplane_in, + ADDRESS(3 downto 0) => slv_addr_in, + Q => adc_addr +); THE_REG_SEL_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then case adc_addr is - when x"0" => reg_sel <= b"0000_0000_0000_0001"; + when x"0" => reg_sel <= b"0000_0000_0000_0001"; rdback_data <= stat_0_in & ctrl_reg(0); - when x"1" => reg_sel <= b"0000_0000_0000_0010"; + when x"1" => reg_sel <= b"0000_0000_0000_0010"; rdback_data <= stat_1_in & ctrl_reg(1); - when x"2" => reg_sel <= b"0000_0000_0000_0100"; + when x"2" => reg_sel <= b"0000_0000_0000_0100"; rdback_data <= stat_2_in & ctrl_reg(2); - when x"3" => reg_sel <= b"0000_0000_0000_1000"; + when x"3" => reg_sel <= b"0000_0000_0000_1000"; rdback_data <= stat_3_in & ctrl_reg(3); - when x"4" => reg_sel <= b"0000_0000_0001_0000"; + when x"4" => reg_sel <= b"0000_0000_0001_0000"; rdback_data <= stat_4_in & ctrl_reg(4); - when x"5" => reg_sel <= b"0000_0000_0010_0000"; + when x"5" => reg_sel <= b"0000_0000_0010_0000"; rdback_data <= stat_5_in & ctrl_reg(5); - when x"6" => reg_sel <= b"0000_0000_0100_0000"; + when x"6" => reg_sel <= b"0000_0000_0100_0000"; rdback_data <= stat_6_in & ctrl_reg(6); - when x"7" => reg_sel <= b"0000_0000_1000_0000"; + when x"7" => reg_sel <= b"0000_0000_1000_0000"; rdback_data <= stat_7_in & ctrl_reg(7); - when x"8" => reg_sel <= b"0000_0001_0000_0000"; + when x"8" => reg_sel <= b"0000_0001_0000_0000"; rdback_data <= stat_8_in & ctrl_reg(8); - when x"9" => reg_sel <= b"0000_0010_0000_0000"; + when x"9" => reg_sel <= b"0000_0010_0000_0000"; rdback_data <= stat_9_in & ctrl_reg(9); - when x"a" => reg_sel <= b"0000_0100_0000_0000"; + when x"a" => reg_sel <= b"0000_0100_0000_0000"; rdback_data <= stat_10_in & ctrl_reg(10); - when x"b" => reg_sel <= b"0000_1000_0000_0000"; + when x"b" => reg_sel <= b"0000_1000_0000_0000"; rdback_data <= stat_11_in & ctrl_reg(11); - when x"c" => reg_sel <= b"0001_0000_0000_0000"; + when x"c" => reg_sel <= b"0001_0000_0000_0000"; rdback_data <= stat_12_in & ctrl_reg(12); - when x"d" => reg_sel <= b"0010_0000_0000_0000"; + when x"d" => reg_sel <= b"0010_0000_0000_0000"; rdback_data <= stat_13_in & ctrl_reg(13); - when x"e" => reg_sel <= b"0100_0000_0000_0000"; + when x"e" => reg_sel <= b"0100_0000_0000_0000"; rdback_data <= stat_14_in & ctrl_reg(14); - when x"f" => reg_sel <= b"1000_0000_0000_0000"; + when x"f" => reg_sel <= b"1000_0000_0000_0000"; rdback_data <= stat_15_in & ctrl_reg(15); - when others => reg_sel <= b"0000_0000_0000_0000"; -- never used + when others => reg_sel <= b"0000_0000_0000_0000"; -- never used rdback_data <= x"0000_0000"; end case; end if; @@ -164,38 +168,38 @@ begin store_wr_x <= '0'; store_rd_x <= '0'; case CURRENT_STATE is - when SLEEP => if ( slv_read_in = '1' ) then + when SLEEP => if ( slv_read_in = '1' ) then NEXT_STATE <= RD_DEL0; store_rd_x <= '1'; elsif( slv_write_in = '1' ) then NEXT_STATE <= WR_DEL0; store_wr_x <= '1'; - else + else NEXT_STATE <= SLEEP; end if; - when RD_DEL0 => NEXT_STATE <= RD_DEL1; - when RD_DEL1 => NEXT_STATE <= RD_RDY; - when RD_RDY => NEXT_STATE <= RD_ACK; - when RD_ACK => if( slv_read_in = '0' ) then + when RD_DEL0 => NEXT_STATE <= RD_DEL1; + when RD_DEL1 => NEXT_STATE <= RD_RDY; + when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_ACK => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; slv_ack_x <= '1'; else NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; end if; - when WR_DEL0 => NEXT_STATE <= WR_DEL1; - when WR_DEL1 => NEXT_STATE <= WR_RDY; - when WR_RDY => NEXT_STATE <= WR_ACK; - when WR_ACK => if( slv_write_in = '0' ) then + when WR_DEL0 => NEXT_STATE <= WR_DEL1; + when WR_DEL1 => NEXT_STATE <= WR_RDY; + when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_ACK => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; slv_ack_x <= '1'; else NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; @@ -204,7 +208,7 @@ end process TRANSFORM; --------------------------------------------------------- -- register write -GEN_CTRL_REG: for i in 0 to 15 generate +GEN_CTRL_REG: for i in 0 to 15 generate THE_WR_REG_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then diff --git a/src/spi_adc_master.vhd b/src/spi_adc_master.vhd index 92ed5c9..74dab72 100644 --- a/src/spi_adc_master.vhd +++ b/src/spi_adc_master.vhd @@ -7,58 +7,61 @@ library work; use work.adcmv3_components.all; entity spi_adc_master is -generic( RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" ); -port( CLK_IN : in std_logic; - RESET_IN : in std_logic; - -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- SPI connections - SPI_CS_OUT : out std_logic; - SPI_SDO_OUT : out std_logic; - SPI_SCK_OUT : out std_logic; - -- ADC connections - ADC_LOCKED_IN : in std_logic; - ADC_PD_OUT : out std_logic; - ADC_RST_OUT : out std_logic; - ADC_DEL_OUT : out std_logic_vector(3 downto 0); - -- APV connections - APV_RST_OUT : out std_logic; - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); +generic( + RESET_VALUE_CTRL : std_logic_vector(7 downto 0) := x"60" +); +port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- SPI connections + SPI_CS_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; + SPI_SCK_OUT : out std_logic; + -- ADC connections + ADC_LOCKED_IN : in std_logic; + ADC_PD_OUT : out std_logic; + ADC_RST_OUT : out std_logic; + ADC_DEL_OUT : out std_logic_vector(3 downto 0); + -- APV connections + APV_RST_OUT : out std_logic; + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); end entity; architecture Behavioral of spi_adc_master is -- Signals - type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - - signal status_data : std_logic_vector(31 downto 0); - signal spi_busy : std_logic; - - signal reg_ctrl_data : std_logic_vector(7 downto 0); - signal adc_ctrl_data : std_logic_vector(7 downto 0); - - signal reg_slv_data_out : std_logic_vector(31 downto 0); -- readback - - signal spi_start_x : std_logic; - signal spi_start : std_logic; - - -- State machine signals - signal slv_busy_x : std_logic; - signal slv_busy : std_logic; - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; +type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +signal status_data : std_logic_vector(31 downto 0); +signal spi_busy : std_logic; + +signal reg_ctrl_data : std_logic_vector(7 downto 0); +signal adc_ctrl_data : std_logic_vector(7 downto 0); + +signal reg_slv_data_out : std_logic_vector(31 downto 0); -- readback + +signal spi_start_x : std_logic; +signal spi_start : std_logic; + +-- State machine signals +signal slv_busy_x : std_logic; +signal slv_busy : std_logic; +signal slv_ack_x : std_logic; +signal slv_ack : std_logic; +signal store_wr_x : std_logic; +signal store_wr : std_logic; +signal store_rd_x : std_logic; +signal store_rd : std_logic; begin @@ -67,21 +70,22 @@ begin --------------------------------------------------------- THE_SPI_REAL_SLIM: spi_real_slim -port map( SYSCLK => clk_in, - RESET => reset_in, - -- Command interface - START_IN => spi_start, - BUSY_OUT => spi_busy, - CMD_IN => reg_ctrl_data, - -- SPI interface - SPI_SCK_OUT => spi_sck_out, - SPI_CS_OUT => spi_cs_out, - SPI_SDO_OUT => spi_sdo_out, - -- DEBUG - CLK_EN_OUT => open, - BSM_OUT => open, - DEBUG_OUT => open - ); +port map( + SYSCLK => clk_in, + RESET => reset_in, + -- Command interface + START_IN => spi_start, + BUSY_OUT => spi_busy, + CMD_IN => reg_ctrl_data, + -- SPI interface + SPI_SCK_OUT => spi_sck_out, + SPI_CS_OUT => spi_cs_out, + SPI_SDO_OUT => spi_sdo_out, + -- DEBUG + CLK_EN_OUT => open, + BSM_OUT => open, + DEBUG_OUT => open +); --------------------------------------------------------- -- Statemachine -- @@ -115,7 +119,7 @@ begin store_wr_x <= '0'; store_rd_x <= '0'; case CURRENT_STATE is - when SLEEP => if ( (spi_busy = '0') and (slv_read_in = '1') ) then + when SLEEP => if ( (spi_busy = '0') and (slv_read_in = '1') ) then NEXT_STATE <= RD_RDY; store_rd_x <= '1'; elsif( (spi_busy = '0') and (slv_write_in = '1') ) then @@ -127,40 +131,40 @@ begin elsif( (spi_busy = '1') and (slv_write_in = '1') ) then NEXT_STATE <= WR_BSY; slv_busy_x <= '1'; - else + else NEXT_STATE <= SLEEP; end if; - when RD_RDY => NEXT_STATE <= RD_ACK; + when RD_RDY => NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; - when WR_RDY => NEXT_STATE <= WR_ACK; + when WR_RDY => NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; - when RD_ACK => if( slv_read_in = '0' ) then + when RD_ACK => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= RD_ACK; slv_ack_x <= '1'; end if; - when WR_ACK => if( slv_write_in = '0' ) then + when WR_ACK => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= WR_ACK; slv_ack_x <= '1'; end if; - when RD_BSY => if( slv_read_in = '0' ) then + when RD_BSY => if( slv_read_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= RD_BSY; slv_busy_x <= '1'; end if; - when WR_BSY => if( slv_write_in = '0' ) then + when WR_BSY => if( slv_write_in = '0' ) then NEXT_STATE <= DONE; else NEXT_STATE <= WR_BSY; slv_busy_x <= '1'; end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; end case; end process TRANSFORM; diff --git a/src/spi_real_slim.vhd b/src/spi_real_slim.vhd index 4b83c1e..2ad57b3 100644 --- a/src/spi_real_slim.vhd +++ b/src/spi_real_slim.vhd @@ -7,60 +7,61 @@ use work.adcmv3_components.all; entity spi_real_slim is - port( SYSCLK : in std_logic; -- 100MHz sysclock - RESET : in std_logic; -- synchronous reset - -- Command interface - START_IN : in std_logic; -- one start pulse - BUSY_OUT : out std_logic; -- SPI transactions are ongoing - CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte - -- SPI interface - SPI_SCK_OUT : out std_logic; - SPI_CS_OUT : out std_logic; - SPI_SDO_OUT : out std_logic; - -- DEBUG - CLK_EN_OUT : out std_logic; - BSM_OUT : out std_logic_vector(7 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); +port( + SYSCLK : in std_logic; -- 100MHz sysclock + RESET : in std_logic; -- synchronous reset + -- Command interface + START_IN : in std_logic; -- one start pulse + BUSY_OUT : out std_logic; -- SPI transactions are ongoing + CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte + -- SPI interface + SPI_SCK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; + SPI_SDO_OUT : out std_logic; + -- DEBUG + CLK_EN_OUT : out std_logic; + BSM_OUT : out std_logic_vector(7 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) +); end spi_real_slim; architecture Behavioral of spi_real_slim is -- new clock divider -signal div_counter : std_logic_vector(1 downto 0); -signal div_done_x : std_logic; -signal div_done : std_logic; -- same as clk_en -signal clk_en : std_logic; -- same as div_done +signal div_counter : std_logic_vector(1 downto 0); +signal div_done_x : std_logic; +signal div_done : std_logic; -- same as clk_en +signal clk_en : std_logic; -- same as div_done -- Statemachine signals type state_t is (IDLE,CSL,TXCMD,CSH); -signal STATE, NEXT_STATE : state_t; - -signal tx_ena_x : std_logic; -signal tx_ena : std_logic; -signal busy_x : std_logic; -signal busy : std_logic; -signal spi_cs_x : std_logic; -- SPI chip select (low active) -signal spi_cs : std_logic; -signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter) -signal spi_sck : std_logic; -signal tx_load_x : std_logic; -- load TX shift register -signal tx_load : std_logic; - -signal last_tx_bit_x : std_logic; -signal last_tx_bit : std_logic; +signal STATE, NEXT_STATE : state_t; + +signal tx_ena_x : std_logic; +signal tx_ena : std_logic; +signal busy_x : std_logic; +signal busy : std_logic; +signal spi_cs_x : std_logic; -- SPI chip select (low active) +signal spi_cs : std_logic; +signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter) +signal spi_sck : std_logic; +signal tx_load_x : std_logic; -- load TX shift register +signal tx_load : std_logic; + +signal last_tx_bit_x : std_logic; +signal last_tx_bit : std_logic; -- debug signals -signal bsm_x : std_logic_vector(7 downto 0); -signal debug_x : std_logic_vector(31 downto 0); +signal bsm_x : std_logic_vector(7 downto 0); +signal debug_x : std_logic_vector(31 downto 0); -signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine -signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes +signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine +signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes -- transmitter -signal tx_sreg : std_logic_vector(7 downto 0); -signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer -signal tx_bit_cnt : std_logic_vector(3 downto 0); +signal tx_sreg : std_logic_vector(7 downto 0); +signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer +signal tx_bit_cnt : std_logic_vector(3 downto 0); begin @@ -82,7 +83,7 @@ debug_x(7) <= '0'; debug_x(6) <= '0'; debug_x(5) <= tx_load; debug_x(4) <= tx_ena; -debug_x(3) <= '0'; +debug_x(3) <= '0'; debug_x(2 downto 0) <= (others => '0'); @@ -200,11 +201,11 @@ end process THE_STATE_TRANSITIONS; THE_STATEMACHINE_OUT: process( STATE ) begin case STATE is - when IDLE => bsm_x <= x"00"; - when CSL => bsm_x <= x"01"; - when TXCMD => bsm_x <= x"02"; - when CSH => bsm_x <= x"03"; - when others => bsm_x <= x"ff"; + when IDLE => bsm_x <= x"00"; + when CSL => bsm_x <= x"01"; + when TXCMD => bsm_x <= x"02"; + when CSH => bsm_x <= x"03"; + when others => bsm_x <= x"ff"; end case; end process THE_STATEMACHINE_OUT; diff --git a/src/state_sync.vhd b/src/state_sync.vhd index a00cd2f..82813b2 100644 --- a/src/state_sync.vhd +++ b/src/state_sync.vhd @@ -7,19 +7,20 @@ library work; use work.adcmv3_components.all; entity state_sync is - port( STATE_A_IN : in std_logic; - RESET_B_IN : in std_logic; - CLK_B_IN : in std_logic; - STATE_B_OUT : out std_logic - ); +port( + STATE_A_IN : in std_logic; + RESET_B_IN : in std_logic; + CLK_B_IN : in std_logic; + STATE_B_OUT : out std_logic +); end; architecture behavioral of state_sync is - -- normal signals - signal sync_q : std_logic; - signal sync_qq : std_logic; - +-- normal signals +signal sync_q : std_logic; +signal sync_qq : std_logic; + begin -- synchronizing stage for clock domain B diff --git a/src/tb_apv_trgctrl.vhd b/src/tb_apv_trgctrl.vhd index ec21ace..09b79f2 100755 --- a/src/tb_apv_trgctrl.vhd +++ b/src/tb_apv_trgctrl.vhd @@ -28,8 +28,10 @@ ARCHITECTURE behavior OF testbench IS TRB_TTAG_IN : IN std_logic_vector(15 downto 0); TRB_TRND_IN : IN std_logic_vector(7 downto 0); TRB_TTYPE_IN : IN std_logic_vector(3 downto 0); + TRB_TINFO_IN : IN std_logic_vector(23 downto 0); TRB_TRGRCVD_IN : IN std_logic; - TRB_RST_COUNTER_IN : IN std_logic; + TRB_COUNTER_IN : IN std_logic_vector(15 downto 0); + TRB_LD_COUNTER_IN : IN std_logic; EDS_DONE_IN : IN std_logic; TRG_FOUND_OUT : OUT std_logic; TRB_MISSING_OUT : OUT std_logic; @@ -66,10 +68,12 @@ ARCHITECTURE behavior OF testbench IS SIGNAL TRB_TTAG_IN : std_logic_vector(15 downto 0); SIGNAL TRB_TRND_IN : std_logic_vector(7 downto 0); SIGNAL TRB_TTYPE_IN : std_logic_vector(3 downto 0); + SIGNAL TRB_TINFO_IN : std_logic_vector(23 downto 0); SIGNAL TRB_TRGRCVD_IN : std_logic; SIGNAL TRB_MISSING_OUT : std_logic; SIGNAL TRB_RELEASE_OUT : std_logic; - SIGNAL TRB_RST_COUNTER_IN : std_logic; + SIGNAL TRB_COUNTER_IN : std_logic_vector(15 downto 0); + SIGNAL TRB_LD_COUNTER_IN : std_logic; SIGNAL TRB_COUNTER_OUT : std_logic_vector(15 downto 0); SIGNAL EDS_DATA_OUT : std_logic_vector(39 downto 0); SIGNAL EDS_AVAIL_OUT : std_logic; @@ -105,10 +109,12 @@ BEGIN TRB_TTAG_IN => TRB_TTAG_IN, TRB_TRND_IN => TRB_TRND_IN, TRB_TTYPE_IN => TRB_TTYPE_IN, + TRB_TINFO_IN => TRB_TINFO_IN, TRB_TRGRCVD_IN => TRB_TRGRCVD_IN, TRB_MISSING_OUT => TRB_MISSING_OUT, TRB_RELEASE_OUT => TRB_RELEASE_OUT, - TRB_RST_COUNTER_IN => TRB_RST_COUNTER_IN, + TRB_COUNTER_IN => TRB_COUNTER_IN, + TRB_LD_COUNTER_IN => TRB_LD_COUNTER_IN, TRB_COUNTER_OUT => TRB_COUNTER_OUT, EDS_DATA_OUT => EDS_DATA_OUT, EDS_AVAIL_OUT => EDS_AVAIL_OUT, @@ -155,8 +161,10 @@ begin trb_ttag_in <= x"0000"; trb_trnd_in <= x"00"; trb_ttype_in <= x"0"; + trb_tinfo_in <= x"00_00_00"; trb_trgrcvd_in <= '0'; - trb_rst_counter_in <= '0'; + trb_counter_in <= x"dead"; + trb_ld_counter_in <= '0'; eds_done_in <= '0'; wait for 20 ns; @@ -181,6 +189,12 @@ begin wait until rising_edge(clk_in); wait for 1 us; + + -- Set local LVL1 counter to TRBnet value + wait until rising_edge(clk_in); + trb_ld_counter_in <= '1'; + wait until rising_edge(clk_in); + trb_ld_counter_in <= '0'; -- first trigger -- send in one timing trigger @@ -193,12 +207,14 @@ begin wait for 2.3 us; wait until rising_edge(clk_in); trb_ttype_in <= x"1"; - trb_ttag_in <= x"abcd"; - trb_trnd_in <= x"ef"; + trb_ttag_in <= x"dead"; + trb_trnd_in <= x"a0"; + trb_tinfo_in <= x"00_00_00"; -- data format = b"000" wait until rising_edge(clk_in); trb_trgrcvd_in <= '1'; -- release trigger + wait until rising_edge(clk_in); wait until rising_edge(trb_release_out); wait until rising_edge(clk_in); wait until rising_edge(clk_in); @@ -218,8 +234,75 @@ begin wait for 2.3 us; wait until rising_edge(clk_in); trb_ttype_in <= x"2"; - trb_ttag_in <= x"dead"; + trb_ttag_in <= x"deae"; trb_trnd_in <= x"42"; + trb_tinfo_in <= x"00_01_00"; -- data format = b"001" + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '1'; + + -- release trigger + wait until rising_edge(trb_release_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '0'; + wait until rising_edge(clk_in); + + wait for 1.11 us; + + -- next trigger (missing timing trigger) + -- send TRB trigger infos + wait for 2.3 us; + wait until rising_edge(clk_in); + trb_ttype_in <= x"3"; + trb_ttag_in <= x"deaf"; + trb_trnd_in <= x"7c"; + trb_tinfo_in <= x"00_05_00"; -- data format = b"101" + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '1'; + + -- release trigger + wait until rising_edge(trb_release_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '0'; + wait until rising_edge(clk_in); + + wait for 1.51 us; + + -- next trigger (timingtriggerless trigger) + -- send TRB trigger infos + wait for 2.3 us; + wait until rising_edge(clk_in); + trb_ttype_in <= x"9"; + trb_ttag_in <= x"deb0"; + trb_trnd_in <= x"19"; + trb_tinfo_in <= x"00_00_80"; -- timingtriggerless trigger + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '1'; + + -- release trigger + wait until rising_edge(trb_release_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '0'; + wait until rising_edge(clk_in); + + wait for 1.21 us; + + -- next trigger + -- send in one timing trigger + wait for 77.7 ns; + time_trg_in <= x"1"; + wait for 222.2 ns; + time_trg_in <= x"0"; + + -- send TRB trigger infos + wait for 2.3 us; + wait until rising_edge(clk_in); + trb_ttype_in <= x"4"; + trb_ttag_in <= x"deb1"; + trb_trnd_in <= x"97"; + trb_tinfo_in <= x"00_00_01"; -- data format = b"000", suppress data wait until rising_edge(clk_in); trb_trgrcvd_in <= '1'; @@ -237,16 +320,35 @@ begin eds_done_in <= '1'; wait until rising_edge(clk_in); eds_done_in <= '0'; + wait for 100 ns; + + -- release one EDS wait until rising_edge(clk_in); + eds_done_in <= '1'; + wait until rising_edge(clk_in); + eds_done_in <= '0'; + wait for 100 ns; - wait for 200 ns; + -- release one EDS + wait until rising_edge(clk_in); + eds_done_in <= '1'; + wait until rising_edge(clk_in); + eds_done_in <= '0'; + wait for 100 ns; -- release one EDS wait until rising_edge(clk_in); eds_done_in <= '1'; wait until rising_edge(clk_in); eds_done_in <= '0'; + wait for 100 ns; + + -- release one EDS wait until rising_edge(clk_in); + eds_done_in <= '1'; + wait until rising_edge(clk_in); + eds_done_in <= '0'; + wait for 100 ns; -- Stay a while, stay forever.... wuhahahahaha diff --git a/src/tb_ipu_fifo_stage.vhd b/src/tb_ipu_fifo_stage.vhd index c1d3d3a..19e384d 100644 --- a/src/tb_ipu_fifo_stage.vhd +++ b/src/tb_ipu_fifo_stage.vhd @@ -2,9 +2,6 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; -library work; -use work.adcmv3_components.all; - ENTITY testbench IS END testbench; @@ -24,6 +21,7 @@ ARCHITECTURE behavior OF testbench IS DHDR_LENGTH_IN : IN std_logic_vector(15 downto 0); DHDR_STORE_IN : IN std_logic; FIFO_START_IN : IN std_logic; + FIFO_SPACE_REQ_IN : IN std_logic_vector(11 downto 0); FIFO_0_DATA_IN : IN std_logic_vector(39 downto 0); FIFO_1_DATA_IN : IN std_logic_vector(39 downto 0); FIFO_2_DATA_IN : IN std_logic_vector(39 downto 0); @@ -47,6 +45,8 @@ ARCHITECTURE behavior OF testbench IS IPU_READOUT_FINISHED_OUT : OUT std_logic; IPU_LENGTH_OUT : OUT std_logic_vector(15 downto 0); IPU_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0); + LVL2_COUNTER_OUT : OUT std_logic_vector(15 downto 0); + DHDR_BUF_FULL_OUT : OUT std_logic; DBG_BSM_OUT : OUT std_logic_vector(7 downto 0); DBG_OUT : OUT std_logic_vector(63 downto 0) ); @@ -65,10 +65,13 @@ ARCHITECTURE behavior OF testbench IS SIGNAL IPU_READ_IN : std_logic; SIGNAL IPU_LENGTH_OUT : std_logic_vector(15 downto 0); SIGNAL IPU_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0); + SIGNAL LVL2_COUNTER_OUT : std_logic_vector(15 downto 0); SIGNAL DHDR_DATA_IN : std_logic_vector(31 downto 0); SIGNAL DHDR_LENGTH_IN : std_logic_vector(15 downto 0); SIGNAL DHDR_STORE_IN : std_logic; + SIGNAL DHDR_BUF_FULL_OUT : std_logic; SIGNAL FIFO_START_IN : std_logic; + SIGNAL FIFO_SPACE_REQ_IN : std_logic_vector(11 downto 0); SIGNAL FIFO_0_DATA_IN : std_logic_vector(39 downto 0); SIGNAL FIFO_1_DATA_IN : std_logic_vector(39 downto 0); SIGNAL FIFO_2_DATA_IN : std_logic_vector(39 downto 0); @@ -107,10 +110,13 @@ BEGIN IPU_READ_IN => IPU_READ_IN, IPU_LENGTH_OUT => IPU_LENGTH_OUT, IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_OUT, + LVL2_COUNTER_OUT => LVL2_COUNTER_OUT, DHDR_DATA_IN => DHDR_DATA_IN, DHDR_LENGTH_IN => DHDR_LENGTH_IN, DHDR_STORE_IN => DHDR_STORE_IN, + DHDR_BUF_FULL_OUT => DHDR_BUF_FULL_OUT, FIFO_START_IN => FIFO_START_IN, + FIFO_SPACE_REQ_IN => FIFO_SPACE_REQ_IN, FIFO_0_DATA_IN => FIFO_0_DATA_IN, FIFO_1_DATA_IN => FIFO_1_DATA_IN, FIFO_2_DATA_IN => FIFO_2_DATA_IN, @@ -155,6 +161,8 @@ begin dhdr_data_in <= x"01234567"; dhdr_length_in <= x"0000"; dhdr_store_in <= '0'; +-- fifo_space_req_in <= x"082"; -- 128 + 2 + fifo_space_req_in <= x"7f8"; fifo_start_in <= '0'; fifo_we_in <= x"0000"; fifo_done_in <= '0'; @@ -199,6 +207,7 @@ begin -- Fill data buffers wait until rising_edge(clk_in); fifo_we_in <= b"1111_1111_1111_1111"; +-- fifo_we_in <= b"1111_1111_0111_1111"; fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_1111"; fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0001_1110"; fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0010_1101"; @@ -216,31 +225,322 @@ begin fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1110_0001"; fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_1111_0000"; wait until rising_edge(clk_in); - fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; - fifo_we_in(0) <= '0'; - wait until rising_edge(clk_in); - +-- fifo_we_in <= b"1111_1111_1111_1110"; + fifo_we_in <= b"1111_1111_0111_1110"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0001_1110"; + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0010_1101"; + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0011_1100"; + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0100_1011"; + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0101_1010"; + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0110_1001"; + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_0111_1000"; + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1000_0111"; + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1001_0110"; + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1010_0101"; + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0001_1111_0000"; + wait until rising_edge(clk_in); +-- fifo_we_in <= b"1111_1111_1111_1100"; + fifo_we_in <= b"1111_1111_0111_1100"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0010_1101"; + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0011_1100"; + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0100_1011"; + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0101_1010"; + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0110_1001"; + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_0111_1000"; + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1000_0111"; + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1001_0110"; + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1010_0101"; + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0010_1111_0000"; + wait until rising_edge(clk_in); +-- fifo_we_in <= b"1111_1111_1111_1000"; + fifo_we_in <= b"1111_1111_0111_1000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0011_1100"; + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0100_1011"; + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0101_1010"; + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0110_1001"; + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_0111_1000"; + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1000_0111"; + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1001_0110"; + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1010_0101"; + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0011_1111_0000"; + wait until rising_edge(clk_in); +-- fifo_we_in <= b"1111_1111_1111_0000"; + fifo_we_in <= b"1111_1111_0111_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0100_1011"; + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0101_1010"; + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0110_1001"; + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_0111_1000"; + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1000_0111"; + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1001_0110"; + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1010_0101"; + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0100_1111_0000"; + wait until rising_edge(clk_in); +-- fifo_we_in <= b"1111_1111_1110_0000"; + fifo_we_in <= b"1111_1111_0110_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0101_1010"; + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0110_1001"; + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_0111_1000"; + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1000_0111"; + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1001_0110"; + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1010_0101"; + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0101_1111_0000"; + wait until rising_edge(clk_in); +-- fifo_we_in <= b"1111_1111_1100_0000"; + fifo_we_in <= b"1111_1111_0100_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_0110_1001"; + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_0111_1000"; + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1000_0111"; + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1001_0110"; + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1010_0101"; + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0110_1111_0000"; + wait until rising_edge(clk_in); +-- fifo_we_in <= b"1111_1111_1000_0000"; + fifo_we_in <= b"1111_1111_0000_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_0111_1000"; + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1000_0111"; + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1001_0110"; + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1010_0101"; + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0111_1111_0000"; + wait until rising_edge(clk_in); + fifo_we_in <= b"1111_1111_0000_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1000_0111"; + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1001_0110"; + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1010_0101"; + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1000_1111_0000"; + wait until rising_edge(clk_in); + fifo_we_in <= b"1111_1110_0000_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1001_0110"; + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1010_0101"; + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1001_1111_0000"; + wait until rising_edge(clk_in); + fifo_we_in <= b"1111_1100_0000_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1010_0101"; + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1010_1111_0000"; + wait until rising_edge(clk_in); + fifo_we_in <= b"1111_1000_0000_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1011_0100"; + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1011_1111_0000"; + wait until rising_edge(clk_in); + fifo_we_in <= b"1111_0000_0000_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1100_0011"; + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1100_1111_0000"; + wait until rising_edge(clk_in); + fifo_we_in <= b"1110_0000_0000_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1101_0010"; + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1101_1111_0000"; + wait until rising_edge(clk_in); + fifo_we_in <= b"1100_0000_0000_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_1110_1110_0001"; + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1110_1111_0000"; + wait until rising_edge(clk_in); + fifo_we_in <= b"1000_0000_0000_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_1111_1111_0000"; + wait until rising_edge(clk_in); + fifo_we_in <= b"0000_0000_0000_0000"; + fifo_0_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_1_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_2_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_3_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_4_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_5_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_6_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_7_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_8_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_9_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_10_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_11_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_12_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_13_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_14_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off + fifo_15_data_in(26 downto 0) <= b"000_00_00_0000_0000_0000_0000_0000"; -- off wait until rising_edge(clk_in); -- Final stage, counter values setting wait until rising_edge(clk_in); wait until rising_edge(clk_in); - fifo_0_data_in(37 downto 27) <= "10000000001"; -- "10000000011"; -- 3 - fifo_1_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid - fifo_2_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid - fifo_3_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid - fifo_4_data_in(37 downto 27) <= "10000000001"; -- "10000000101"; -- 5 - fifo_5_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid - fifo_6_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid - fifo_7_data_in(37 downto 27) <= "10000000001"; -- "10000000111"; -- 7 - fifo_8_data_in(37 downto 27) <= "10000000001"; -- "10000000001"; -- 1 - fifo_9_data_in(37 downto 27) <= "10000000001"; -- "10000000010"; -- 2 - fifo_10_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid - fifo_11_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid - fifo_12_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid - fifo_13_data_in(37 downto 27) <= "10000000001"; -- "10000001000"; -- 8 - fifo_14_data_in(37 downto 27) <= "10000000001"; -- "10000000111"; -- 7 - fifo_15_data_in(37 downto 27) <= "10000000001"; -- "00000000000"; -- invalid + fifo_0_data_in(37 downto 27) <= "10000000001"; -- 1 + fifo_1_data_in(37 downto 27) <= "10000000010"; -- 2 + fifo_2_data_in(37 downto 27) <= "10000000011"; -- 3 + fifo_3_data_in(37 downto 27) <= "10000000100"; -- 4 + fifo_4_data_in(37 downto 27) <= "10000000101"; -- 5 + fifo_5_data_in(37 downto 27) <= "10000000110"; -- 6 + fifo_6_data_in(37 downto 27) <= "10000000111"; -- 7 +-- fifo_7_data_in(37 downto 27) <= "10000001000"; -- 8 + fifo_7_data_in(37 downto 27) <= "10000000001"; -- NO DATA + fifo_8_data_in(37 downto 27) <= "10000001001"; -- 9 + fifo_9_data_in(37 downto 27) <= "10000001010"; -- 10 + fifo_10_data_in(37 downto 27) <= "10000001011"; -- 11 + fifo_11_data_in(37 downto 27) <= "10000001100"; -- 12 + fifo_12_data_in(37 downto 27) <= "10000001101"; -- 13 + fifo_13_data_in(37 downto 27) <= "10000001110"; -- 14 + fifo_14_data_in(37 downto 27) <= "10000001111"; -- 15 + fifo_15_data_in(37 downto 27) <= "10000010000"; -- 16 wait until rising_edge(clk_in); wait until rising_edge(clk_in); @@ -257,6 +557,7 @@ begin wait until rising_edge(clk_in); wait until rising_edge(clk_in); + wait for 2 us; -- IPU request wait until rising_edge(clk_in); @@ -279,6 +580,43 @@ begin wait until rising_edge(clk_in); wait until rising_edge(clk_in); wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + + THE_LOOP: for i in 0 to 1024 loop + ipu_read_in <= '1'; + wait until (ipu_dataready_out = '1') or (ipu_readout_finished_out = '1'); + if ipu_readout_finished_out = '1' then exit; end if; + wait until rising_edge(clk_in); + ipu_read_in <= '0'; + if ipu_readout_finished_out = '1' then exit; end if; + wait until rising_edge(clk_in); + + end loop THE_LOOP; + + wait; + +--- +-- theloop : for i in 0 to 100 loop +-- ipu_read_in <= '1'; +-- wait until ipu_dataready_out = '1' or ipu_readout_finished_out = '1'; +-- if ipu_readout_finished_out = '1' then exit; end if; +-- wait until rising_edge(CLOCK); +-- ipu_read_in <= '0'; +-- if ipu_readout_finished_out = '1' then exit; end if; +-- case i is +-- when 3 => wait for 39 ns; +-- when 4 => wait for 49 ns; +-- when 5 => wait for 29 ns; +-- when others => null; +-- end case; +-- wait until rising_edge(CLOCK); +-- if ipu_readout_finished_out = '1' then exit; end if; +-- end loop; +--- + + + wait; + ipu_read_in <= '1'; wait until rising_edge(clk_in); diff --git a/src/tb_ped_corr_ctrl.vhd b/src/tb_ped_corr_ctrl.vhd index f968586..4689489 100644 --- a/src/tb_ped_corr_ctrl.vhd +++ b/src/tb_ped_corr_ctrl.vhd @@ -13,7 +13,6 @@ ARCHITECTURE behavior OF testbench IS RESET_IN : IN std_logic; EDS_DATA_IN : IN std_logic_vector(39 downto 0); EDS_AVAIL_IN : IN std_logic; - EVT_TYPE_IN : IN std_logic_vector(2 downto 0); BUF_TICK_IN : IN std_logic_vector(15 downto 0); BUF_START_IN : IN std_logic_vector(15 downto 0); BUF_0_DATA_IN : IN std_logic_vector(37 downto 0); @@ -67,7 +66,9 @@ ARCHITECTURE behavior OF testbench IS EDS_DONE_OUT : OUT std_logic; DHDR_DATA_OUT : OUT std_logic_vector(31 downto 0); DHDR_LENGTH_OUT : OUT std_logic_vector(15 downto 0); + DHDR_BUF_FULL_IN : IN std_logic; DHDR_STORE_OUT : OUT std_logic; + FIFO_SPACE_REQ_OUT : OUT std_logic_vector(11 downto 0); PED_ADDR_OUT : OUT std_logic_vector(6 downto 0); THR_ADDR_OUT : OUT std_logic_vector(6 downto 0); BUF_ADDR_OUT : OUT std_logic_vector(6 downto 0); @@ -103,79 +104,28 @@ ARCHITECTURE behavior OF testbench IS SIGNAL EDS_DONE_OUT : std_logic; SIGNAL DHDR_DATA_OUT : std_logic_vector(31 downto 0); SIGNAL DHDR_LENGTH_OUT : std_logic_vector(15 downto 0); + SIGNAL DHDR_BUF_FULL_IN : std_logic; SIGNAL DHDR_STORE_OUT : std_logic; - SIGNAL EVT_TYPE_IN : std_logic_vector(2 downto 0); SIGNAL BUF_ADDR_OUT : std_logic_vector(6 downto 0); SIGNAL BUF_DONE_OUT : std_logic; SIGNAL BUF_TICK_IN : std_logic_vector(15 downto 0); SIGNAL BUF_START_IN : std_logic_vector(15 downto 0); SIGNAL BUF_0_DATA_IN : std_logic_vector(37 downto 0); SIGNAL BUF_1_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_2_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_3_DATA_IN : std_logic_vector(37 downto 0); SIGNAL BUF_4_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_5_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_6_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_7_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_8_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_9_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_10_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_11_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_12_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_13_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_14_DATA_IN : std_logic_vector(37 downto 0); - SIGNAL BUF_15_DATA_IN : std_logic_vector(37 downto 0); SIGNAL THR_ADDR_OUT : std_logic_vector(6 downto 0); SIGNAL THR_0_DATA_IN : std_logic_vector(17 downto 0); SIGNAL THR_1_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_2_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_3_DATA_IN : std_logic_vector(17 downto 0); SIGNAL THR_4_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_5_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_6_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_7_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_8_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_9_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_10_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_11_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_12_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_13_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_14_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL THR_15_DATA_IN : std_logic_vector(17 downto 0); SIGNAL PED_ADDR_OUT : std_logic_vector(6 downto 0); SIGNAL PED_0_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_1_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_2_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_3_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_4_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_5_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_6_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_7_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_8_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_9_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_10_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_11_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_12_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_13_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_14_DATA_IN : std_logic_vector(17 downto 0); - SIGNAL PED_15_DATA_IN : std_logic_vector(17 downto 0); + SIGNAL FIFO_SPACE_REQ_OUT : std_logic_vector(11 downto 0); SIGNAL FIFO_START_OUT : std_logic; - SIGNAL FIFO_0_DATA_OUT : std_logic_vector(39 downto 0); +-- SIGNAL FIFO_0_DATA_OUT : std_logic_vector(39 downto 0); + SIGNAL ADC_0_STATUS_OUT : std_logic_vector(25 downto 0); + SIGNAL ADC_0_DATA_OUT : std_logic_vector(13 downto 0); SIGNAL FIFO_1_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_2_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_3_DATA_OUT : std_logic_vector(39 downto 0); SIGNAL FIFO_4_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_5_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_6_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_7_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_8_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_9_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_10_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_11_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_12_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_13_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_14_DATA_OUT : std_logic_vector(39 downto 0); - SIGNAL FIFO_15_DATA_OUT : std_logic_vector(39 downto 0); SIGNAL FIFO_WE_OUT : std_logic_vector(15 downto 0); SIGNAL FIFO_DONE_OUT : std_logic; SIGNAL DBG_BSM_OUT : std_logic_vector(7 downto 0); @@ -197,79 +147,82 @@ BEGIN EDS_DONE_OUT => EDS_DONE_OUT, DHDR_DATA_OUT => DHDR_DATA_OUT, DHDR_LENGTH_OUT => DHDR_LENGTH_OUT, + DHDR_BUF_FULL_IN => DHDR_BUF_FULL_IN, DHDR_STORE_OUT => DHDR_STORE_OUT, - EVT_TYPE_IN => EVT_TYPE_IN, BUF_ADDR_OUT => BUF_ADDR_OUT, BUF_DONE_OUT => BUF_DONE_OUT, BUF_TICK_IN => BUF_TICK_IN, BUF_START_IN => BUF_START_IN, BUF_0_DATA_IN => BUF_0_DATA_IN, BUF_1_DATA_IN => BUF_1_DATA_IN, - BUF_2_DATA_IN => BUF_2_DATA_IN, - BUF_3_DATA_IN => BUF_3_DATA_IN, + BUF_2_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", + BUF_3_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", BUF_4_DATA_IN => BUF_4_DATA_IN, - BUF_5_DATA_IN => BUF_5_DATA_IN, - BUF_6_DATA_IN => BUF_6_DATA_IN, - BUF_7_DATA_IN => BUF_7_DATA_IN, - BUF_8_DATA_IN => BUF_8_DATA_IN, - BUF_9_DATA_IN => BUF_9_DATA_IN, - BUF_10_DATA_IN => BUF_10_DATA_IN, - BUF_11_DATA_IN => BUF_11_DATA_IN, - BUF_12_DATA_IN => BUF_12_DATA_IN, - BUF_13_DATA_IN => BUF_13_DATA_IN, - BUF_14_DATA_IN => BUF_14_DATA_IN, - BUF_15_DATA_IN => BUF_15_DATA_IN, + BUF_5_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", + BUF_6_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", + BUF_7_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", + BUF_8_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", + BUF_9_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", + BUF_10_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", + BUF_11_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", + BUF_12_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", + BUF_13_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", + BUF_14_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", + BUF_15_DATA_IN => x"20" & x"0ee" & x"0" & b"00" & x"000", PED_ADDR_OUT => PED_ADDR_OUT, PED_0_DATA_IN => PED_0_DATA_IN, - PED_1_DATA_IN => PED_1_DATA_IN, - PED_2_DATA_IN => PED_2_DATA_IN, - PED_3_DATA_IN => PED_3_DATA_IN, - PED_4_DATA_IN => PED_4_DATA_IN, - PED_5_DATA_IN => PED_5_DATA_IN, - PED_6_DATA_IN => PED_6_DATA_IN, - PED_7_DATA_IN => PED_7_DATA_IN, - PED_8_DATA_IN => PED_8_DATA_IN, - PED_9_DATA_IN => PED_9_DATA_IN, - PED_10_DATA_IN => PED_10_DATA_IN, - PED_11_DATA_IN => PED_11_DATA_IN, - PED_12_DATA_IN => PED_12_DATA_IN, - PED_13_DATA_IN => PED_13_DATA_IN, - PED_14_DATA_IN => PED_14_DATA_IN, - PED_15_DATA_IN => PED_15_DATA_IN, + PED_1_DATA_IN => b"00" & x"0000", + PED_2_DATA_IN => b"00" & x"0000", + PED_3_DATA_IN => b"00" & x"0000", + PED_4_DATA_IN => b"00" & x"0000", + PED_5_DATA_IN => b"00" & x"0000", + PED_6_DATA_IN => b"00" & x"0000", + PED_7_DATA_IN => b"00" & x"0000", + PED_8_DATA_IN => b"00" & x"0000", + PED_9_DATA_IN => b"00" & x"0000", + PED_10_DATA_IN => b"00" & x"0000", + PED_11_DATA_IN => b"00" & x"0000", + PED_12_DATA_IN => b"00" & x"0000", + PED_13_DATA_IN => b"00" & x"0000", + PED_14_DATA_IN => b"00" & x"0000", + PED_15_DATA_IN => b"00" & x"0000", THR_ADDR_OUT => THR_ADDR_OUT, THR_0_DATA_IN => THR_0_DATA_IN, THR_1_DATA_IN => THR_1_DATA_IN, - THR_2_DATA_IN => THR_2_DATA_IN, - THR_3_DATA_IN => THR_3_DATA_IN, + THR_2_DATA_IN => b"00" & x"0000", + THR_3_DATA_IN => b"00" & x"0000", THR_4_DATA_IN => THR_4_DATA_IN, - THR_5_DATA_IN => THR_5_DATA_IN, - THR_6_DATA_IN => THR_6_DATA_IN, - THR_7_DATA_IN => THR_7_DATA_IN, - THR_8_DATA_IN => THR_8_DATA_IN, - THR_9_DATA_IN => THR_9_DATA_IN, - THR_10_DATA_IN => THR_10_DATA_IN, - THR_11_DATA_IN => THR_11_DATA_IN, - THR_12_DATA_IN => THR_12_DATA_IN, - THR_13_DATA_IN => THR_13_DATA_IN, - THR_14_DATA_IN => THR_14_DATA_IN, - THR_15_DATA_IN => THR_15_DATA_IN, + THR_5_DATA_IN => b"00" & x"0000", + THR_6_DATA_IN => b"00" & x"0000", + THR_7_DATA_IN => b"00" & x"0000", + THR_8_DATA_IN => b"00" & x"0000", + THR_9_DATA_IN => b"00" & x"0000", + THR_10_DATA_IN => b"00" & x"0000", + THR_11_DATA_IN => b"00" & x"0000", + THR_12_DATA_IN => b"00" & x"0000", + THR_13_DATA_IN => b"00" & x"0000", + THR_14_DATA_IN => b"00" & x"0000", + THR_15_DATA_IN => b"00" & x"0000", + FIFO_SPACE_REQ_OUT => FIFO_SPACE_REQ_OUT, FIFO_START_OUT => FIFO_START_OUT, - FIFO_0_DATA_OUT => FIFO_0_DATA_OUT, +-- FIFO_0_DATA_OUT => FIFO_0_DATA_OUT, + FIFO_0_DATA_OUT(39 downto 14) => ADC_0_STATUS_OUT, + FIFO_0_DATA_OUT(13 downto 0) => ADC_0_DATA_OUT, FIFO_1_DATA_OUT => FIFO_1_DATA_OUT, - FIFO_2_DATA_OUT => FIFO_2_DATA_OUT, - FIFO_3_DATA_OUT => FIFO_3_DATA_OUT, - FIFO_4_DATA_OUT => FIFO_4_DATA_OUT, - FIFO_5_DATA_OUT => FIFO_5_DATA_OUT, - FIFO_6_DATA_OUT => FIFO_6_DATA_OUT, - FIFO_7_DATA_OUT => FIFO_7_DATA_OUT, - FIFO_8_DATA_OUT => FIFO_8_DATA_OUT, - FIFO_9_DATA_OUT => FIFO_9_DATA_OUT, - FIFO_10_DATA_OUT => FIFO_10_DATA_OUT, - FIFO_11_DATA_OUT => FIFO_11_DATA_OUT, - FIFO_12_DATA_OUT => FIFO_12_DATA_OUT, - FIFO_13_DATA_OUT => FIFO_13_DATA_OUT, - FIFO_14_DATA_OUT => FIFO_14_DATA_OUT, - FIFO_15_DATA_OUT => FIFO_15_DATA_OUT, + FIFO_2_DATA_OUT => open, + FIFO_3_DATA_OUT => open, + FIFO_4_DATA_OUT => open, + FIFO_5_DATA_OUT => open, + FIFO_6_DATA_OUT => open, + FIFO_7_DATA_OUT => open, + FIFO_8_DATA_OUT => open, + FIFO_9_DATA_OUT => open, + FIFO_10_DATA_OUT => open, + FIFO_11_DATA_OUT => open, + FIFO_12_DATA_OUT => open, + FIFO_13_DATA_OUT => open, + FIFO_14_DATA_OUT => open, + FIFO_15_DATA_OUT => open, FIFO_WE_OUT => FIFO_WE_OUT, FIFO_DONE_OUT => FIFO_DONE_OUT, DBG_BSM_OUT => DBG_BSM_OUT, @@ -298,96 +251,28 @@ TESTBENCH: process begin -- Setup signal reset_in <= '0'; + dhdr_buf_full_in <= '0'; eds_data_in <= (others => '0'); eds_avail_in <= '0'; - evt_type_in <= "000"; buf_start_in <= (others => '0'); buf_tick_in <= (others => '0'); -- Buffer level information: 7 -> good, 6 -> broken, 5 -> ignore, rest LEVEL buf_0_data_in(37 downto 30) <= x"80"; -- good buf_1_data_in(37 downto 30) <= x"20"; -- ignore - buf_2_data_in(37 downto 30) <= x"20"; -- ignore - buf_3_data_in(37 downto 30) <= x"20"; -- ignore buf_4_data_in(37 downto 30) <= x"40"; -- broken!!! - buf_5_data_in(37 downto 30) <= x"20"; -- ignore - buf_6_data_in(37 downto 30) <= x"20"; -- ignore - buf_7_data_in(37 downto 30) <= x"20"; -- ignore - buf_8_data_in(37 downto 30) <= x"20"; -- ignore - buf_9_data_in(37 downto 30) <= x"20"; -- ignore - buf_10_data_in(37 downto 30) <= x"20"; -- ignore - buf_11_data_in(37 downto 30) <= x"20"; -- ignore - buf_12_data_in(37 downto 30) <= x"20"; -- ignore - buf_13_data_in(37 downto 30) <= x"20"; -- ignore - buf_14_data_in(37 downto 30) <= x"20"; -- ignore - buf_15_data_in(37 downto 30) <= x"20"; -- ignore -- Buffer frame information: 8 -> APV error, [7:0] row buf_0_data_in(29 downto 18) <= x"011"; -- row 0x11, no error buf_1_data_in(29 downto 18) <= x"0ee"; -- - buf_2_data_in(29 downto 18) <= x"0ee"; -- - buf_3_data_in(29 downto 18) <= x"0ee"; -- buf_4_data_in(29 downto 18) <= x"0aa"; -- - buf_5_data_in(29 downto 18) <= x"0ee"; -- - buf_6_data_in(29 downto 18) <= x"0ee"; -- - buf_7_data_in(29 downto 18) <= x"0ee"; -- - buf_8_data_in(29 downto 18) <= x"0ee"; -- - buf_9_data_in(29 downto 18) <= x"0ee"; -- - buf_10_data_in(29 downto 18) <= x"0ee"; -- - buf_11_data_in(29 downto 18) <= x"0ee"; -- - buf_12_data_in(29 downto 18) <= x"0ee"; -- - buf_13_data_in(29 downto 18) <= x"0ee"; -- - buf_14_data_in(29 downto 18) <= x"0ee"; -- - buf_15_data_in(29 downto 18) <= x"0ee"; -- -- Buffer data buf_0_data_in(17 downto 14) <= x"0"; buf_1_data_in(17 downto 14) <= x"0"; buf_1_data_in(13 downto 0) <= "00000000000000"; - buf_2_data_in(17 downto 14) <= x"0"; buf_2_data_in(13 downto 0) <= "00000000000000"; - buf_3_data_in(17 downto 14) <= x"0"; buf_3_data_in(13 downto 0) <= "00000000000000"; buf_4_data_in(17 downto 14) <= x"0"; buf_4_data_in(13 downto 0) <= "00000000000000"; - buf_5_data_in(17 downto 14) <= x"0"; buf_5_data_in(13 downto 0) <= "00000000000000"; - buf_6_data_in(17 downto 14) <= x"0"; buf_6_data_in(13 downto 0) <= "00000000000000"; - buf_7_data_in(17 downto 14) <= x"0"; buf_7_data_in(13 downto 0) <= "00000000000000"; - buf_8_data_in(17 downto 14) <= x"0"; buf_8_data_in(13 downto 0) <= "00000000000000"; - buf_9_data_in(17 downto 14) <= x"0"; buf_9_data_in(13 downto 0) <= "00000000000000"; - buf_10_data_in(17 downto 14) <= x"0"; buf_10_data_in(13 downto 0) <= "00000000000000"; - buf_11_data_in(17 downto 14) <= x"0"; buf_11_data_in(13 downto 0) <= "00000000000000"; - buf_12_data_in(17 downto 14) <= x"0"; buf_12_data_in(13 downto 0) <= "00000000000000"; - buf_13_data_in(17 downto 14) <= x"0"; buf_13_data_in(13 downto 0) <= "00000000000000"; - buf_14_data_in(17 downto 14) <= x"0"; buf_14_data_in(13 downto 0) <= "00000000000000"; - buf_15_data_in(17 downto 14) <= x"0"; buf_15_data_in(13 downto 0) <= "00000000000000"; -- Pedestal data --- ped_0_data_in <= "00" & x"0000"; - ped_1_data_in <= "00" & x"0000"; - ped_2_data_in <= "00" & x"0000"; - ped_3_data_in <= "00" & x"0000"; - ped_4_data_in <= "00" & x"0000"; - ped_5_data_in <= "00" & x"0000"; - ped_6_data_in <= "00" & x"0000"; - ped_7_data_in <= "00" & x"0000"; - ped_8_data_in <= "00" & x"0000"; - ped_9_data_in <= "00" & x"0000"; - ped_10_data_in <= "00" & x"0000"; - ped_11_data_in <= "00" & x"0000"; - ped_12_data_in <= "00" & x"0000"; - ped_13_data_in <= "00" & x"0000"; - ped_14_data_in <= "00" & x"0000"; - ped_15_data_in <= "00" & x"0000"; -- Threshold data -- thr_0_data_in <= "00" & x"0000"; thr_1_data_in <= "00" & x"0000"; - thr_2_data_in <= "00" & x"0000"; - thr_3_data_in <= "00" & x"0000"; thr_4_data_in <= "00" & x"0000"; - thr_5_data_in <= "00" & x"0000"; - thr_6_data_in <= "00" & x"0000"; - thr_7_data_in <= "00" & x"0000"; - thr_8_data_in <= "00" & x"0000"; - thr_9_data_in <= "00" & x"0000"; - thr_10_data_in <= "00" & x"0000"; - thr_11_data_in <= "00" & x"0000"; - thr_12_data_in <= "00" & x"0000"; - thr_13_data_in <= "00" & x"0000"; - thr_14_data_in <= "00" & x"0000"; - thr_15_data_in <= "00" & x"0000"; -- Reset wait until rising_edge(clk_in); @@ -398,17 +283,14 @@ begin reset_in <= '0'; wait until rising_edge(clk_in); - ---------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------- + + -- Tests may start now ---------------------------------------------------------------- -- "000" -> RAW128 ---------------------------------------------------------------- wait until rising_edge(clk_in); reset_in <= '1'; - evt_type_in <= "000"; wait until rising_edge(clk_in); reset_in <= '0'; wait until rising_edge(clk_in); @@ -416,7 +298,7 @@ begin wait until rising_edge(clk_in); -- EDS comes in - eds_data_in <= x"01abcdee01"; + eds_data_in <= x"01abcdee00"; wait until rising_edge(clk_in); eds_avail_in <= '1'; wait until rising_edge(clk_in); @@ -432,132 +314,17 @@ begin wait until rising_edge(clk_in); wait until rising_edge(clk_in); buf_0_data_in(37 downto 30) <= x"81"; - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - buf_0_data_in(37 downto 30) <= x"82"; - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - buf_0_data_in(37 downto 30) <= x"83"; -- wait for first buffer wait until rising_edge(buf_done_out); - wait for 300 ns; + wait for 600 ns; wait until rising_edge(clk_in); - ---------------------------------------------------------------- -- "001" -> PED128 ---------------------------------------------------------------- wait until rising_edge(clk_in); reset_in <= '1'; - evt_type_in <= "001"; - wait until rising_edge(clk_in); - reset_in <= '0'; - wait until rising_edge(clk_in); - wait for 55 ns; - wait until rising_edge(clk_in); - - -- EDS comes in - eds_data_in <= x"01abcdee11"; - wait until rising_edge(clk_in); - eds_avail_in <= '1'; - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - eds_avail_in <= '0'; - wait until rising_edge(clk_in); - - -- Buffer 0 becomes ready - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - buf_0_data_in(37 downto 30) <= x"81"; - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - buf_0_data_in(37 downto 30) <= x"82"; - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - buf_0_data_in(37 downto 30) <= x"83"; - - -- wait for first buffer - wait until rising_edge(buf_done_out); - wait for 300 ns; - wait until rising_edge(clk_in); - - ---------------------------------------------------------------- - -- "010" -> PED128THR - ---------------------------------------------------------------- - wait until rising_edge(clk_in); - reset_in <= '1'; - evt_type_in <= "010"; - wait until rising_edge(clk_in); - reset_in <= '0'; - wait until rising_edge(clk_in); - wait for 55 ns; - wait until rising_edge(clk_in); - - -- EDS comes in - eds_data_in <= x"01abcdee21"; - wait until rising_edge(clk_in); - eds_avail_in <= '1'; - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - eds_avail_in <= '0'; - wait until rising_edge(clk_in); - - -- Buffer 0 becomes ready - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - buf_0_data_in(37 downto 30) <= x"81"; - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - buf_0_data_in(37 downto 30) <= x"82"; - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - wait until rising_edge(clk_in); - buf_0_data_in(37 downto 30) <= x"83"; - - -- wait for first buffer - wait until rising_edge(buf_done_out); - wait for 300 ns; - wait until rising_edge(clk_in); - - ---------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------- - ---------------------------------------------------------------------------------------- - wait; - - -- Tests may start now - ---------------------------------------------------------------- - -- "000" -> RAW128 - ---------------------------------------------------------------- - wait until rising_edge(clk_in); - reset_in <= '1'; - evt_type_in <= "000"; wait until rising_edge(clk_in); reset_in <= '0'; wait until rising_edge(clk_in); @@ -584,15 +351,14 @@ begin -- wait for first buffer wait until rising_edge(buf_done_out); - wait for 300 ns; + wait for 600 ns; wait until rising_edge(clk_in); ---------------------------------------------------------------- - -- "001" -> PED128 + -- "010" -> PED128THR ---------------------------------------------------------------- wait until rising_edge(clk_in); reset_in <= '1'; - evt_type_in <= "001"; wait until rising_edge(clk_in); reset_in <= '0'; wait until rising_edge(clk_in); @@ -600,7 +366,7 @@ begin wait until rising_edge(clk_in); -- EDS comes in - eds_data_in <= x"01abcdee01"; + eds_data_in <= x"01abcdee02"; wait until rising_edge(clk_in); eds_avail_in <= '1'; wait until rising_edge(clk_in); @@ -619,15 +385,14 @@ begin -- wait for first buffer wait until rising_edge(buf_done_out); - wait for 300 ns; + wait for 600 ns; wait until rising_edge(clk_in); ---------------------------------------------------------------- - -- "010" -> PED128THR + -- "011" -> RAW64 ---------------------------------------------------------------- wait until rising_edge(clk_in); reset_in <= '1'; - evt_type_in <= "010"; wait until rising_edge(clk_in); reset_in <= '0'; wait until rising_edge(clk_in); @@ -635,7 +400,7 @@ begin wait until rising_edge(clk_in); -- EDS comes in - eds_data_in <= x"01abcdee01"; + eds_data_in <= x"01abcdee03"; wait until rising_edge(clk_in); eds_avail_in <= '1'; wait until rising_edge(clk_in); @@ -654,7 +419,7 @@ begin -- wait for first buffer wait until rising_edge(buf_done_out); - wait for 300 ns; + wait for 600 ns; wait until rising_edge(clk_in); ---------------------------------------------------------------- @@ -662,7 +427,6 @@ begin ---------------------------------------------------------------- wait until rising_edge(clk_in); reset_in <= '1'; - evt_type_in <= "100"; wait until rising_edge(clk_in); reset_in <= '0'; wait until rising_edge(clk_in); @@ -670,7 +434,7 @@ begin wait until rising_edge(clk_in); -- EDS comes in - eds_data_in <= x"01abcdee01"; + eds_data_in <= x"01abcdee04"; wait until rising_edge(clk_in); eds_avail_in <= '1'; wait until rising_edge(clk_in); @@ -689,7 +453,7 @@ begin -- wait for first buffer wait until rising_edge(buf_done_out); - wait for 300 ns; + wait for 600 ns; wait until rising_edge(clk_in); ---------------------------------------------------------------- @@ -697,7 +461,6 @@ begin ---------------------------------------------------------------- wait until rising_edge(clk_in); reset_in <= '1'; - evt_type_in <= "101"; wait until rising_edge(clk_in); reset_in <= '0'; wait until rising_edge(clk_in); @@ -705,7 +468,7 @@ begin wait until rising_edge(clk_in); -- EDS comes in - eds_data_in <= x"01abcdee01"; + eds_data_in <= x"01abcdee05"; wait until rising_edge(clk_in); eds_avail_in <= '1'; wait until rising_edge(clk_in); @@ -724,7 +487,7 @@ begin -- wait for first buffer wait until rising_edge(buf_done_out); - wait for 300 ns; + wait for 600 ns; wait until rising_edge(clk_in); ---------------------------------------------------------------- @@ -732,7 +495,6 @@ begin ---------------------------------------------------------------- wait until rising_edge(clk_in); reset_in <= '1'; - evt_type_in <= "110"; wait until rising_edge(clk_in); reset_in <= '0'; wait until rising_edge(clk_in); @@ -740,7 +502,7 @@ begin wait until rising_edge(clk_in); -- EDS comes in - eds_data_in <= x"01abcdee01"; + eds_data_in <= x"01abcdee06"; wait until rising_edge(clk_in); eds_avail_in <= '1'; wait until rising_edge(clk_in); @@ -759,7 +521,7 @@ begin -- wait for first buffer wait until rising_edge(buf_done_out); - wait for 300 ns; + wait for 600 ns; wait until rising_edge(clk_in); ---------------------------------------------------------------- @@ -767,7 +529,6 @@ begin ---------------------------------------------------------------- wait until rising_edge(clk_in); reset_in <= '1'; - evt_type_in <= "111"; wait until rising_edge(clk_in); reset_in <= '0'; wait until rising_edge(clk_in); @@ -775,7 +536,7 @@ begin wait until rising_edge(clk_in); -- EDS comes in - eds_data_in <= x"01abcdee01"; + eds_data_in <= x"01abcdee07"; wait until rising_edge(clk_in); eds_avail_in <= '1'; wait until rising_edge(clk_in); @@ -794,16 +555,12 @@ begin -- wait for first buffer wait until rising_edge(buf_done_out); - wait for 300 ns; + wait for 600 ns; wait until rising_edge(clk_in); - - - - - -- stay a while, stay forever! wait; + end process TESTBENCH; -- Data faker for "APV 0"... @@ -1100,7 +857,8 @@ BUF_0_THR_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then case thr_addr is - when "0000000" => thr_0_data_in <= "00" & x"001e"; +-- when "0000000" => thr_0_data_in <= "00" & x"001e"; + when "0000000" => thr_0_data_in <= "00" & x"ffff"; when "0000001" => thr_0_data_in <= "00" & x"100f"; when "0000010" => thr_0_data_in <= "00" & x"201e"; when "0000011" => thr_0_data_in <= "00" & x"300f"; diff --git a/src/tb_real_trg_handler.vhd b/src/tb_real_trg_handler.vhd index 3250152..2a8ab37 100644 --- a/src/tb_real_trg_handler.vhd +++ b/src/tb_real_trg_handler.vhd @@ -10,10 +10,10 @@ ARCHITECTURE behavior OF testbench IS COMPONENT real_trg_handler PORT( CLK_IN : IN std_logic; - CLEAR_IN : IN std_logic; RESET_IN : IN std_logic; TIME_TRG_IN : IN std_logic_vector(3 downto 0); TRB_TRG_IN : IN std_logic_vector(3 downto 0); + TRG_SETUP_IN : IN std_logic_vector(7 downto 0); APV_TRGDONE_IN : IN std_logic; TRG_3_TODO_IN : IN std_logic_vector(3 downto 0); TRG_2_TODO_IN : IN std_logic_vector(3 downto 0); @@ -22,9 +22,11 @@ ARCHITECTURE behavior OF testbench IS TRB_TTAG_IN : IN std_logic_vector(15 downto 0); TRB_TRND_IN : IN std_logic_vector(7 downto 0); TRB_TTYPE_IN : IN std_logic_vector(3 downto 0); + TRB_TINFO_IN : IN std_logic_vector(23 downto 0); TRB_TRGRCVD_IN : IN std_logic; BUSY_RELEASE_IN : IN std_logic; - TRB_MISMATCH_OUT : OUT std_logic; + LVL1_COUNTER_IN : IN std_logic_vector(15 downto 0); + LVL1_LD_COUNTER_IN : IN std_logic; LVL1_COUNTER_OUT : OUT std_logic_vector(15 downto 0); APV_TRGSEL_OUT : OUT std_logic_vector(3 downto 0); APV_TRGSTART_OUT : OUT std_logic; @@ -34,15 +36,15 @@ ARCHITECTURE behavior OF testbench IS EDS_READY_OUT : OUT std_logic; DBG_FRMCTR_OUT : OUT std_logic_vector(3 downto 0); BSM_OUT : OUT std_logic_vector(7 downto 0); - DEBUG_OUT : OUT std_logic_vector(15 downto 0) + DEBUG_OUT : OUT std_logic_vector(63 downto 0) ); END COMPONENT; SIGNAL CLK_IN : std_logic; - SIGNAL CLEAR_IN : std_logic; SIGNAL RESET_IN : std_logic; SIGNAL TIME_TRG_IN : std_logic_vector(3 downto 0); SIGNAL TRB_TRG_IN : std_logic_vector(3 downto 0); + SIGNAL TRG_SETUP_IN : std_logic_vector(7 downto 0); SIGNAL APV_TRGDONE_IN : std_logic; SIGNAL TRG_3_TODO_IN : std_logic_vector(3 downto 0); SIGNAL TRG_2_TODO_IN : std_logic_vector(3 downto 0); @@ -51,8 +53,10 @@ ARCHITECTURE behavior OF testbench IS SIGNAL TRB_TTAG_IN : std_logic_vector(15 downto 0); SIGNAL TRB_TRND_IN : std_logic_vector(7 downto 0); SIGNAL TRB_TTYPE_IN : std_logic_vector(3 downto 0); + SIGNAL TRB_TINFO_IN : std_logic_vector(23 downto 0); SIGNAL TRB_TRGRCVD_IN : std_logic; - SIGNAL TRB_MISMATCH_OUT : std_logic; + SIGNAL LVL1_COUNTER_IN : std_logic_vector(15 downto 0); + SIGNAL LVL1_LD_COUNTER_IN : std_logic; SIGNAL LVL1_COUNTER_OUT : std_logic_vector(15 downto 0); SIGNAL BUSY_RELEASE_IN : std_logic; SIGNAL APV_TRGSEL_OUT : std_logic_vector(3 downto 0); @@ -63,17 +67,17 @@ ARCHITECTURE behavior OF testbench IS SIGNAL EDS_READY_OUT : std_logic; SIGNAL DBG_FRMCTR_OUT : std_logic_vector(3 downto 0); SIGNAL BSM_OUT : std_logic_vector(7 downto 0); - SIGNAL DEBUG_OUT : std_logic_vector(15 downto 0); + SIGNAL DEBUG_OUT : std_logic_vector(63 downto 0); BEGIN -- Please check and add your generic clause manually uut: real_trg_handler PORT MAP( CLK_IN => CLK_IN, - CLEAR_IN => CLEAR_IN, RESET_IN => RESET_IN, TIME_TRG_IN => TIME_TRG_IN, TRB_TRG_IN => TRB_TRG_IN, + TRG_SETUP_IN => TRG_SETUP_IN, APV_TRGDONE_IN => APV_TRGDONE_IN, TRG_3_TODO_IN => TRG_3_TODO_IN, TRG_2_TODO_IN => TRG_2_TODO_IN, @@ -83,7 +87,9 @@ BEGIN TRB_TRND_IN => TRB_TRND_IN, TRB_TTYPE_IN => TRB_TTYPE_IN, TRB_TRGRCVD_IN => TRB_TRGRCVD_IN, - TRB_MISMATCH_OUT => TRB_MISMATCH_OUT, + TRB_TINFO_IN => TRB_TINFO_IN, + LVL1_COUNTER_IN => LVL1_COUNTER_IN, + LVL1_LD_COUNTER_IN => LVL1_LD_COUNTER_IN, LVL1_COUNTER_OUT => LVL1_COUNTER_OUT, BUSY_RELEASE_IN => BUSY_RELEASE_IN, APV_TRGSEL_OUT => APV_TRGSEL_OUT, @@ -106,23 +112,24 @@ end process THE_CLOCK_GEN; THE_TEST_BENCH: process begin -- Setup signals - clear_in <= '0'; reset_in <= '0'; time_trg_in <= x"0"; trb_trg_in <= x"0"; + trg_setup_in <= x"00"; apv_trgdone_in <= '0'; trg_3_todo_in <= x"0"; trg_2_todo_in <= x"3"; trg_1_todo_in <= x"2"; trg_0_todo_in <= x"1"; - trb_ttag_in <= x"dead"; - trb_trnd_in <= x"fc"; - trb_ttype_in <= x"1"; + trb_ttag_in <= x"0000"; + trb_trnd_in <= x"00"; + trb_ttype_in <= x"0"; + trb_tinfo_in <= x"00_00_00"; trb_trgrcvd_in <= '0'; busy_release_in <= '0'; + lvl1_counter_in <= x"affe"; + lvl1_ld_counter_in <= '0'; -- Reset all - clear_in <= '1'; wait for 50 ns; - clear_in <= '0'; wait for 50 ns; wait until rising_edge(clk_in); wait until rising_edge(clk_in); reset_in <= '1'; @@ -132,10 +139,79 @@ begin wait until rising_edge(clk_in); -- Tests may start here + -- Load the local counter with TRBnet value + wait until rising_edge(clk_in); + lvl1_ld_counter_in <= '1'; + wait until rising_edge(clk_in); + lvl1_ld_counter_in <= '0'; + wait until rising_edge(clk_in); + + wait for 200 ns; + + -- Check missing timing trigger + wait until rising_edge(clk_in); + trb_ttag_in <= x"affe"; + trb_trnd_in <= x"a0"; + trb_ttype_in <= x"1"; + trb_tinfo_in <= x"ff_00_00"; + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '1'; wait until rising_edge(clk_in); + + wait until rising_edge(eds_we_out); + + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + busy_release_in <= '1'; + + wait until rising_edge(eds_ready_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '0'; + busy_release_in <= '0'; wait until rising_edge(clk_in); + trb_ttag_in <= x"0000"; + trb_trnd_in <= x"00"; + trb_ttype_in <= x"0"; + trb_tinfo_in <= x"00_00_00"; wait until rising_edge(clk_in); + wait for 400 ns; + + -- Check timingtriggerless trigger + wait until rising_edge(clk_in); + trb_ttag_in <= x"afff"; + trb_trnd_in <= x"c7"; + trb_ttype_in <= x"9"; + trb_tinfo_in <= x"ff_00_80"; + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '1'; + wait until rising_edge(clk_in); + + wait until rising_edge(eds_we_out); + + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + busy_release_in <= '1'; + + wait until rising_edge(eds_ready_out); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + trb_trgrcvd_in <= '0'; + busy_release_in <= '0'; + wait until rising_edge(clk_in); + trb_ttag_in <= x"0000"; + trb_trnd_in <= x"00"; + trb_ttype_in <= x"0"; + trb_tinfo_in <= x"00_00_00"; + wait until rising_edge(clk_in); + + + wait; -- First sync trigger wait until rising_edge(clk_in); @@ -235,6 +311,8 @@ begin wait until rising_edge(clk_in); + + -- Stay a while, stay forever. wait; diff --git a/src/version.vhd b/src/version.vhd index 45d398a..00a8ada 100644 --- a/src/version.vhd +++ b/src/version.vhd @@ -8,7 +8,7 @@ use ieee.numeric_std.all; package version is - constant VERSION_NUMBER_TIME : std_logic_vector(31 downto 0) := CONV_STD_LOGIC_VECTOR(1264600226,32); + constant VERSION_NUMBER_TIME : std_logic_vector(31 downto 0) := CONV_STD_LOGIC_VECTOR(1272371189,32); end package version;