From: Tobias Weber <toweber86@gmail.com>
Date: Wed, 19 Dec 2018 15:06:44 +0000 (+0100)
Subject: adding header version and timestamp
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ccb6f0b0045321ae1fb231394851389ac39e94ce;p=trb3.git

adding header version and timestamp
---

diff --git a/mupix/Mupix8/sources/Datapath/ReadoutController.vhd b/mupix/Mupix8/sources/Datapath/ReadoutController.vhd
index ee09676..193b42a 100644
--- a/mupix/Mupix8/sources/Datapath/ReadoutController.vhd
+++ b/mupix/Mupix8/sources/Datapath/ReadoutController.vhd
@@ -42,6 +42,7 @@ architecture RTL of ReadoutController is
 
   constant c_frame_start : std_logic_vector(g_datawidth - 1 downto 0) := x"FABEABBA";
   constant c_frame_end   : std_logic_vector(g_datawidth - 1 downto 0) := x"BEEFBEEF";
+  constant c_version     : std_logic_vector(7 downto 0) := x"01";
 
   --readout state type, in mode 1, 2 a header and trailer will be put
   --at beginning and end of readout frame
@@ -50,13 +51,27 @@ architecture RTL of ReadoutController is
 
   signal wordcounter        : unsigned(g_addresswidth - 1 downto 0) := (others => '0');
   signal framecounter       : unsigned(31 downto 0)                 := (others => '0');
-  signal headercounter      : integer range 0 to 2                  := 0;
+  signal headercounter      : integer range 0 to 3                  := 0;
   signal trailercounter     : integer range 0 to 1                  := 0;
   signal triggerwaitcounter : unsigned(g_addresswidth - 1 downto 0) := (others => '0');
   signal almost_empty_edge  : std_logic_vector(1 downto 0)          := (others => '0');
 
+  signal timestamp_cnt, timestamp_reg      : unsigned(23 downto 0) := (others => '0');
+
 begin
 
+  timestamps : process(clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        timestamp_cnt <= (others => '0');
+      else
+        timestamp_cnt <= timestamp_cnt + 1;
+        timestamp_reg <= timestamp_cnt;
+      end if;
+    end if;
+  end process timestamps;
+
   edge_detection : process (clk) is
   begin
     if rising_edge(clk) then
@@ -124,6 +139,9 @@ begin
                 data_out      <= sensor_id;
                 headercounter <= 2;
               when 2 =>
+                data_out     <= c_version & std_logic_vector(timestamp_reg);
+                headercounter <= 3;
+              when 3 =>
                 data_out     <= std_logic_vector(framecounter);
                 framecounter <= framecounter + 1;
                 if mode = "01" then