From: Ingo Froehlich <ingo@nomail.fake>
Date: Wed, 8 May 2019 11:54:16 +0000 (+0200)
Subject: auto flash erase
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=cd48f80d117ece833254af773c2edbadcb00bc00;p=vhdlbasics.git

auto flash erase
---

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index 283e333..8ff6efa 100644
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -152,6 +152,7 @@ architecture arch of generic_flash_ctrl is
   
 
   type state_type is (IDLE, EnableFLASH1, EnableFLASH2, EnableFLASH3, Start, ReadPage, WritePage, WaitFlash1, WaitFlash2,
+                      EraseFLASH1, EraseFLASH2, EraseFLASH3,
                       ReadSPI0, ReadSPI1, ReadSPI2, ReadSPI3,
                       ReadRAM, ReadRAM0, WaitRAM1, WaitRAM2, WaitRAM3, WaitRAM4,
                       WaitRAM2_32, WaitRAM3_32, WaitRAM4_32, WaitRAM5_32, WaitRAM6_32, WriteSPI, DisableFLASH1, DisableFLASH2, DisableFLASH3);
@@ -164,6 +165,7 @@ architecture arch of generic_flash_ctrl is
   signal master_start_reg     : std_logic := '0';
   signal clean_master_start_reg : std_logic := '0';
   signal master_readback      : std_logic := '0';
+  signal master_erase         : std_logic := '0';
   signal master_DATA_OUT  : std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
   signal master_ADDR_OUT  : std_logic_vector(7 downto 0);
   signal master_WRITE_OUT : std_logic;
@@ -312,13 +314,15 @@ PROC_SELECTOR : process begin
       spi_ram_write_i <= '1';
       spi_ram_data_i  <= SPI_DATA_IN(7 downto 0);
       spi_ram_addr_i  <= SPI_ADDR_IN(3 downto 0);
+    elsif (SPI_ADDR_IN(7 downto 0) = x"5B") then
+      master_start_reg <= SPI_DATA_IN(0);
+      master_readback  <= SPI_DATA_IN(1);
+      master_erase     <= SPI_DATA_IN(2);
+      readback_num     <= SPI_DATA_IN(7 downto 4);
+      readback_reg     <= SPI_DATA_IN(15 downto 8);
     elsif (SPI_ADDR_IN(7 downto 0) = x"5C") then
       reg_LOC_WRITE_OUT <= '0';
       enable_cfg_flash <= SPI_DATA_IN(0);
-      master_readback  <= SPI_DATA_IN(2);  --new
-      master_start_reg <= SPI_DATA_IN(3);  --changed
-      readback_num     <= SPI_DATA_IN(7 downto 4);
-      readback_reg     <= SPI_DATA_IN(15 downto 8);
       --flash_mode       <= SPI_DATA_IN(8);  --XXX
     elsif (SPI_ADDR_IN(7 downto 0) = x"5d") then
       reg_LOC_WRITE_OUT <= '0';
@@ -451,11 +455,16 @@ PROC_SELECTOR : process begin
       reg_SPI_READY_OUT <= '1';
       reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');
       reg_SPI_DATA_OUT(2 downto 0) <= flash_command_register;
+    elsif (SPI_ADDR_IN(7 downto 0) = x"5B") then
+      reg_LOC_READ_OUT  <= '0';
+      reg_SPI_READY_OUT <= '1';
+      reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');
+      reg_SPI_DATA_OUT(15 downto 0) <= readback_reg & readback_num & master_running & master_erase & master_readback & master_start_reg;
     elsif (SPI_ADDR_IN(7 downto 0) = x"5C") then
       reg_LOC_READ_OUT  <= '0';
       reg_SPI_READY_OUT <= '1';
       reg_SPI_DATA_OUT(DATA_BUS_WIDTH-1 downto 0) <= (others => '0');
-      reg_SPI_DATA_OUT(15 downto 0) <= x"0" & "000" & flash_mode & '0' & auto_reset & master_running & master_start_reg & '0' & flash_busy & flash_err & enable_cfg_flash;
+      reg_SPI_DATA_OUT(15 downto 0) <= x"0" & "000" & flash_mode & '0' & auto_reset & "00" & '0' & flash_busy & flash_err & enable_cfg_flash;
     elsif (SPI_ADDR_IN(7 downto 0) = x"5d") then
       reg_LOC_READ_OUT  <= '0';
       reg_SPI_READY_OUT <= '1';
@@ -505,7 +514,8 @@ begin
         master_running <= '0';
         --if ((master_start_reg = '1' or auto_reset = '1') and (flash_mode = '0')) then
         if ((master_start_reg = '1' or auto_reset = '1') and (flash_mode = '1')) then
-          state <= Start;
+          --state <= Start;
+          --state <= EnableFLASH1;
           clean_master_start_reg <= '1';
           master_DATA_OUT <= (others => '0');
           master_ADDR_OUT <= x"00";
@@ -519,9 +529,13 @@ begin
               master_flash_go <= '1';
             end if;
           else
-            master_flash_command <= "000";
+            --master_flash_command <= "000";
+            state <= EnableFLASH1;
+            master_flash_command <= "100";
+            master_flash_go <= '1';
           end if;
         end if;
+        
       when EnableFLASH1 =>
         auto_dbg <= '1';
         state <= EnableFLASH2;
@@ -532,7 +546,24 @@ begin
         if (flash_busy = '0' and master_flash_go = '0') then
            state <= Start;
            master_flash_command <= "000";
-        end if;                    
+           if master_erase = '1' then
+             state <= EraseFlash1;
+             master_flash_command <= "111";
+             master_flash_go <= '1';
+           end if;
+        end if;
+
+      when EraseFlash1 =>
+        state <= EraseFlash2;
+      when EraseFlash2 =>
+        state <= EraseFlash3;
+      when EraseFlash3 =>
+        state <= EraseFlash3;
+        if (flash_busy = '0' and master_flash_go = '0') then
+          state <= Start;
+          master_flash_command <= "000";
+        end if;
+        
       when Start =>
         --master_flash_page   <= MASTER_STARTPAGE;
         master_flash_page   <= (others => '0');