From: Cahit Date: Fri, 8 May 2015 12:12:30 +0000 (+0200) Subject: brought 4-conn-addon (padiwa) project up-to-date X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=cd9ffaf3066799e85852e4727ca289ff938506d0;p=trb3.git brought 4-conn-addon (padiwa) project up-to-date --- diff --git a/base/trb3_periph_padiwa.lpf b/base/trb3_periph_padiwa.lpf index 212e83b..fba1f2a 100644 --- a/base/trb3_periph_padiwa.lpf +++ b/base/trb3_periph_padiwa.lpf @@ -12,8 +12,8 @@ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; -MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT_c" 1 X ; -MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT_c" TO CLKNET "clk_100_internal_c" 2 X ; +MULTICYCLE FROM CLKNET "clk_100_internal" TO CLKNET "CLK_PCLK_LEFT" 2 X ; +MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal" 2 X ; LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; diff --git a/wasa/config.vhd b/wasa/config.vhd index 0bef662..171c07d 100644 --- a/wasa/config.vhd +++ b/wasa/config.vhd @@ -12,8 +12,8 @@ package config is --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 49; -- number of tdc channels per module - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, diff --git a/wasa/currentRelease b/wasa/currentRelease index 02a0ff9..b10de14 120000 --- a/wasa/currentRelease +++ b/wasa/currentRelease @@ -1 +1 @@ -../tdc_releases/tdc_v2.1.1 \ No newline at end of file +../../tdc/releases/tdc_v2.1.2 \ No newline at end of file diff --git a/wasa/tdc_release b/wasa/tdc_release index 02a0ff9..b10de14 120000 --- a/wasa/tdc_release +++ b/wasa/tdc_release @@ -1 +1 @@ -../tdc_releases/tdc_v2.1.1 \ No newline at end of file +../../tdc/releases/tdc_v2.1.2 \ No newline at end of file diff --git a/wasa/unimportant_lines_constraints.lpf b/wasa/unimportant_lines_constraints.lpf index 0c65598..b9b6e80 100644 --- a/wasa/unimportant_lines_constraints.lpf +++ b/wasa/unimportant_lines_constraints.lpf @@ -1,4 +1,4 @@ -# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; -# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x; +MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x; +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x; -# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x; +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_internal TO CLKNET clk_100_internal 5x;