From: Thomas Gessler Date: Wed, 8 Jul 2020 14:13:03 +0000 (+0200) Subject: Add Kintex UltraScale FIFOs and GTH for CBM CRI X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=cfbb60cce87c5b2c4f8fe35480b19915ddb9c81e;p=trbnet.git Add Kintex UltraScale FIFOs and GTH for CBM CRI Migrated from the CBM RICH CRI test repo: git.cbm.gsi.de/rich/rich_cri Original code by: Adrian Weber --- diff --git a/media_interfaces/med_xcku_sfp_sync.vhd b/media_interfaces/med_xcku_sfp_sync.vhd new file mode 100644 index 0000000..091c952 --- /dev/null +++ b/media_interfaces/med_xcku_sfp_sync.vhd @@ -0,0 +1,275 @@ +--Media interface for Xilinx Kintex UltraScale + + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.config.all; +use work.trb_net_components.all; +use work.med_sync_define.all; + +entity med_xcku_sfp_sync is + generic( + SERDES_NUM : integer range 0 to 3 := 0; + IS_SYNC_SLAVE : integer := c_YES --select slave mode + ); + port( + CLK_REF_FULL : in std_logic; -- 200 MHz reference clock + CLK_INTERNAL_FULL : in std_logic; -- internal 200 MHz, always on + SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + TX_USRCLK : out std_logic; + FREECLK : in std_logic; + --Internal Connection TX + MEDIA_MED2INT : out MED2INT; + MEDIA_INT2MED : in INT2MED; + + --Sync operation + RX_DLM : out std_logic := '0'; + RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; + TX_DLM : in std_logic := '0'; + TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00"; + + --SFP Connection + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable + SD_REFCLK : in std_logic; + SD_RX_N : in std_logic; + SD_RX_P : in std_logic; + SD_TX_N : out std_logic; + SD_TX_P : out std_logic; + --Control Interface + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + + -- Status and control port + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') + ); +end entity; + + +architecture med_xcku_sfp_sync_arch of med_xcku_sfp_sync is + + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of med_xcku_sfp_sync_arch : architecture is "media_interface_group"; + attribute syn_sharing : string; + attribute syn_sharing of med_xcku_sfp_sync_arch : architecture is "off"; + attribute syn_hier : string; + attribute syn_hier of med_xcku_sfp_sync_arch : architecture is "hard"; + +-- signal clk_200_i : std_logic; +signal clk_200_ref : std_logic; +signal clk_rx_full : std_logic; +signal clk_tx_full : std_logic; + +signal tx_data : std_logic_vector(7 downto 0); +signal tx_k : std_logic; +signal rx_data : std_logic_vector(7 downto 0); +signal rx_k : std_logic; +signal rx_error : std_logic; + +signal rst_n : std_logic; +signal rx_serdes_rst : std_logic; +signal tx_serdes_rst : std_logic; +signal tx_pcs_rst : std_logic; +signal rx_pcs_rst : std_logic; +signal rst_qd : std_logic; +signal serdes_rst_qd : std_logic; + +signal rx_los_low : std_logic; +signal lsm_status : std_logic; +signal rx_cdr_lol : std_logic; +signal tx_pll_lol : std_logic; + +signal sci_ch_i : std_logic_vector(4 downto 0); +signal sci_addr_i : std_logic_vector(5 downto 0); +signal sci_data_in_i : std_logic_vector(7 downto 0); +signal sci_data_out_i : std_logic_vector(7 downto 0); +signal sci_read_i : std_logic; +signal sci_write_i : std_logic; + +signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; +signal wa_position_sel : std_logic_vector(3 downto 0); + +signal stat_rx_control_i : std_logic_vector(31 downto 0); +signal stat_tx_control_i : std_logic_vector(31 downto 0); +signal debug_rx_control_i : std_logic_vector(31 downto 0); +signal debug_tx_control_i : std_logic_vector(31 downto 0); +signal stat_fsm_reset_i : std_logic_vector(31 downto 0); +signal debug_med_sync_control_i : std_logic_vector(31 downto 0); + +signal stat_med : std_logic_vector(31 downto 0); + +signal reset_rx_pll_dp : std_logic := '0'; +signal reset_all : std_logic := '0'; +signal reset_clk_freerun : std_logic := '0'; +signal reset_tx_pll_dp : std_logic := '0'; +signal reset_tx_dp : std_logic := '0'; +signal reset_rx_dp : std_logic := '0'; +signal reset_rx_cdr : std_logic; +signal reset_tx_done : std_logic; +signal reset_rx_done : std_logic; +signal gtrefClk : std_logic; + +signal gtpowergood_i : std_logic; +signal tx_ready_i : std_logic; +signal rx_ready_i : std_logic; +signal tx_active_i : std_logic; +signal rx_active_i : std_logic; +signal rx_cdr_stable_i : std_logic; + +signal init_done_i : std_logic; + +begin + +clk_200_ref <= CLK_REF_FULL; + +SD_TXDIS_OUT <= not rx_ready_i when IS_SYNC_SLAVE = 1 else '0'; --slave only switches on when RX is ready +-- SD_TXDIS_OUT <= RESET; + +-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate +-- clk_200_i <= clk_rx_full; +-- end generate; +-- +-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate +-- clk_200_i <= clk_200_internal; +-- end generate; + + +------------------------------------------------- +-- Serdes +------------------------------------------------- +gen_pcs0 : if SERDES_NUM = 0 generate + +THE_GTH_8b10b : entity work.gth_8b10b + port map( + clk_100 => SYSCLK, + clk_200 => CLK_INTERNAL_FULL, + reset_all => RESET, + mgtrefclk0_x0y3_int => SD_REFCLK, + FREECLK => FREECLK, + + ch0_gthrxn_in => SD_RX_N, + ch0_gthrxp_in => SD_RX_P, + ch0_gthtxn_out => SD_TX_N, + ch0_gthtxp_out => SD_TX_P, + + tx_clk => clk_tx_full, + tx_data => tx_data, + tx_k => tx_k, + + rx_clk => clk_rx_full, + rx_data => rx_data, --clk with 200MHz osci + rx_k => rx_k, + + rx_cdr_stable => rx_cdr_stable_i, + tx_pll_reset => '0',--reset_tx_pll_and_datapath_i, + rx_pll_reset => '0',--reset_rx_pll_and_datapath_i, + + tx_ready => tx_ready_i, + rx_ready => rx_ready_i, + + tx_active => tx_active_i, + rx_active => rx_active_i, + gtpowergood => gtpowergood_i, + + init_done => init_done_i, + TX_USRCLK => TX_USRCLK + ); + +end generate; + + tx_serdes_rst <= '0'; --SD_LOS_IN; --no function + serdes_rst_qd <= '0'; --included in rst_qd + wa_position_sel <= x"0"; +-- wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0 +-- else wa_position(15 downto 12) when SERDES_NUM = 3; + +THE_MED_CONTROL : entity work.med_sync_control + generic map( + IS_SYNC_SLAVE => IS_SYNC_SLAVE, + IS_TX_RESET => 1 + ) + port map( + CLK_SYS => SYSCLK, + CLK_RXI => clk_rx_full, --clk_rx_full, + CLK_RXHALF => '0', + CLK_TXI => clk_tx_full, --clk_200_ref, --clk_200_internal, --clk_tx_full, JM150706 + CLK_REF => CLK_INTERNAL_FULL, + RESET => RESET, + CLEAR => CLEAR, + + INIT_DONE => init_done_i, + + TX_ACTIVE => tx_active_i, + RX_ACTIVE => rx_active_i, + + RX_SERDES_RST => open, + TX_SERDES_RST => open, + + MEDIA_MED2INT => MEDIA_MED2INT, + MEDIA_INT2MED => MEDIA_INT2MED, + + TX_DATA => tx_data, + TX_K => tx_k, + RX_DATA => rx_data, + RX_K => rx_k, + + TX_DLM_WORD => TX_DLM_WORD, + TX_DLM => TX_DLM, + RX_DLM_WORD => RX_DLM_WORD, + RX_DLM => RX_DLM, + + SERDES_RX_READY_IN => rx_ready_i, + SERDES_TX_READY_IN => tx_ready_i, + + STAT_TX_CONTROL => stat_tx_control_i, + STAT_RX_CONTROL => stat_rx_control_i, + DEBUG_TX_CONTROL => debug_tx_control_i, + DEBUG_RX_CONTROL => debug_rx_control_i, + STAT_RESET => stat_fsm_reset_i, + DEBUG_OUT => debug_med_sync_control_i + ); + +THE_BUS : process begin + wait until rising_edge(SYSCLK); + BUS_TX.unknown <= '1'; + BUS_TX.ack <= '1'; +end process; + +-- STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0); +-- STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8); +-- STAT_DEBUG(7) <= '0'; +-- STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0); +-- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16); +-- STAT_DEBUG(31 downto 0) <= debug_rx_control_i(31 downto 0); + STAT_DEBUG(3 downto 0) <= debug_med_sync_control_i(3 downto 0); + STAT_DEBUG(7 downto 4) <= rx_los_low & lsm_status & rx_cdr_lol & tx_pll_lol; +-- STAT_DEBUG(9) <= CLK_REF_FULL; +-- STAT_DEBUG(10) <= clk_rx_full; +-- STAT_DEBUG(11) <= clk_tx_full; + + +stat_med(0) <= rst_qd; +stat_med(1) <= rx_pcs_rst; +stat_med(2) <= tx_pcs_rst; +stat_med(3) <= rx_serdes_rst; +stat_med(4) <= tx_pll_lol; +stat_med(5) <= rx_cdr_lol; +stat_med(6) <= rx_los_low; +stat_med(7) <= rx_ready_i; +stat_med(8) <= tx_ready_i; +stat_med(9) <= lsm_status; +stat_med(31 downto 10) <= (others => '0'); + + +end architecture; + diff --git a/media_interfaces/sync/med_sync_control_xcku.vhd b/media_interfaces/sync/med_sync_control_xcku.vhd new file mode 100644 index 0000000..369e852 --- /dev/null +++ b/media_interfaces/sync/med_sync_control_xcku.vhd @@ -0,0 +1,267 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.med_sync_define.all; + +entity med_sync_control is + generic( + IS_SYNC_SLAVE : integer := 1; + IS_TX_RESET : integer := 1 + ); + port( + CLK_SYS : in std_logic; + CLK_RXI : in std_logic; + CLK_RXHALF : in std_logic; + CLK_TXI : in std_logic; + CLK_REF : in std_logic; + RESET : in std_logic; + CLEAR : in std_logic; + + INIT_DONE : in std_logic; + + TX_ACTIVE : in std_logic; + RX_ACTIVE : in std_logic; + + RX_SERDES_RST : out std_logic; + TX_SERDES_RST : out std_logic; + + MEDIA_MED2INT : out MED2INT; + MEDIA_INT2MED : in INT2MED; + + TX_DATA : out std_logic_vector(7 downto 0); + TX_K : out std_logic; + TX_CD : out std_logic; + RX_DATA : in std_logic_vector(7 downto 0); + RX_K : in std_logic; + + TX_DLM_WORD : in std_logic_vector(7 downto 0); + TX_DLM : in std_logic; + RX_DLM_WORD : out std_logic_vector(7 downto 0); + RX_DLM : out std_logic; + + SERDES_RX_READY_IN : in std_logic := '1'; + SERDES_TX_READY_IN : in std_logic := '1'; + + STAT_TX_CONTROL : out std_logic_vector(31 downto 0); + STAT_RX_CONTROL : out std_logic_vector(31 downto 0); + DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0); + DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0); + STAT_RESET : out std_logic_vector(31 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + +architecture med_sync_control_arch of med_sync_control is + +signal rx_fsm_state : std_logic_vector(3 downto 0); +signal tx_fsm_state : std_logic_vector(3 downto 0); +signal wa_position_rx : std_logic_vector(3 downto 0); +signal start_timer : unsigned(21 downto 0) := (others => '0'); + +signal request_retr_i : std_logic; +signal start_retr_i : std_logic; +signal request_retr_position_i : std_logic_vector(7 downto 0); +signal start_retr_position_i : std_logic_vector(7 downto 0); +signal rx_dlm_i : std_logic; + +signal led_ok : std_logic; +signal led_dlm, last_led_dlm : std_logic; +signal led_rx, last_led_rx : std_logic; +signal led_tx, last_led_tx : std_logic; +signal timer : unsigned(20 downto 0); +signal sd_los_i : std_logic; + +signal rx_allow : std_logic; +signal tx_allow : std_logic; +signal got_link_ready_i : std_logic; +signal make_link_reset_i : std_logic; +signal send_link_reset_i : std_logic; +signal make_link_reset_real_i : std_logic := '0'; +signal make_link_reset_sys_i : std_logic := '0'; +signal send_link_reset_real_i : std_logic := '0'; +signal send_link_reset_sys_i : std_logic := '0'; + +signal reset_i, rst_n, rst_n_tx : std_logic; +signal media_med2int_i : MED2INT; +signal finished_reset_rx, finished_reset_rx_q : std_logic; +signal finished_reset_tx, finished_reset_tx_q : std_logic; +signal TX_DATA_i : std_logic_vector(7 downto 0); +signal TX_K_i : std_logic; + +attribute MARK_DEBUG : string; +attribute MARK_DEBUG of CLK_SYS : signal is "TRUE"; +attribute MARK_DEBUG of media_med2int_i : signal is "TRUE"; +attribute MARK_DEBUG of MEDIA_INT2MED : signal is "TRUE"; +attribute MARK_DEBUG of RX_DATA : signal is "TRUE"; +attribute KEEP : string; +attribute KEEP of CLK_SYS : signal is "TRUE"; +attribute KEEP of media_med2int_i : signal is "TRUE"; +attribute KEEP of MEDIA_INT2MED : signal is "TRUE"; +attribute KEEP of RX_DATA : signal is "TRUE"; + +begin + +media_med2int_i.clk_half <= CLK_RXHALF; +media_med2int_i.clk_full <= CLK_RXI; + +TX_DATA <= TX_DATA_i; +TX_K <= TX_K_i; + + +-- +finished_reset_tx <= INIT_DONE; +finished_reset_rx <= INIT_DONE; +reset_i <= RESET; + +------------------------------------------------- +-- TX Data +------------------------------------------------- +THE_TX : tx_control + port map( + CLK_200 => CLK_REF, + CLK_100 => CLK_SYS, + RESET_IN => reset_i, + + TX_DATA_IN => MEDIA_INT2MED.data, + TX_PACKET_NUMBER_IN => MEDIA_INT2MED.packet_num, + TX_WRITE_IN => MEDIA_INT2MED.dataready, + TX_READ_OUT => media_med2int_i.tx_read, + + TX_DATA_OUT => TX_DATA_i, + TX_K_OUT => TX_K_i, + TX_CD_OUT => TX_CD, + + REQUEST_RETRANSMIT_IN => request_retr_i, --TODO + REQUEST_POSITION_IN => request_retr_position_i, --TODO + + START_RETRANSMIT_IN => start_retr_i, --TODO + START_POSITION_IN => start_retr_position_i, --TODO + + SEND_DLM => TX_DLM, + SEND_DLM_WORD => TX_DLM_WORD, + + SEND_LINK_RESET_IN => MEDIA_INT2MED.ctrl_op(15), + TX_ALLOW_IN => TX_ACTIVE, + RX_ALLOW_IN => RX_ACTIVE, + + DEBUG_OUT => DEBUG_TX_CONTROL, + STAT_REG_OUT => STAT_TX_CONTROL + ); + + +------------------------------------------------- +-- RX Data +------------------------------------------------- +THE_RX_CONTROL : rx_control + port map( + CLK_200 => CLK_REF, --200MHz intern; used in fifo of 8b10b + CLK_100 => CLK_SYS, + RESET_IN => reset_i, + + RX_DATA_OUT => media_med2int_i.data, + RX_PACKET_NUMBER_OUT => media_med2int_i.packet_num, + RX_WRITE_OUT => media_med2int_i.dataready, +-- RX_READ_IN => '1', + + RX_DATA_IN => RX_DATA, + RX_K_IN => RX_K, + + REQUEST_RETRANSMIT_OUT => request_retr_i, + REQUEST_POSITION_OUT => request_retr_position_i, + + START_RETRANSMIT_OUT => start_retr_i, + START_POSITION_OUT => start_retr_position_i, + + --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM + RX_DLM => rx_dlm_i, + RX_DLM_WORD => RX_DLM_WORD, + + SEND_LINK_RESET_OUT => send_link_reset_i, + MAKE_RESET_OUT => make_link_reset_sys_i, + RX_ALLOW_IN => RX_ACTIVE, + RX_RESET_FINISHED => finished_reset_rx, + GOT_LINK_READY => got_link_ready_i, + + DEBUG_OUT => DEBUG_RX_CONTROL, + STAT_REG_OUT => STAT_RX_CONTROL + ); + +RX_DLM <= rx_dlm_i; +MEDIA_MED2INT <= media_med2int_i; + +------------------------------------------------- +-- Generate LED signals +------------------------------------------------- +led_ok <= TX_ACTIVE and RX_ACTIVE when rising_edge(CLK_SYS); +led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS); +-- led_tx <= '1' when DEBUG_TX_CONTROL(13 downto 10) = x"c" else '0'; -- +led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_i) and not timer(20) when rising_edge(CLK_SYS); +led_dlm <= (led_dlm or rx_dlm_i) and not timer(20) when rising_edge(CLK_SYS); +-- led_dlm <= '1' when DEBUG_RX_CONTROL(3 downto 0) = x"f" else '0'; + +ROC_TIMER : process begin + wait until rising_edge(CLK_SYS); + timer <= timer + 1 ; + if timer(20) = '1' then + timer <= (others => '0'); + last_led_rx <= led_rx ; + last_led_tx <= led_tx; + last_led_dlm <= led_dlm; + end if; +end process; + +------------------------------------------------- +-- Status signals +------------------------------------------------- + +STAT_RESET(3 downto 0) <= rx_fsm_state; +STAT_RESET(7 downto 4) <= tx_fsm_state; +STAT_RESET(8) <= TX_ACTIVE; +STAT_RESET(9) <= RX_ACTIVE; +STAT_RESET(15 downto 10) <= (others => '0'); +STAT_RESET(16) <= '0'; +STAT_RESET(17) <= '0'; +STAT_RESET(18) <= '0';--QUAD_RST; --RX_PCS_RST; +STAT_RESET(19) <= '0';--TX_PCS_RST; +STAT_RESET(20) <= '0'; +STAT_RESET(21) <= rst_n; +STAT_RESET(22) <= rst_n_tx; +STAT_RESET(30 downto 23) <= (others => '0'); +STAT_RESET(31) <= start_timer(start_timer'left); + + +gen_link_reset : if IS_SYNC_SLAVE = 1 generate + link_reset_send : signal_sync port map(RESET => '0',CLK0 => CLK_RXI,CLK1 => CLK_SYS, + D_IN(0) => send_link_reset_i, + D_OUT(0) => send_link_reset_sys_i); +end generate; + +make_link_reset_real_i <= make_link_reset_sys_i or sd_los_i when IS_SYNC_SLAVE = 1 + else '0'; +send_link_reset_real_i <= send_link_reset_sys_i when IS_SYNC_SLAVE = 1 + else '0'; + +sd_los_i <= '0';--SFP_LOS when rising_edge(CLK_SYS); + +media_med2int_i.stat_op(15) <= send_link_reset_real_i when rising_edge(CLK_SYS); +media_med2int_i.stat_op(14) <= '0'; +media_med2int_i.stat_op(13) <= make_link_reset_real_i when rising_edge(CLK_SYS); --make trbnet reset +media_med2int_i.stat_op(12) <= led_dlm when rising_edge(CLK_SYS); -- or last_led_dlm; +media_med2int_i.stat_op(11) <= led_tx; -- or last_led_tx; +media_med2int_i.stat_op(10) <= led_rx or last_led_rx; +media_med2int_i.stat_op(9) <= TX_ACTIVE; --led_ok +media_med2int_i.stat_op(8 downto 5) <= (others => '0'); +media_med2int_i.stat_op(4) <= RX_ACTIVE; +media_med2int_i.stat_op(3 downto 0) <= x"0" when RX_ACTIVE = '1' and TX_ACTIVE = '1' else x"7"; + +DEBUG_OUT(0) <= TX_ACTIVE; +DEBUG_OUT(1) <= RX_ACTIVE; +DEBUG_OUT(2) <= sd_los_i; +DEBUG_OUT(3) <= '0'; --DEBUG_RX_CONTROL(4); + +end architecture; diff --git a/media_interfaces/sync/rx_control_xcku.vhd b/media_interfaces/sync/rx_control_xcku.vhd new file mode 100644 index 0000000..94e0b90 --- /dev/null +++ b/media_interfaces/sync/rx_control_xcku.vhd @@ -0,0 +1,437 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.med_sync_define.all; + +entity rx_control is + generic( + IDLE_WORD_CKECK_LENGTH : unsigned(9 downto 0) := b"00_0110_0100"; --100 + RESET_WORD_CKECK_LENGTH : unsigned(9 downto 0) := b"00_0010_0000"; --32 + IS_SIMULATION : std_logic := '0' + ); + port( + CLK_200 : in std_logic; + CLK_100 : in std_logic; + RESET_IN : in std_logic; + +--clk_sys signals + RX_DATA_OUT : out std_logic_vector(15 downto 0); + RX_PACKET_NUMBER_OUT : out std_logic_vector(2 downto 0); + RX_WRITE_OUT : out std_logic; + +-- clk_rx signals + RX_DATA_IN : in std_logic_vector( 7 downto 0); + RX_K_IN : in std_logic; + + REQUEST_RETRANSMIT_OUT : out std_logic := '0'; + REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0) := (others => '0'); + + START_RETRANSMIT_OUT : out std_logic := '0'; + START_POSITION_OUT : out std_logic_vector( 7 downto 0) := (others => '0'); + + --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM + RX_DLM : out std_logic := '0'; + RX_DLM_WORD : out std_logic_vector( 7 downto 0) := (others => '0'); + +--other signals + SEND_LINK_RESET_OUT : out std_logic := '0'; --clk_rx + MAKE_RESET_OUT : out std_logic := '0'; --clk_rx + RX_ALLOW_IN : in std_logic := '0'; --clk_sys + RX_RESET_FINISHED : in std_logic := '0'; --clk_rx + GOT_LINK_READY : out std_logic := '0'; --clk_rx + + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + +architecture rx_control_arch of rx_control is + +signal reset_i : std_logic; +type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, MAKE_RESET, START_RETR); +signal rx_state : rx_state_t; +signal rx_state_bits : std_logic_vector(3 downto 0); +signal rx_packet_num : std_logic_vector(2 downto 0); +signal buf_rx_write_out : std_logic := '0'; + +signal rx_data : std_logic_vector(17 downto 0); +signal ct_fifo_write : std_logic := '0'; +signal ct_fifo_read : std_logic := '0'; +signal ct_fifo_reset : std_logic := '0'; +signal ct_fifo_data_out : std_logic_vector(17 downto 0); +signal ct_fifo_empty : std_logic; +signal ct_fifo_full : std_logic; +signal ct_fifo_afull : std_logic; +signal last_ct_fifo_empty : std_logic; +signal last_ct_fifo_read : std_logic; + +signal idle_hist_i : std_logic_vector(3 downto 0) := x"0"; +signal got_link_ready_i : std_logic := '0'; +signal start_retr_i : std_logic; +signal start_retr_pos_i : std_logic_vector(7 downto 0); +signal rx_dlm_i : std_logic; +signal rx_dlm_word_i : std_logic_vector(7 downto 0); + +signal send_link_reset_i : std_logic; +signal make_reset_i : std_logic; +signal next_sop : std_logic; + +signal reg_rx_data_in : std_logic_vector(7 downto 0); +signal reg_rx_k_in : std_logic; + +signal reset_cnt : unsigned(11 downto 0); + +signal byte_align : std_logic := '0'; +signal last_reg_k_in : std_logic; +signal last_reg_rx_data_in : std_logic_vector(7 downto 0); +signal idle_wrd_cnt : unsigned(9 downto 0); + +signal last_rx_data : std_logic_vector(7 downto 0); +signal tn_reset_wrd_cnt : unsigned(9 downto 0); +signal make_reset_trbnet_i : std_logic; +signal make_reset_trbnet_sync : std_logic; +signal last_make_reset_trbnet_i : std_logic; +signal trbnetReset, trbnetReset_long : std_logic; + +attribute MARK_DEBUG : string; +attribute MARK_DEBUG of CLK_200 : signal is "TRUE"; +attribute MARK_DEBUG of ct_fifo_write : signal is "TRUE"; +attribute MARK_DEBUG of rx_data : signal is "TRUE"; +attribute MARK_DEBUG of rx_state_bits : signal is "TRUE"; +attribute MARK_DEBUG of reg_rx_data_in : signal is "TRUE"; +attribute MARK_DEBUG of reg_rx_k_in : signal is "TRUE"; +attribute MARK_DEBUG of reset_i : signal is "TRUE"; +attribute MARK_DEBUG of rx_packet_num : signal is "TRUE"; +attribute MARK_DEBUG of trbnetReset : signal is "TRUE"; +attribute MARK_DEBUG of make_reset_trbnet_i : signal is "TRUE"; +attribute MARK_DEBUG of tn_reset_wrd_cnt : signal is "TRUE"; +attribute KEEP : string; +attribute KEEP of CLK_200 : signal is "TRUE"; +attribute KEEP of ct_fifo_write : signal is "TRUE"; +attribute KEEP of rx_data : signal is "TRUE"; +attribute KEEP of rx_state_bits : signal is "TRUE"; +attribute KEEP of reg_rx_data_in : signal is "TRUE"; +attribute KEEP of reg_rx_k_in : signal is "TRUE"; +attribute KEEP of reset_i : signal is "TRUE"; +attribute KEEP of rx_packet_num : signal is "TRUE"; +attribute KEEP of trbnetReset : signal is "TRUE"; +attribute KEEP of make_reset_trbnet_i : signal is "TRUE"; +attribute KEEP of tn_reset_wrd_cnt : signal is "TRUE"; + +begin + +---------------------------------------------------------------------- +-- Data to Endpoint +---------------------------------------------------------------------- +reset_i <= RESET_IN; + +ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty; -- when rising_edge(CLK_100); +buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty when rising_edge(CLK_100); + +RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ; +RX_WRITE_OUT <= buf_rx_write_out; +RX_PACKET_NUMBER_OUT <= rx_packet_num; + +last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_100); +last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_100); + +process begin + wait until rising_edge(CLK_100); + if RX_ALLOW_IN = '0' then + rx_packet_num <= "100"; + elsif (byte_align = '1') then + rx_packet_num <= "100"; + elsif buf_rx_write_out = '1' then + if rx_packet_num = "100" then + rx_packet_num <= "000"; + else + rx_packet_num <= std_logic_vector(unsigned(rx_packet_num)+1); + end if; + end if; +end process; + +---------------------------------------------------------------------- +-- Clock Domain Transfer +---------------------------------------------------------------------- +THE_CT_FIFO : entity work.fifo_18x16_dualport_oreg + port map( + Data => rx_data, + WrClock => CLK_200, + RdClock => CLK_100, + WrEn => ct_fifo_write, + RdEn => ct_fifo_read, + Reset => ct_fifo_reset, + RPReset => ct_fifo_reset, + Q(17 downto 0) => ct_fifo_data_out, + Empty => ct_fifo_empty, + Full => ct_fifo_full, + AlmostFull => ct_fifo_afull + ); + +ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_200); + + +---------------------------------------------------------------------- +-- Read incoming data +---------------------------------------------------------------------- +PROC_RX_FSM : process begin + wait until rising_edge(CLK_200); + ct_fifo_write <= '0'; + start_retr_i <= '0'; + rx_dlm_i <= '0'; + idle_hist_i(3 downto 1) <= idle_hist_i(2 downto 0); + idle_hist_i(0) <= got_link_ready_i; + byte_align <= '0'; + --newly added + make_reset_i <= '0'; + + case rx_state is + when SLEEP => + rx_state_bits <= x"1"; + got_link_ready_i <= '0'; + make_reset_i <= '0'; + rx_data(7 downto 0) <= reg_rx_data_in; + if reg_rx_k_in = '1' and reg_rx_data_in = x"BC" then + rx_state <= WAIT_1; + end if; + + when WAIT_1 => + rx_state <= FIRST; + + when FIRST => + rx_state_bits <= x"2"; + rx_data(7 downto 0) <= reg_rx_data_in; + if byte_align = '0' then + if reg_rx_k_in = '1' then + case reg_rx_data_in is + when K_IDLE => + rx_state <= GET_IDLE; + when K_RST => + rx_state <= MAKE_RESET; + reset_cnt <= x"000"; + when K_DLM => + rx_state <= GET_DLM; + when K_REQ => + rx_state <= START_RETR; + when others => null; + end case; + else + rx_state <= GET_DATA; + end if; + end if; + + when GET_IDLE => + rx_state_bits <= x"3"; + rx_state <= FIRST; + next_sop <= '1'; + if reg_rx_k_in = '0' and reg_rx_data_in = D_IDLE1 then + idle_hist_i(0) <= '1'; + got_link_ready_i <= got_link_ready_i or (idle_hist_i(1) and idle_hist_i(3)); + elsif reg_rx_k_in = '1' then + rx_state <= FIRST; -- SLEEP; + end if; + + when GET_DATA => + rx_state_bits <= x"4"; + if reg_rx_k_in = '0' then + next_sop <= '0'; + rx_data(15 downto 8)<= reg_rx_data_in; + rx_data(16) <= next_sop; + rx_data(17) <= '0'; + ct_fifo_write <= '1'; + rx_state <= FIRST; + elsif reg_rx_k_in = '1' and reg_rx_data_in = K_IDLE then + --word is missaligned + byte_align <= '1'; + rx_state <= FIRST; + else + rx_state <= FIRST; -- SLEEP; + end if; + + when GET_DLM => + rx_state_bits <= x"5"; + rx_dlm_i <= '1'; + rx_dlm_word_i <= reg_rx_data_in; + rx_state <= FIRST; + + when START_RETR => + rx_state_bits <= x"6"; + start_retr_i <= '1'; + start_retr_pos_i <= reg_rx_data_in; + rx_state <= FIRST; + + when MAKE_RESET => + rx_state_bits <= x"F"; + if reg_rx_k_in = '1' and reg_rx_data_in = K_RST then + send_link_reset_i <= '1'; + make_reset_i <= '0'; + got_link_ready_i <= '0'; + if reset_cnt <= x"3ff" then + reset_cnt <= reset_cnt + 1; +-- else +-- make_reset_i <= '1'; + end if; + elsif reset_cnt > x"3ff" then -- or reset_cnt < x"40" + send_link_reset_i <= '0'; + make_reset_i <= '1'; + rx_state <= SLEEP; + else + if reset_cnt <= x"3ff" then + reset_cnt <= reset_cnt + 1; + end if; + send_link_reset_i <= '1'; + end if; + + end case; + + if reset_i = '1' or RX_RESET_FINISHED = '0' or (idle_wrd_cnt < IDLE_WORD_CKECK_LENGTH) then + rx_state <= SLEEP; + if rx_state = MAKE_RESET then + make_reset_i <= '1'; + else + make_reset_i <= '0'; + end if; + send_link_reset_i <= '0'; + end if; + + --fixing trbnetReset packetnumber misalignment + if trbnetReset_long = '1' then + rx_state <= SLEEP; + make_reset_i <= '1';--for debugging + end if; + +end process; + +-- link_reset_pulse : pulse_sync port map( CLK_A_IN => CLK_100, CLK_B_IN => CLK_200, RESET_A_IN => '0', +-- PULSE_A_IN => make_reset_trbnet_i, +-- PULSE_B_OUT => make_reset_trbnet_sync, RESET_B_IN => '0'); + + +THE_IDLE_PROC : process begin +wait until rising_edge(CLK_200); +-- Handles random data on RX line after reset. First right bc50 comes in, then random stuff, then again correct behavior. + last_reg_k_in <= reg_rx_k_in; + last_reg_rx_data_in <= reg_rx_data_in; + if reset_i = '1' then + idle_wrd_cnt <= (others=> '0'); + else + --check 50bc order + if idle_wrd_cnt < IDLE_WORD_CKECK_LENGTH then + + if (((reg_rx_k_in = '1') and (reg_rx_data_in = x"BC")) and ((last_reg_k_in = '0') and (last_reg_rx_data_in = x"50"))) then + idle_wrd_cnt <= idle_wrd_cnt + 1; + elsif (((reg_rx_k_in = '0') and (reg_rx_data_in = x"50")) and ((last_reg_k_in = '1') and (last_reg_rx_data_in = x"BC"))) then + idle_wrd_cnt <= idle_wrd_cnt + 1; + else + idle_wrd_cnt <= (others=> '0'); + end if; + + end if; + end if; +end process; + + +THE_TrbNet_RESET_PROC : process begin +wait until rising_edge(CLK_200); + last_rx_data <= reg_rx_data_in; + if reset_i = '1' then + tn_reset_wrd_cnt <= (others=> '0'); + make_reset_trbnet_i <= '0'; + else + --check 50bc order + if ((reg_rx_data_in = x"FE") and (last_rx_data = x"FE")) then + tn_reset_wrd_cnt <= tn_reset_wrd_cnt + 1; + else + tn_reset_wrd_cnt <= (others=> '0'); + end if; + + if (tn_reset_wrd_cnt >= RESET_WORD_CKECK_LENGTH) then --TODO: sync. Clocks + make_reset_trbnet_i <= '1'; + else + make_reset_trbnet_i <= '0'; + end if; + + last_make_reset_trbnet_i <= make_reset_trbnet_i; + trbnetReset <= '0'; + if make_reset_trbnet_i = '0' and last_make_reset_trbnet_i = '1'then --end of x"FEFE" chain + --make_reset_i <= '0';--for debugging + trbnetReset <= '1'; + end if; + end if; +end process; + +THE_TrbNet_RESET_PROC_strobe : process + variable loc_cnt : unsigned(3 downto 0); +begin +wait until rising_edge(CLK_200); + trbnetReset_long <= '0'; + if loc_cnt > 0 then + loc_cnt := loc_cnt + 1; + trbnetReset_long <= '1'; + end if; + + if trbnetReset = '1' then + loc_cnt := x"1"; + end if; + +end process; + +reg_rx_data_in <= RX_DATA_IN when rising_edge(CLK_200); +reg_rx_k_in <= RX_K_IN when rising_edge(CLK_200); + + +---------------------------------------------------------------------- +-- Signals out +---------------------------------------------------------------------- +GOT_LINK_READY <= got_link_ready_i; + +START_RETRANSMIT_OUT <= start_retr_i when rising_edge(CLK_200); +START_POSITION_OUT <= start_retr_pos_i when rising_edge(CLK_200); + +RX_DLM <= rx_dlm_i when rising_edge(CLK_200); +RX_DLM_WORD <= rx_dlm_word_i when rising_edge(CLK_200); + +REQUEST_RETRANSMIT_OUT <= '0'; --TODO: check incoming data +REQUEST_POSITION_OUT <= x"00"; --TODO: check incoming data + +SEND_LINK_RESET_OUT <= send_link_reset_i when rising_edge(CLK_200); +MAKE_RESET_OUT <= make_reset_i when rising_edge(CLK_200); + + +---------------------------------------------------------------------- +-- Debug and Status +---------------------------------------------------------------------- +STAT_REG_OUT(3 downto 0) <= rx_state_bits; +STAT_REG_OUT(4) <= got_link_ready_i; +STAT_REG_OUT(5) <= ct_fifo_afull; +STAT_REG_OUT(6) <= ct_fifo_empty; +STAT_REG_OUT(7) <= ct_fifo_write; +STAT_REG_OUT(15 downto 8) <= reg_rx_data_in when rising_edge(clk_100); --rx_data(7 downto 0); +STAT_REG_OUT(16) <= rx_data(16); +STAT_REG_OUT(17) <= '0'; +STAT_REG_OUT(31 downto 18) <= (others => '0'); + + +DEBUG_OUT(3 downto 0) <= rx_state_bits; +DEBUG_OUT(4) <= got_link_ready_i; +DEBUG_OUT(5) <= ct_fifo_afull; +DEBUG_OUT(6) <= ct_fifo_empty; +DEBUG_OUT(7) <= ct_fifo_write; +DEBUG_OUT(15 downto 8) <= rx_data(7 downto 0); +DEBUG_OUT(16) <= reg_rx_k_in; +DEBUG_OUT(17) <= make_reset_i; +DEBUG_OUT(18) <= send_link_reset_i; +DEBUG_OUT(19) <= '1' when rx_state_bits = x"f" else '0'; +--DEBUG_OUT(16) <= rx_data(16); +DEBUG_OUT(31 downto 20) <= (others => '0'); +-- DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0); +-- DEBUG_OUT(31 downto 24) <= ct_fifo_data_out(7 downto 0); + + + +end architecture; diff --git a/media_interfaces/sync/tx_control_xcku.vhd b/media_interfaces/sync/tx_control_xcku.vhd new file mode 100644 index 0000000..3fa06d0 --- /dev/null +++ b/media_interfaces/sync/tx_control_xcku.vhd @@ -0,0 +1,585 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.med_sync_define.all; + +entity tx_control is + port( + CLK_200 : in std_logic; + CLK_100 : in std_logic; + RESET_IN : in std_logic; + + TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); + TX_WRITE_IN : in std_logic; + TX_READ_OUT : out std_logic; + + TX_DATA_OUT : out std_logic_vector( 7 downto 0); + TX_K_OUT : out std_logic; + TX_CD_OUT : out std_logic; + + REQUEST_RETRANSMIT_IN : in std_logic := '0'; + REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); + + START_RETRANSMIT_IN : in std_logic := '0'; + START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0'); + --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM + SEND_DLM : in std_logic := '0'; + SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0'); + + SEND_LINK_RESET_IN : in std_logic := '0'; + TX_ALLOW_IN : in std_logic := '0'; + RX_ALLOW_IN : in std_logic := '0'; + + DEBUG_OUT : out std_logic_vector(31 downto 0); + STAT_REG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + + +architecture arch of tx_control is + + + type state_t is (SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, SEND_DLM_L, SEND_DLM_H, + SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H, + SEND_RESET, SEND_CHKSUM_L, SEND_CHKSUM_H); -- gk 05.10.10 + signal current_state : state_t; + signal state_bits : std_logic_vector(3 downto 0); + + type ram_t is array(0 to 255) of std_logic_vector(17 downto 0); + signal ram : ram_t; + + signal ram_write : std_logic := '0'; + signal ram_write_addr : unsigned(7 downto 0) := (others => '0'); + signal last_ram_write_addr : unsigned(7 downto 0) := (others => '0'); + signal ram_read : std_logic := '0'; + signal ram_read_addr : unsigned(7 downto 0) := (others => '0'); + signal ram_dout : std_logic_vector(17 downto 0); + signal next_ram_dout : std_logic_vector(17 downto 0); + signal ram_fill_level : unsigned(7 downto 0); + signal ram_empty : std_logic; + signal ram_afull : std_logic; + + signal request_position_q : std_logic_vector( 7 downto 0); + signal restart_position_q : std_logic_vector( 7 downto 0); + signal request_position_i : std_logic_vector( 7 downto 0); + signal restart_position_i : std_logic_vector( 7 downto 0); + signal make_request_i : std_logic; + signal make_restart_i : std_logic; + signal load_read_pointer_i : std_logic; + signal send_dlm_in_i : std_logic; + signal send_dlm_i : std_logic; + signal start_retransmit_i : std_logic; + signal request_retransmit_i : std_logic; + + signal buf_tx_read_out : std_logic; + signal tx_data_200 : std_logic_vector(17 downto 0); + signal tx_allow_qtx : std_logic; + signal rx_allow_qtx : std_logic; + signal tx_allow_q : std_logic; + signal send_link_reset_qtx : std_logic; + signal ct_fifo_empty : std_logic; + signal ct_fifo_write : std_logic := '0'; + signal ct_fifo_read : std_logic := '0'; + signal ct_fifo_full : std_logic; + signal ct_fifo_afull : std_logic; + signal ct_fifo_reset : std_logic; + signal last_ct_fifo_empty : std_logic; + signal last_ct_fifo_read : std_logic; + signal debug_sending_dlm : std_logic; + + -- gk 05.10.10 + signal save_sop : std_logic; + signal save_eop : std_logic; + signal load_sop : std_logic; + signal load_eop : std_logic; + signal crc_reset : std_logic; + signal crc_q : std_logic_vector(7 downto 0); + signal crc_en : std_logic; + signal crc_data : std_logic_vector(7 downto 0); + signal first_idle : std_logic; + signal toggle_idle : std_logic; + + attribute MARK_DEBUG : string; + attribute MARK_DEBUG of CLK_100 : signal is "TRUE"; + attribute MARK_DEBUG of TX_DATA_IN : signal is "TRUE"; + attribute MARK_DEBUG of TX_PACKET_NUMBER_IN : signal is "TRUE"; + attribute MARK_DEBUG of TX_WRITE_IN : signal is "TRUE"; + attribute MARK_DEBUG of stat_reg_out : signal is "TRUE"; + attribute MARK_DEBUG of CLK_200 : signal is "TRUE"; + attribute MARK_DEBUG of TX_DATA_OUT : signal is "TRUE"; + attribute MARK_DEBUG of TX_K_OUT : signal is "TRUE"; + attribute MARK_DEBUG of state_bits : signal is "TRUE"; + attribute MARK_DEBUG of debug_out : signal is "TRUE"; + attribute KEEP : string; + attribute KEEP of CLK_100 : signal is "TRUE"; + attribute KEEP of TX_DATA_IN : signal is "TRUE"; + attribute KEEP of TX_PACKET_NUMBER_IN : signal is "TRUE"; + attribute KEEP of TX_WRITE_IN : signal is "TRUE"; + attribute KEEP of stat_reg_out : signal is "TRUE"; + attribute KEEP of CLK_200 : signal is "TRUE"; + attribute KEEP of TX_DATA_OUT : signal is "TRUE"; + attribute KEEP of TX_K_OUT : signal is "TRUE"; + attribute KEEP of state_bits : signal is "TRUE"; + attribute KEEP of debug_out : signal is "TRUE"; +begin + +---------------------------------------------------------------------- +-- Clock Domain Transfer +---------------------------------------------------------------------- +-- gk 05.10.10 + THE_CT_FIFO : entity work.fifo_18x16_dualport_oreg + port map( + Data(15 downto 0) => TX_DATA_IN, + Data(16) => save_sop, + Data(17) => save_eop, + WrClock => CLK_100, + RdClock => CLK_200, + WrEn => ct_fifo_write, + RdEn => ct_fifo_read, + Reset => ct_fifo_reset, + RPReset => ct_fifo_reset, + Q(17 downto 0) => tx_data_200, + Empty => ct_fifo_empty, + Full => ct_fifo_full, + AlmostFull => ct_fifo_afull + ); + + THE_RD_PROC : process(CLK_100) + begin + if rising_edge(CLK_100) then + buf_tx_read_out <= tx_allow_q and not ct_fifo_afull ; + end if; + end process; + + ct_fifo_reset <= not tx_allow_qtx; + TX_READ_OUT <= buf_tx_read_out; + + ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN; + ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty; + + last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_200); + last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_200); + + save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0'; + save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0'; + +---------------------------------------------------------------------- +-- RAM +---------------------------------------------------------------------- + + + THE_RAM_WR_PROC : process(CLK_200) + begin +-- if RESET_IN = '1' then +-- ram_write <= '0'; +-- els + if rising_edge(CLK_200) then + ram_write <= last_ct_fifo_read and not last_ct_fifo_empty; + end if; + end process; + +--RAM + THE_RAM_PROC : process(CLK_200) + begin + if rising_edge(CLK_200) then + if ram_write = '1' then + ram((to_integer(ram_write_addr))) <= tx_data_200; + end if; + next_ram_dout <= ram(to_integer(ram_read_addr)); + ram_dout <= next_ram_dout; + end if; + end process; + +--RAM read pointer + THE_READ_CNT : process(CLK_200) + begin +-- if RESET_IN = '1' then +-- ram_read_addr <= (others => '0'); +-- els + if rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + ram_read_addr <= (others => '0'); + elsif load_read_pointer_i = '1' then + ram_read_addr <= unsigned(restart_position_i); + elsif ram_read = '1' then + ram_read_addr <= ram_read_addr + to_unsigned(1,1); + end if; + end if; + end process; + +--RAM write pointer + THE_WRITE_CNT : process(CLK_200) + begin +-- if RESET_IN = '1' then +-- ram_write_addr <= (others => '0'); +-- els + if rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + ram_write_addr <= (others => '0'); + elsif ram_write = '1' then + ram_write_addr <= ram_write_addr + to_unsigned(1,1); + end if; + end if; + end process; + + +--RAM fill level counter + THE_FILL_CNT : process(CLK_200) + begin +-- if RESET_IN = '1' then +-- ram_fill_level <= (others => '0'); +-- els + if rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + ram_fill_level <= (others => '0'); + else + ram_fill_level <= last_ram_write_addr - ram_read_addr; + end if; + end if; + end process; + + +--RAM empty +-- ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN; + ram_empty <= '1' when (last_ram_write_addr = ram_read_addr) or RESET_IN = '1' else '0'; + ram_afull <= '1' when ram_fill_level >= 4 else '0'; + + last_ram_write_addr <= ram_write_addr when rising_edge(CLK_200); + +---------------------------------------------------------------------- +-- TX control state machine +---------------------------------------------------------------------- + + THE_DATA_CONTROL_FSM : process(CLK_200, RESET_IN) + begin + if rising_edge(CLK_200) then +-- ram_read <= '0'; + TX_K_OUT <= '0'; + TX_CD_OUT <= '0'; + debug_sending_dlm <= '0'; + first_idle <= '1'; + case current_state is + when SEND_IDLE_L => + TX_DATA_OUT <= K_IDLE; + TX_K_OUT <= '1'; + current_state <= SEND_IDLE_H; + first_idle <= first_idle; + + when SEND_IDLE_H => + if rx_allow_qtx = '1' or toggle_idle = '1' then + TX_DATA_OUT <= D_IDLE1; + toggle_idle <= rx_allow_qtx; + else + TX_DATA_OUT <= D_IDLE0; + toggle_idle <= '1'; + end if; + TX_CD_OUT <= first_idle; + first_idle <= '0'; + + when SEND_DATA_L => + TX_DATA_OUT <= ram_dout(7 downto 0); + load_sop <= ram_dout(16); + load_eop <= ram_dout(17); + current_state <= SEND_DATA_H; + + when SEND_DATA_H => + TX_DATA_OUT <= ram_dout(15 downto 8); + + when SEND_CHKSUM_L => + TX_DATA_OUT <= K_EOP; + TX_K_OUT <= '1'; + load_sop <= '0'; + load_eop <= '0'; + current_state <= SEND_CHKSUM_H; + + when SEND_CHKSUM_H => + TX_DATA_OUT <= crc_q; + + when SEND_START_L => + TX_DATA_OUT <= K_BGN; + TX_K_OUT <= '1'; + current_state <= SEND_START_H; + + when SEND_START_H => + TX_DATA_OUT <= std_logic_vector(ram_read_addr); + + when SEND_REQUEST_L => + TX_DATA_OUT <= K_REQ; + TX_K_OUT <= '1'; + current_state <= SEND_REQUEST_H; + + when SEND_DLM_L => + TX_DATA_OUT <= K_DLM; + TX_K_OUT <= '1'; + current_state <= SEND_DLM_H; + debug_sending_dlm <= '1'; + + when SEND_DLM_H => + TX_DATA_OUT <= SEND_DLM_WORD; + debug_sending_dlm <= '1'; + + when SEND_REQUEST_H => + TX_DATA_OUT <= request_position_i; + + when SEND_RESET => + TX_DATA_OUT <= K_RST; + TX_K_OUT <= '1'; + if send_link_reset_qtx = '0' then + current_state <= SEND_IDLE_L; + end if; + + when others => + current_state <= SEND_IDLE_L; + end case; + + if current_state = SEND_START_H or + current_state = SEND_IDLE_H or + current_state = SEND_DATA_H or + current_state = SEND_DLM_H or + current_state = SEND_REQUEST_H or + current_state = SEND_CHKSUM_H then + if tx_allow_qtx = '0' then + current_state <= SEND_IDLE_L; + elsif send_link_reset_qtx = '1' then + current_state <= SEND_RESET; + elsif make_request_i = '1' then + current_state <= SEND_REQUEST_L; + elsif make_restart_i = '1' then + current_state <= SEND_START_L; + elsif send_dlm_i = '1' then + current_state <= SEND_DLM_L; +-- elsif (load_eop = '1') then +-- current_state <= SEND_CHKSUM_L; + elsif ram_empty = '0' then +-- ram_read <= '1'; + current_state <= SEND_DATA_L; + else + current_state <= SEND_IDLE_L; + end if; + + end if; + end if; + --async because of oreg. + if (current_state = SEND_START_H or current_state = SEND_IDLE_H or current_state = SEND_DATA_H or + current_state = SEND_DLM_H or current_state = SEND_REQUEST_H or current_state = SEND_CHKSUM_H) + and ram_empty = '0' and tx_allow_qtx = '1' and send_link_reset_qtx = '0' + and make_request_i = '0' and make_restart_i = '0' and send_dlm_i = '0' then --TODO: Sync these 3 signals + ram_read <= '1'; + else + ram_read <= '0'; + end if; + if RESET_IN = '1' then + ram_read <= '0'; + end if; + end process; + +---------------------------------------------------------------------- +-- +---------------------------------------------------------------------- + + txallow_sync : signal_sync port map(RESET => '0',CLK0 => CLK_200, CLK1 => CLK_200, + D_IN(0) => TX_ALLOW_IN, + D_OUT(0) => tx_allow_qtx); + rxallow_sync : signal_sync port map(RESET => '0',CLK0 => CLK_200, CLK1 => CLK_200, + D_IN(0) => RX_ALLOW_IN, + D_OUT(0) => rx_allow_qtx); + sendres_sync : signal_sync port map(RESET => '0',CLK0 => CLK_200, CLK1 => CLK_200, + D_IN(0) => SEND_LINK_RESET_IN, + D_OUT(0) => send_link_reset_qtx); + txallow_sync2 : signal_sync port map(RESET => '0',CLK0 => CLK_100, CLK1 => CLK_100, + D_IN(0) => tx_allow_qtx, + D_OUT(0) => tx_allow_q); + + + THE_RETRANSMIT_PULSE_SYNC_1 : pulse_sync + port map( + CLK_A_IN => CLK_100, + RESET_A_IN => RESET_IN, + PULSE_A_IN => REQUEST_RETRANSMIT_IN, + CLK_B_IN => CLK_200, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => request_retransmit_i + ); + + THE_RETRANSMIT_PULSE_SYNC_2 : pulse_sync + port map( + CLK_A_IN => CLK_100, + RESET_A_IN => RESET_IN, + PULSE_A_IN => START_RETRANSMIT_IN, + CLK_B_IN => CLK_200, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => start_retransmit_i + ); + +-- THE_RETRANSMIT_PULSE_SYNC_3 : pulse_sync +-- port map( +-- CLK_A_IN => CLK_100, +-- RESET_A_IN => RESET_IN, +-- PULSE_A_IN => SEND_DLM, +-- CLK_B_IN => CLK_200, +-- RESET_B_IN => RESET_IN, +-- PULSE_B_OUT => send_dlm_in_i +-- ); + send_dlm_in_i <= SEND_DLM; + + THE_POSITION_REG : process(CLK_100) + begin + if rising_edge(CLK_100) then + if REQUEST_RETRANSMIT_IN = '1' then + request_position_q <= REQUEST_POSITION_IN; + end if; + if START_RETRANSMIT_IN = '1' then + restart_position_q <= START_POSITION_IN; + end if; + end if; + end process; + + +--Store Request Retransmit position + THE_STORE_REQUEST_PROC : process(CLK_200, RESET_IN) + begin + if RESET_IN = '1' then + make_request_i <= '0'; + request_position_i <= (others => '0'); + elsif rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + make_request_i <= '0'; + request_position_i <= (others => '0'); + elsif request_retransmit_i = '1' then + make_request_i <= '1'; + request_position_i <= request_position_q; + elsif current_state = SEND_REQUEST_L then + make_request_i <= '0'; + elsif current_state = SEND_REQUEST_H then + request_position_i <= (others => '0'); + end if; + end if; + end process; + + +--Store Restart position + THE_STORE_RESTART_PROC : process(CLK_200, RESET_IN) + begin + if RESET_IN = '1' then + make_restart_i <= '0'; + restart_position_i <= (others => '0'); + elsif rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + make_restart_i <= '0'; + restart_position_i <= (others => '0'); + elsif start_retransmit_i = '1' then + make_restart_i <= '1'; + restart_position_i <= restart_position_q; + elsif current_state = SEND_START_L then + make_restart_i <= '0'; + elsif current_state = SEND_START_H then + restart_position_i <= (others => '0'); + end if; + end if; + end process; + +--Store Restart position + THE_STORE_DLM_PROC : process(CLK_200, RESET_IN) + begin + if RESET_IN = '1' then + send_dlm_i <= '0'; + elsif rising_edge(CLK_200) then + if tx_allow_qtx = '0' then + send_dlm_i <= '0'; + elsif send_dlm_in_i = '1' then + send_dlm_i <= '1'; + elsif current_state = SEND_DLM_L then + send_dlm_i <= '0'; + end if; + end if; + end process; + + load_read_pointer_i <= '1' when current_state = SEND_START_L else '0'; + + -- gk 05.10.10 + crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_CHKSUM_H) or (current_state = SEND_START_H)) else '0'; + crc_en <= '1' when ((current_state = SEND_DATA_L) or (current_state = SEND_DATA_H)) else '0'; + crc_data <= ram_dout(15 downto 8) when (current_state = SEND_DATA_H) else ram_dout(7 downto 0); + + -- gk 05.10.10 + CRC_CALC : trb_net_CRC8 + port map( + CLK => CLK_200, + RESET => crc_reset, + CLK_EN => crc_en, + DATA_IN => crc_data, + CRC_OUT => crc_q, + CRC_match => open + ); + + +---------------------------------------------------------------------- +-- Debug +---------------------------------------------------------------------- + DEBUG_OUT(0) <= ct_fifo_afull; + DEBUG_OUT(1) <= ct_fifo_write; + DEBUG_OUT(2) <= ct_fifo_read; + DEBUG_OUT(3) <= tx_allow_qtx; +-- DEBUG_OUT(4) <= ram_empty; + DEBUG_OUT(5) <= ram_afull; + DEBUG_OUT(6) <= debug_sending_dlm when rising_edge(CLK_200); + DEBUG_OUT(7) <= TX_WRITE_IN; +-- DEBUG_OUT(8) <= ram_read; + DEBUG_OUT(9) <= ram_write; + DEBUG_OUT(13 downto 10) <= state_bits; + DEBUG_OUT(15 downto 14) <= "00"; + DEBUG_OUT(23 downto 16) <= tx_data_200(7 downto 0); + DEBUG_OUT(31 downto 24) <= ram_dout(7 downto 0); + + process(CLK_100) + begin + if rising_edge(CLK_100) then + STAT_REG_OUT <= (others => '0'); +-- STAT_REG_OUT(7 downto 0) <= std_logic_vector(ram_fill_level); + STAT_REG_OUT(3 downto 0) <= state_bits; + +-- STAT_REG_OUT(7) <= TX_K_OUT; +-- STAT_REG_OUT(15 downto 8) <= TX_DATA_OUT; + STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr); +-- STAT_REG_OUT(16) <= ram_afull; + STAT_REG_OUT(17) <= ram_empty; + STAT_REG_OUT(18) <= tx_allow_qtx; + STAT_REG_OUT(19) <= TX_ALLOW_IN; + STAT_REG_OUT(20) <= make_restart_i; + STAT_REG_OUT(21) <= make_request_i; + STAT_REG_OUT(22) <= load_eop; + STAT_REG_OUT(23) <= send_dlm_i; + STAT_REG_OUT(24) <= make_restart_i; + STAT_REG_OUT(25) <= make_request_i; + STAT_REG_OUT(26) <= load_read_pointer_i; + STAT_REG_OUT(27) <= ct_fifo_afull; + STAT_REG_OUT(28) <= ct_fifo_read; + STAT_REG_OUT(29) <= ct_fifo_write; + STAT_REG_OUT(30) <= RESET_IN; + STAT_REG_OUT(31) <= '0'; +-- STAT_REG_OUT(31 downto 27) <= (others => '0'); + end if; + end process; + +state_bits <= x"0" when current_state = SEND_IDLE_L else + x"1" when current_state = SEND_IDLE_H else + x"2" when current_state = SEND_DATA_L else + x"3" when current_state = SEND_DATA_H else + x"4" when current_state = SEND_DLM_L else + x"5" when current_state = SEND_DLM_H else + x"6" when current_state = SEND_START_L else + x"7" when current_state = SEND_START_H else + x"8" when current_state = SEND_REQUEST_L else + x"9" when current_state = SEND_REQUEST_H else + x"a" when current_state = SEND_CHKSUM_L else + x"b" when current_state = SEND_CHKSUM_H else + x"c" when current_state = SEND_RESET else + x"F"; + +end architecture; diff --git a/media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xci b/media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xci new file mode 100644 index 0000000..f6efa8f --- /dev/null +++ b/media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xci @@ -0,0 +1,715 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_txUsrClk + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.000 + + + + 100000000 + 0 + 0 + 0.000 + + + + 100000000 + 0 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 100.0 + 0000 + 0000 + 200.00000 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 200.00000 + 0.000 + 50.000 + 200.000 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 2.0 + 2.0 + 2.0 + 2.0 + 2.0 + 2.0 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________100.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 10.000 + 0.000 + FALSE + 10.000 + 10.000 + 5.000 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 1 + None + 0.010 + 0.010 + FALSE + 64.000 + 2.000 + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out1__200.00000______0.000______50.0______114.829_____98.575 + clk_out2__100.00000______0.000______50.0______130.958_____98.575 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1440.000 + 600.000 + clk_txUsrClk + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + Buffer + 114.829 + false + 98.575 + 50.000 + 200.000 + 0.000 + 1 + true + Buffer + 130.958 + false + 98.575 + 50.000 + 100.000 + 0.000 + 1 + true + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_txUsrClk + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 10.000 + 0.000 + false + 10.000 + 10.000 + 5.000 + 0.500 + 0.000 + false + 10 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + AUTO + 1 + None + 0.010 + 0.010 + false + 2 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + false + false + true + false + false + false + kintexu + + + xcku115 + flvf1924 + VHDL + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2020.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xml b/media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xml new file mode 100644 index 0000000..cc4c11c --- /dev/null +++ b/media_interfaces/xcku/clk_txUsrClk/clk_txUsrClk.xml @@ -0,0 +1,4678 @@ + + + xilinx.com + customized_ip + clk_txUsrClk + 1.0 + + + s_axi_lite + S_AXI_LITE + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 1 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 1 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 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C_ENABLE_USER_CLOCK0 + 0 + + + C_ENABLE_USER_CLOCK1 + 0 + + + C_ENABLE_USER_CLOCK2 + 0 + + + C_ENABLE_USER_CLOCK3 + 0 + + + C_Enable_PLL0 + 0 + + + C_Enable_PLL1 + 0 + + + C_REF_CLK_FREQ + 100.0 + + + C_PRECISION + 1 + + + C_CLKOUT3_USED + 0 + + + C_CLKOUT4_USED + 0 + + + C_CLKOUT5_USED + 0 + + + C_CLKOUT6_USED + 0 + + + C_CLKOUT7_USED + 0 + + + C_USE_CLKOUT1_BAR + 0 + + + C_USE_CLKOUT2_BAR + 0 + + + C_USE_CLKOUT3_BAR + 0 + + + C_USE_CLKOUT4_BAR + 0 + + + c_component_name + clk_txUsrClk + + + C_PLATFORM + UNKNOWN + + + C_USE_FREQ_SYNTH + 1 + + + C_USE_PHASE_ALIGNMENT + 0 + + + C_PRIM_IN_JITTER + 0.010 + + + C_SECONDARY_IN_JITTER + 0.010 + + + C_JITTER_SEL + No_Jitter + + + C_USE_MIN_POWER + 0 + + + C_USE_MIN_O_JITTER + 0 + + + C_USE_MAX_I_JITTER + 0 + + + C_USE_DYN_PHASE_SHIFT + 0 + + + C_USE_INCLK_SWITCHOVER + 0 + + + C_USE_DYN_RECONFIG + 0 + + + C_USE_SPREAD_SPECTRUM + 0 + + + C_USE_FAST_SIMULATION + 0 + + + C_PRIMTYPE_SEL + AUTO + + + C_USE_CLK_VALID + 0 + + + C_PRIM_IN_FREQ + 100.000 + + + C_PRIM_IN_TIMEPERIOD + 10.000 + + + C_IN_FREQ_UNITS + Units_MHz + + + C_SECONDARY_IN_FREQ + 100.000 + + + C_SECONDARY_IN_TIMEPERIOD + 10.000 + + + C_FEEDBACK_SOURCE + FDBK_AUTO + + + C_PRIM_SOURCE + Single_ended_clock_capable_pin + + + C_PHASESHIFT_MODE + WAVEFORM + + + C_SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + C_CLKFB_IN_SIGNALING + SINGLE + + + C_USE_RESET + 1 + + + C_RESET_LOW + 0 + + + C_USE_LOCKED + 1 + + + C_USE_INCLK_STOPPED + 0 + + + C_USE_CLKFB_STOPPED + 0 + + + C_USE_POWER_DOWN + 0 + + + C_USE_STATUS + 0 + + + C_USE_FREEZE + 0 + + + C_NUM_OUT_CLKS + 2 + + + C_CLKOUT1_DRIVES + BUFG + + + C_CLKOUT2_DRIVES + BUFG + + + C_CLKOUT3_DRIVES + BUFG + + + C_CLKOUT4_DRIVES + BUFG + + + C_CLKOUT5_DRIVES + BUFG + + + C_CLKOUT6_DRIVES + BUFG + + + C_CLKOUT7_DRIVES + BUFG + + + C_INCLK_SUM_ROW0 + Input Clock Freq (MHz) Input Jitter (UI) + + + C_INCLK_SUM_ROW1 + __primary_________100.000____________0.010 + + + C_INCLK_SUM_ROW2 + no_secondary_input_clock + + + C_OUTCLK_SUM_ROW0A + C Outclk Sum Row0a + Output Output Phase Duty Cycle Pk-to-Pk Phase + + + C_OUTCLK_SUM_ROW0B + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + + + C_OUTCLK_SUM_ROW1 + clk_out1__200.00000______0.000______50.0______114.829_____98.575 + + + C_OUTCLK_SUM_ROW2 + clk_out2__100.00000______0.000______50.0______130.958_____98.575 + + + C_OUTCLK_SUM_ROW3 + no_CLK_OUT3_output + + + C_OUTCLK_SUM_ROW4 + no_CLK_OUT4_output + + + C_OUTCLK_SUM_ROW5 + no_CLK_OUT5_output + + + C_OUTCLK_SUM_ROW6 + no_CLK_OUT6_output + + + C_OUTCLK_SUM_ROW7 + no_CLK_OUT7_output + + + C_CLKOUT1_REQUESTED_OUT_FREQ + 200.000 + + + C_CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT1_REQUESTED_PHASE + 0.000 + + + C_CLKOUT2_REQUESTED_PHASE + 0.000 + + + C_CLKOUT3_REQUESTED_PHASE + 0.000 + + + C_CLKOUT4_REQUESTED_PHASE + 0.000 + + + C_CLKOUT5_REQUESTED_PHASE + 0.000 + + + C_CLKOUT6_REQUESTED_PHASE + 0.000 + + + C_CLKOUT7_REQUESTED_PHASE + 0.000 + + + C_CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT1_OUT_FREQ + 200.00000 + + + C_CLKOUT2_OUT_FREQ + 100.00000 + + + C_CLKOUT3_OUT_FREQ + 100.000 + + + C_CLKOUT4_OUT_FREQ + 100.000 + + + C_CLKOUT5_OUT_FREQ + 100.000 + + + C_CLKOUT6_OUT_FREQ + 100.000 + + + C_CLKOUT7_OUT_FREQ + 100.000 + + + C_CLKOUT1_PHASE + 0.000 + + + C_CLKOUT2_PHASE + 0.000 + + + C_CLKOUT3_PHASE + 0.000 + + + C_CLKOUT4_PHASE + 0.000 + + + C_CLKOUT5_PHASE + 0.000 + + + C_CLKOUT6_PHASE + 0.000 + + + C_CLKOUT7_PHASE + 0.000 + + + C_CLKOUT1_DUTY_CYCLE + 50.0 + + + C_CLKOUT2_DUTY_CYCLE + 50.0 + + + C_CLKOUT3_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_DUTY_CYCLE + 50.000 + + + C_USE_SAFE_CLOCK_STARTUP + 0 + + + C_USE_CLOCK_SEQUENCING + 0 + + + C_CLKOUT1_SEQUENCE_NUMBER + 1 + + + C_CLKOUT2_SEQUENCE_NUMBER + 1 + + + C_CLKOUT3_SEQUENCE_NUMBER + 1 + + + C_CLKOUT4_SEQUENCE_NUMBER + 1 + + + C_CLKOUT5_SEQUENCE_NUMBER + 1 + + + C_CLKOUT6_SEQUENCE_NUMBER + 1 + + + C_CLKOUT7_SEQUENCE_NUMBER + 1 + + + C_MMCM_NOTES + None + + + C_MMCM_BANDWIDTH + OPTIMIZED + + + C_MMCM_CLKFBOUT_MULT_F + 10.000 + + + C_MMCM_CLKIN1_PERIOD + 10.000 + + + C_MMCM_CLKIN2_PERIOD + 10.000 + + + C_MMCM_CLKOUT4_CASCADE + FALSE + + + C_MMCM_CLOCK_HOLD + FALSE + + + C_MMCM_COMPENSATION + AUTO + + + C_MMCM_DIVCLK_DIVIDE + 1 + + + C_MMCM_REF_JITTER1 + 0.010 + + + C_MMCM_REF_JITTER2 + 0.010 + + + C_MMCM_STARTUP_WAIT + FALSE + + + C_MMCM_CLKOUT0_DIVIDE_F + 5.000 + + + C_MMCM_CLKOUT1_DIVIDE + 10 + + + C_MMCM_CLKOUT2_DIVIDE + 1 + + + C_MMCM_CLKOUT3_DIVIDE + 1 + + + C_MMCM_CLKOUT4_DIVIDE + 1 + + + C_MMCM_CLKOUT5_DIVIDE + 1 + + + C_MMCM_CLKOUT6_DIVIDE + 1 + + + C_MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKFBOUT_PHASE + 0.000 + + + C_MMCM_CLKOUT0_PHASE + 0.000 + + + C_MMCM_CLKOUT1_PHASE + 0.000 + + + C_MMCM_CLKOUT2_PHASE + 0.000 + + + C_MMCM_CLKOUT3_PHASE + 0.000 + + + C_MMCM_CLKOUT4_PHASE + 0.000 + + + C_MMCM_CLKOUT5_PHASE + 0.000 + + + C_MMCM_CLKOUT6_PHASE + 0.000 + + + C_MMCM_CLKFBOUT_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT0_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT1_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT2_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT3_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT4_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT5_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT6_USE_FINE_PS + FALSE + + + C_PLL_NOTES + No notes + + + C_PLL_BANDWIDTH + OPTIMIZED + + + C_PLL_CLK_FEEDBACK + CLKFBOUT + + + C_PLL_CLKFBOUT_MULT + 1 + + + C_PLL_CLKIN_PERIOD + 1.000 + + + C_PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + C_PLL_DIVCLK_DIVIDE + 1 + + + C_PLL_REF_JITTER + 0.010 + + + C_PLL_CLKOUT0_DIVIDE + 1 + + + C_PLL_CLKOUT1_DIVIDE + 1 + + + C_PLL_CLKOUT2_DIVIDE + 1 + + + C_PLL_CLKOUT3_DIVIDE + 1 + + + C_PLL_CLKOUT4_DIVIDE + 1 + + + C_PLL_CLKOUT5_DIVIDE + 1 + + + C_PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_PLL_CLKFBOUT_PHASE + 0.000 + + + C_PLL_CLKOUT0_PHASE + 0.000 + + + C_PLL_CLKOUT1_PHASE + 0.000 + + + C_PLL_CLKOUT2_PHASE + 0.000 + + + C_PLL_CLKOUT3_PHASE + 0.000 + + + C_PLL_CLKOUT4_PHASE + 0.000 + + + C_PLL_CLKOUT5_PHASE + 0.000 + + + C_CLOCK_MGR_TYPE + NA + + + C_OVERRIDE_MMCM + 0 + + + C_OVERRIDE_PLL + 0 + + + C_PRIMARY_PORT + clk_in1 + + + C_SECONDARY_PORT + clk_in2 + + + C_CLK_OUT1_PORT + clk_out1 + + + C_CLK_OUT2_PORT + clk_out2 + + + C_CLK_OUT3_PORT + clk_out3 + + + C_CLK_OUT4_PORT + clk_out4 + + + C_CLK_OUT5_PORT + clk_out5 + + + C_CLK_OUT6_PORT + clk_out6 + + + C_CLK_OUT7_PORT + clk_out7 + + + C_RESET_PORT + reset + + + C_LOCKED_PORT + locked + + + C_CLKFB_IN_PORT + clkfb_in + + + C_CLKFB_IN_P_PORT + clkfb_in_p + + + C_CLKFB_IN_N_PORT + clkfb_in_n + + + C_CLKFB_OUT_PORT + clkfb_out + + + C_CLKFB_OUT_P_PORT + clkfb_out_p + + + C_CLKFB_OUT_N_PORT + clkfb_out_n + + + C_POWER_DOWN_PORT + power_down + + + C_DADDR_PORT + daddr + + + C_DCLK_PORT + dclk + + + C_DRDY_PORT + drdy + + + C_DWE_PORT + dwe + + + C_DIN_PORT + din + + + C_DOUT_PORT + dout + + + C_DEN_PORT + den + + + C_PSCLK_PORT + psclk + + + C_PSEN_PORT + psen + + + C_PSINCDEC_PORT + psincdec + + + C_PSDONE_PORT + psdone + + + C_CLK_VALID_PORT + CLK_VALID + + + C_STATUS_PORT + STATUS + + + C_CLK_IN_SEL_PORT + clk_in_sel + + + C_INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + C_CLKFB_STOPPED_PORT + clkfb_stopped + + + C_CLKIN1_JITTER_PS + 100.0 + + + C_CLKIN2_JITTER_PS + 100.0 + + + C_PRIMITIVE + MMCM + + + C_SS_MODE + CENTER_HIGH + + + C_SS_MOD_PERIOD + 4000 + + + C_SS_MOD_TIME + 0.004 + + + C_HAS_CDDC + 0 + + + C_CDDCDONE_PORT + cddcdone + + + C_CDDCREQ_PORT + cddcreq + + + C_CLKOUTPHY_MODE + VCO + + + C_ENABLE_CLKOUTPHY + 0 + + + C_INTERFACE_SELECTION + 0 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 11 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_POWER_REG + 0000 + + + C_CLKOUT0_1 + 0000 + + + C_CLKOUT0_2 + 0000 + + + C_CLKOUT1_1 + 0000 + + + C_CLKOUT1_2 + 0000 + + + C_CLKOUT2_1 + 0000 + + + C_CLKOUT2_2 + 0000 + + + C_CLKOUT3_1 + 0000 + + + C_CLKOUT3_2 + 0000 + + + C_CLKOUT4_1 + 0000 + + + C_CLKOUT4_2 + 0000 + + + C_CLKOUT5_1 + 0000 + + + C_CLKOUT5_2 + 0000 + + + C_CLKOUT6_1 + 0000 + + + C_CLKOUT6_2 + 0000 + + + C_CLKFBOUT_1 + 0000 + + + C_CLKFBOUT_2 + 0000 + + + C_DIVCLK + 0000 + + + C_LOCK_1 + 0000 + + + C_LOCK_2 + 0000 + + + C_LOCK_3 + 0000 + + + C_FILTER_1 + 0000 + + + C_FILTER_2 + 0000 + + + C_DIVIDE1_AUTO + 1 + + + C_DIVIDE2_AUTO + 2.0 + + + C_DIVIDE3_AUTO + 2.0 + + + C_DIVIDE4_AUTO + 2.0 + + + C_DIVIDE5_AUTO + 2.0 + + + C_DIVIDE6_AUTO + 2.0 + + + C_DIVIDE7_AUTO + 2.0 + + + C_PLLBUFGCEDIV + false + + + C_MMCMBUFGCEDIV + false + + + C_PLLBUFGCEDIV1 + false + + + C_PLLBUFGCEDIV2 + false + + + C_PLLBUFGCEDIV3 + false + + + C_PLLBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV1 + false + + + C_MMCMBUFGCEDIV2 + false + + + C_MMCMBUFGCEDIV3 + false + + + C_MMCMBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV5 + false + + + C_MMCMBUFGCEDIV6 + false + + + C_MMCMBUFGCEDIV7 + false + + + C_CLKOUT1_MATCHED_ROUTING + false + + + C_CLKOUT2_MATCHED_ROUTING + false + + + C_CLKOUT3_MATCHED_ROUTING + false + + + C_CLKOUT4_MATCHED_ROUTING + false + + + C_CLKOUT5_MATCHED_ROUTING + false + + + C_CLKOUT6_MATCHED_ROUTING + false + + + C_CLKOUT7_MATCHED_ROUTING + false + + + C_CLKOUT0_ACTUAL_FREQ + 200.00000 + + + C_CLKOUT1_ACTUAL_FREQ + 100.00000 + + + C_CLKOUT2_ACTUAL_FREQ + 100.000 + + + C_CLKOUT3_ACTUAL_FREQ + 100.000 + + + C_CLKOUT4_ACTUAL_FREQ + 100.000 + + + C_CLKOUT5_ACTUAL_FREQ + 100.000 + + + C_CLKOUT6_ACTUAL_FREQ + 100.000 + + + C_M_MAX + 64.000 + + + C_M_MIN + 2.000 + + + C_D_MAX + 93.000 + + + C_D_MIN + 1.000 + + + C_O_MAX + 128.000 + + + C_O_MIN + 1.000 + + + C_VCO_MIN + 600.000 + + + C_VCO_MAX + 1440.000 + + + + + + choice_list_1d3de01d + WAVEFORM + LATENCY + + + choice_list_876bfc32 + UI + PS + + + choice_list_a9bdfce0 + LOW + HIGH + OPTIMIZED + + + choice_list_ac75ef1e + Custom + + + choice_list_b9d38208 + CLKFBOUT + CLKOUT0 + + + choice_list_d0ea4aeb + MMCM + PLL + Auto + + + choice_pairs_035ca1c3 + SYSTEM_SYNCHRONOUS + SOURCE_SYNCHRONOUS + INTERNAL + EXTERNAL + + + choice_pairs_0920eb1b + Custom + sys_diff_clock + + + choice_pairs_11d71346 + Single_ended_clock_capable_pin + Differential_clock_capable_pin + Global_buffer + No_buffer + + + choice_pairs_15c806d5 + FDBK_AUTO + FDBK_AUTO_OFFCHIP + FDBK_ONCHIP + FDBK_OFFCHIP + + + choice_pairs_340369e0 + Custom + sys_clock + sys_diff_clock + + + choice_pairs_39d99e50 + Buffer + Buffer_with_CE + BUFG + BUFGCE + BUFGCE_DIV + No_buffer + + + choice_pairs_3c2d3ec7 + SINGLE + DIFF + + + choice_pairs_77d3d587 + MMCM + PLL + BUFGCE_DIV + + + choice_pairs_8b28f1f7 + Enable_AXI + Enable_DRP + + + choice_pairs_8eea9b32 + Units_MHz + Units_ns + + + choice_pairs_94e02745 + AUTO + EXTERNAL + INTERNAL + BUF_IN + ZHOLD + + + choice_pairs_a4fbc00c + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a8642b4c + No_Jitter + Min_O_Jitter + Max_I_Jitter + + + choice_pairs_c5ef7212 + Units_UI + Units_ps + + + choice_pairs_e1c87518 + REL_PRIMARY + REL_SECONDARY + + + choice_pairs_f4e10086 + CENTER_HIGH + CENTER_LOW + DOWN_HIGH + DOWN_LOW + + + choice_pairs_f669c2f5 + frequency + Time + + + The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. + + + Component_Name + clk_txUsrClk + + + USER_CLK_FREQ0 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ1 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ2 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ3 + User Frequency(MHz) + 100.0 + + + ENABLE_CLOCK_MONITOR + Enable Clock Monitoring + false + + + ENABLE_USER_CLOCK0 + User Clock + false + + + ENABLE_USER_CLOCK1 + User Clock + false + + + ENABLE_USER_CLOCK2 + User Clock + false + + + ENABLE_USER_CLOCK3 + User Clock + false + + + Enable_PLL0 + User Clock + false + + + Enable_PLL1 + User Clock + false + + + REF_CLK_FREQ + Reference Frequency(MHz) + 100.0 + + + PRECISION + Tolerance(MHz) + 1 + + + PRIMITIVE + Primitive + MMCM + + + PRIMTYPE_SEL + Primtype Sel + mmcm_adv + + + CLOCK_MGR_TYPE + Clock Mgr Type + auto + + + USE_FREQ_SYNTH + true + + + USE_SPREAD_SPECTRUM + false + + + USE_PHASE_ALIGNMENT + false + + + USE_MIN_POWER + false + + + USE_DYN_PHASE_SHIFT + false + + + USE_DYN_RECONFIG + false + + + JITTER_SEL + No_Jitter + + + PRIM_IN_FREQ + 100.000 + + + PRIM_IN_TIMEPERIOD + 10.000 + + + IN_FREQ_UNITS + Units_MHz + + + PHASESHIFT_MODE + WAVEFORM + + + IN_JITTER_UNITS + Units_UI + + + RELATIVE_INCLK + REL_PRIMARY + + + USE_INCLK_SWITCHOVER + false + + + SECONDARY_IN_FREQ + 100.000 + + + SECONDARY_IN_TIMEPERIOD + 10.000 + + + SECONDARY_PORT + clk_in2 + + + SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + JITTER_OPTIONS + UI + + + CLKIN1_UI_JITTER + 0.010 + + + CLKIN2_UI_JITTER + 0.010 + + + PRIM_IN_JITTER + 0.010 + + + SECONDARY_IN_JITTER + 0.010 + + + CLKIN1_JITTER_PS + 100.0 + + + CLKIN2_JITTER_PS + 100.0 + + + CLKOUT1_USED + true + + + CLKOUT2_USED + true + + + CLKOUT3_USED + false + + + CLKOUT4_USED + false + + + CLKOUT5_USED + false + + + CLKOUT6_USED + false + + + CLKOUT7_USED + false + + + NUM_OUT_CLKS + 2 + + + CLK_OUT1_USE_FINE_PS_GUI + false + + + CLK_OUT2_USE_FINE_PS_GUI + false + + + CLK_OUT3_USE_FINE_PS_GUI + false + + + CLK_OUT4_USE_FINE_PS_GUI + false + + + CLK_OUT5_USE_FINE_PS_GUI + false + + + CLK_OUT6_USE_FINE_PS_GUI + false + + + CLK_OUT7_USE_FINE_PS_GUI + false + + + PRIMARY_PORT + clk_in1 + + + CLK_OUT1_PORT + clk_out1 + + + CLK_OUT2_PORT + clk_out2 + + + CLK_OUT3_PORT + clk_out3 + + + CLK_OUT4_PORT + clk_out4 + + + CLK_OUT5_PORT + clk_out5 + + + CLK_OUT6_PORT + clk_out6 + + + CLK_OUT7_PORT + clk_out7 + + + DADDR_PORT + daddr + + + DCLK_PORT + dclk + + + DRDY_PORT + drdy + + + DWE_PORT + dwe + + + DIN_PORT + din + + + DOUT_PORT + dout + + + DEN_PORT + den + + + PSCLK_PORT + psclk + + + PSEN_PORT + psen + + + PSINCDEC_PORT + psincdec + + + PSDONE_PORT + psdone + + + CLKOUT1_REQUESTED_OUT_FREQ + 200.000 + + + CLKOUT1_REQUESTED_PHASE + 0.000 + + + CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT2_REQUESTED_PHASE + 0.000 + + + CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT3_REQUESTED_PHASE + 0.000 + + + CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT4_REQUESTED_PHASE + 0.000 + + + CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT5_REQUESTED_PHASE + 0.000 + + + CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT6_REQUESTED_PHASE + 0.000 + + + CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT7_REQUESTED_PHASE + 0.000 + + + CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + USE_MAX_I_JITTER + false + + + USE_MIN_O_JITTER + false + + + CLKOUT1_MATCHED_ROUTING + false + + + CLKOUT2_MATCHED_ROUTING + false + + + CLKOUT3_MATCHED_ROUTING + false + + + CLKOUT4_MATCHED_ROUTING + false + + + CLKOUT5_MATCHED_ROUTING + false + + + CLKOUT6_MATCHED_ROUTING + false + + + CLKOUT7_MATCHED_ROUTING + false + + + PRIM_SOURCE + Single_ended_clock_capable_pin + + + CLKOUT1_DRIVES + Buffer + + + CLKOUT2_DRIVES + Buffer + + + CLKOUT3_DRIVES + Buffer + + + CLKOUT4_DRIVES + Buffer + + + CLKOUT5_DRIVES + Buffer + + + CLKOUT6_DRIVES + Buffer + + + CLKOUT7_DRIVES + Buffer + + + FEEDBACK_SOURCE + FDBK_AUTO + + + CLKFB_IN_SIGNALING + SINGLE + + + CLKFB_IN_PORT + clkfb_in + + + CLKFB_IN_P_PORT + clkfb_in_p + + + CLKFB_IN_N_PORT + clkfb_in_n + + + CLKFB_OUT_PORT + clkfb_out + + + CLKFB_OUT_P_PORT + clkfb_out_p + + + CLKFB_OUT_N_PORT + clkfb_out_n + + + PLATFORM + UNKNOWN + + + SUMMARY_STRINGS + empty + + + USE_LOCKED + true + + + CALC_DONE + empty + + + USE_RESET + true + + + USE_POWER_DOWN + false + + + USE_STATUS + false + + + USE_FREEZE + false + + + USE_CLK_VALID + false + + + USE_INCLK_STOPPED + false + + + USE_CLKFB_STOPPED + false + + + RESET_PORT + reset + + + LOCKED_PORT + locked + + + POWER_DOWN_PORT + power_down + + + CLK_VALID_PORT + CLK_VALID + + + STATUS_PORT + STATUS + + + CLK_IN_SEL_PORT + clk_in_sel + + + INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + CLKFB_STOPPED_PORT + clkfb_stopped + + + SS_MODE + CENTER_HIGH + + + SS_MOD_FREQ + 250 + + + SS_MOD_TIME + 0.004 + + + OVERRIDE_MMCM + false + + + MMCM_NOTES + None + + + MMCM_DIVCLK_DIVIDE + 1 + + + MMCM_BANDWIDTH + OPTIMIZED + + + MMCM_CLKFBOUT_MULT_F + 10.000 + + + MMCM_CLKFBOUT_PHASE + 0.000 + + + MMCM_CLKFBOUT_USE_FINE_PS + false + + + MMCM_CLKIN1_PERIOD + 10.000 + + + MMCM_CLKIN2_PERIOD + 10.000 + + + MMCM_CLKOUT4_CASCADE + false + + + MMCM_CLOCK_HOLD + false + + + MMCM_COMPENSATION + AUTO + + + MMCM_REF_JITTER1 + 0.010 + + + MMCM_REF_JITTER2 + 0.010 + + + MMCM_STARTUP_WAIT + false + + + MMCM_CLKOUT0_DIVIDE_F + 5.000 + + + MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT0_PHASE + 0.000 + + + MMCM_CLKOUT0_USE_FINE_PS + false + + + MMCM_CLKOUT1_DIVIDE + 10 + + + MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT1_PHASE + 0.000 + + + MMCM_CLKOUT1_USE_FINE_PS + false + + + MMCM_CLKOUT2_DIVIDE + 1 + + + MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT2_PHASE + 0.000 + + + MMCM_CLKOUT2_USE_FINE_PS + false + + + MMCM_CLKOUT3_DIVIDE + 1 + + + MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT3_PHASE + 0.000 + + + MMCM_CLKOUT3_USE_FINE_PS + false + + + MMCM_CLKOUT4_DIVIDE + 1 + + + MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT4_PHASE + 0.000 + + + MMCM_CLKOUT4_USE_FINE_PS + false + + + MMCM_CLKOUT5_DIVIDE + 1 + + + MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT5_PHASE + 0.000 + + + MMCM_CLKOUT5_USE_FINE_PS + false + + + MMCM_CLKOUT6_DIVIDE + 1 + + + MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT6_PHASE + 0.000 + + + MMCM_CLKOUT6_USE_FINE_PS + false + + + OVERRIDE_PLL + false + + + PLL_NOTES + None + + + PLL_BANDWIDTH + OPTIMIZED + + + PLL_CLKFBOUT_MULT + 4 + + + PLL_CLKFBOUT_PHASE + 0.000 + + + PLL_CLK_FEEDBACK + CLKFBOUT + + + PLL_DIVCLK_DIVIDE + 1 + + + PLL_CLKIN_PERIOD + 10.000 + + + PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + PLL_REF_JITTER + 0.010 + + + PLL_CLKOUT0_DIVIDE + 1 + + + PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT0_PHASE + 0.000 + + + PLL_CLKOUT1_DIVIDE + 1 + + + PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT1_PHASE + 0.000 + + + PLL_CLKOUT2_DIVIDE + 1 + + + PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT2_PHASE + 0.000 + + + PLL_CLKOUT3_DIVIDE + 1 + + + PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT3_PHASE + 0.000 + + + PLL_CLKOUT4_DIVIDE + 1 + + + PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT4_PHASE + 0.000 + + + PLL_CLKOUT5_DIVIDE + 1 + + + PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT5_PHASE + 0.000 + + + RESET_TYPE + Reset Type + ACTIVE_HIGH + + + USE_SAFE_CLOCK_STARTUP + false + + + USE_CLOCK_SEQUENCING + false + + + CLKOUT1_SEQUENCE_NUMBER + 1 + + + CLKOUT2_SEQUENCE_NUMBER + 1 + + + CLKOUT3_SEQUENCE_NUMBER + 1 + + + CLKOUT4_SEQUENCE_NUMBER + 1 + + + CLKOUT5_SEQUENCE_NUMBER + 1 + + + CLKOUT6_SEQUENCE_NUMBER + 1 + + + CLKOUT7_SEQUENCE_NUMBER + 1 + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + CLK_IN1_BOARD_INTERFACE + Custom + + + CLK_IN2_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN1_BOARD_INTERFACE + Custom + + + DIFF_CLK_IN2_BOARD_INTERFACE + Custom + + + AUTO_PRIMITIVE + MMCM + + + RESET_BOARD_INTERFACE + Custom + + + ENABLE_CDDC + false + + + CDDCDONE_PORT + cddcdone + + + CDDCREQ_PORT + cddcreq + + + ENABLE_CLKOUTPHY + false + + + CLKOUTPHY_REQUESTED_FREQ + 600.000 + + + CLKOUT1_JITTER + Clkout1 Jitter + 114.829 + + + CLKOUT1_PHASE_ERROR + Clkout1 Phase + 98.575 + + + CLKOUT2_JITTER + Clkout2 Jitter + 130.958 + + + CLKOUT2_PHASE_ERROR + Clkout2 Phase + 98.575 + + + CLKOUT3_JITTER + Clkout3 Jitter + 0.0 + + + CLKOUT3_PHASE_ERROR + Clkout3 Phase + 0.0 + + + CLKOUT4_JITTER + Clkout4 Jitter + 0.0 + + + CLKOUT4_PHASE_ERROR + Clkout4 Phase + 0.0 + + + CLKOUT5_JITTER + Clkout5 Jitter + 0.0 + + + CLKOUT5_PHASE_ERROR + Clkout5 Phase + 0.0 + + + CLKOUT6_JITTER + Clkout6 Jitter + 0.0 + + + CLKOUT6_PHASE_ERROR + Clkout6 Phase + 0.0 + + + CLKOUT7_JITTER + Clkout7 Jitter + 0.0 + + + CLKOUT7_PHASE_ERROR + Clkout7 Phase + 0.0 + + + INPUT_MODE + frequency + + + INTERFACE_SELECTION + Enable_AXI + + + AXI_DRP + Write DRP registers + false + + + PHASE_DUTY_CONFIG + Phase Duty Cycle Config + false + + + + + Clocking Wizard + + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.1 + + + + + + + + diff --git a/media_interfaces/xcku/clk_wiz_0/clk_wiz_0.xci b/media_interfaces/xcku/clk_wiz_0/clk_wiz_0.xci new file mode 100644 index 0000000..3e73a58 --- /dev/null +++ b/media_interfaces/xcku/clk_wiz_0/clk_wiz_0.xci @@ -0,0 +1,716 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_0 + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.000 + + + + 100000000 + 0 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 100.0 + 0000 + 0000 + 200.00000 + 0000 + 0000 + 100.00000 + BUFG + 50.0 + false + 200.00000 + 0.000 + 50.000 + 200.000 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 2.0 + 2.0 + 2.0 + 2.0 + 2.0 + 2.0 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________200.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 5.000 + 0.000 + FALSE + 5.000 + 10.0 + 5.000 + 0.500 + 0.000 + FALSE + 10 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 1 + None + 0.010 + 0.010 + FALSE + 64.000 + 2.000 + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out1__200.00000______0.000______50.0_______98.146_____89.971 + clk_out2__100.00000______0.000______50.0______112.316_____89.971 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 200.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1440.000 + 600.000 + clk_wiz_0 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 0.010 + 100.0 + 0.010 + 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C_CLKOUT7_DRIVES + BUFG + + + C_INCLK_SUM_ROW0 + Input Clock Freq (MHz) Input Jitter (UI) + + + C_INCLK_SUM_ROW1 + __primary_________200.000____________0.010 + + + C_INCLK_SUM_ROW2 + no_secondary_input_clock + + + C_OUTCLK_SUM_ROW0A + C Outclk Sum Row0a + Output Output Phase Duty Cycle Pk-to-Pk Phase + + + C_OUTCLK_SUM_ROW0B + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + + + C_OUTCLK_SUM_ROW1 + clk_out1__200.00000______0.000______50.0_______98.146_____89.971 + + + C_OUTCLK_SUM_ROW2 + clk_out2__100.00000______0.000______50.0______112.316_____89.971 + + + C_OUTCLK_SUM_ROW3 + no_CLK_OUT3_output + + + C_OUTCLK_SUM_ROW4 + no_CLK_OUT4_output + + + C_OUTCLK_SUM_ROW5 + no_CLK_OUT5_output + + + C_OUTCLK_SUM_ROW6 + no_CLK_OUT6_output + + + C_OUTCLK_SUM_ROW7 + no_CLK_OUT7_output + + + C_CLKOUT1_REQUESTED_OUT_FREQ + 200.000 + + + C_CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + C_CLKOUT1_REQUESTED_PHASE + 0.000 + + + C_CLKOUT2_REQUESTED_PHASE + 0.000 + + + C_CLKOUT3_REQUESTED_PHASE + 0.000 + + + C_CLKOUT4_REQUESTED_PHASE + 0.000 + + + C_CLKOUT5_REQUESTED_PHASE + 0.000 + + + C_CLKOUT6_REQUESTED_PHASE + 0.000 + + + C_CLKOUT7_REQUESTED_PHASE + 0.000 + + + C_CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + C_CLKOUT1_OUT_FREQ + 200.00000 + + + C_CLKOUT2_OUT_FREQ + 100.00000 + + + C_CLKOUT3_OUT_FREQ + 100.000 + + + C_CLKOUT4_OUT_FREQ + 100.000 + + + C_CLKOUT5_OUT_FREQ + 100.000 + + + C_CLKOUT6_OUT_FREQ + 100.000 + + + C_CLKOUT7_OUT_FREQ + 100.000 + + + C_CLKOUT1_PHASE + 0.000 + + + C_CLKOUT2_PHASE + 0.000 + + + C_CLKOUT3_PHASE + 0.000 + + + C_CLKOUT4_PHASE + 0.000 + + + C_CLKOUT5_PHASE + 0.000 + + + C_CLKOUT6_PHASE + 0.000 + + + C_CLKOUT7_PHASE + 0.000 + + + C_CLKOUT1_DUTY_CYCLE + 50.0 + + + C_CLKOUT2_DUTY_CYCLE + 50.0 + + + C_CLKOUT3_DUTY_CYCLE + 50.000 + + + C_CLKOUT4_DUTY_CYCLE + 50.000 + + + C_CLKOUT5_DUTY_CYCLE + 50.000 + + + C_CLKOUT6_DUTY_CYCLE + 50.000 + + + C_CLKOUT7_DUTY_CYCLE + 50.000 + + + C_USE_SAFE_CLOCK_STARTUP + 0 + + + C_USE_CLOCK_SEQUENCING + 0 + + + C_CLKOUT1_SEQUENCE_NUMBER + 1 + + + C_CLKOUT2_SEQUENCE_NUMBER + 1 + + + C_CLKOUT3_SEQUENCE_NUMBER + 1 + + + C_CLKOUT4_SEQUENCE_NUMBER + 1 + + + C_CLKOUT5_SEQUENCE_NUMBER + 1 + + + C_CLKOUT6_SEQUENCE_NUMBER + 1 + + + C_CLKOUT7_SEQUENCE_NUMBER + 1 + + + C_MMCM_NOTES + None + + + C_MMCM_BANDWIDTH + OPTIMIZED + + + C_MMCM_CLKFBOUT_MULT_F + 5.000 + + + C_MMCM_CLKIN1_PERIOD + 5.000 + + + C_MMCM_CLKIN2_PERIOD + 10.0 + + + C_MMCM_CLKOUT4_CASCADE + FALSE + + + C_MMCM_CLOCK_HOLD + FALSE + + + C_MMCM_COMPENSATION + AUTO + + + C_MMCM_DIVCLK_DIVIDE + 1 + + + C_MMCM_REF_JITTER1 + 0.010 + + + C_MMCM_REF_JITTER2 + 0.010 + + + C_MMCM_STARTUP_WAIT + FALSE + + + C_MMCM_CLKOUT0_DIVIDE_F + 5.000 + + + C_MMCM_CLKOUT1_DIVIDE + 10 + + + C_MMCM_CLKOUT2_DIVIDE + 1 + + + C_MMCM_CLKOUT3_DIVIDE + 1 + + + C_MMCM_CLKOUT4_DIVIDE + 1 + + + C_MMCM_CLKOUT5_DIVIDE + 1 + + + C_MMCM_CLKOUT6_DIVIDE + 1 + + + C_MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + C_MMCM_CLKFBOUT_PHASE + 0.000 + + + C_MMCM_CLKOUT0_PHASE + 0.000 + + + C_MMCM_CLKOUT1_PHASE + 0.000 + + + C_MMCM_CLKOUT2_PHASE + 0.000 + + + C_MMCM_CLKOUT3_PHASE + 0.000 + + + C_MMCM_CLKOUT4_PHASE + 0.000 + + + C_MMCM_CLKOUT5_PHASE + 0.000 + + + C_MMCM_CLKOUT6_PHASE + 0.000 + + + C_MMCM_CLKFBOUT_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT0_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT1_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT2_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT3_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT4_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT5_USE_FINE_PS + FALSE + + + C_MMCM_CLKOUT6_USE_FINE_PS + FALSE + + + C_PLL_NOTES + No notes + + + C_PLL_BANDWIDTH + OPTIMIZED + + + C_PLL_CLK_FEEDBACK + CLKFBOUT + + + C_PLL_CLKFBOUT_MULT + 1 + + + C_PLL_CLKIN_PERIOD + 1.000 + + + C_PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + C_PLL_DIVCLK_DIVIDE + 1 + + + C_PLL_REF_JITTER + 0.010 + + + C_PLL_CLKOUT0_DIVIDE + 1 + + + C_PLL_CLKOUT1_DIVIDE + 1 + + + C_PLL_CLKOUT2_DIVIDE + 1 + + + C_PLL_CLKOUT3_DIVIDE + 1 + + + C_PLL_CLKOUT4_DIVIDE + 1 + + + C_PLL_CLKOUT5_DIVIDE + 1 + + + C_PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + C_PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + C_PLL_CLKFBOUT_PHASE + 0.000 + + + C_PLL_CLKOUT0_PHASE + 0.000 + + + C_PLL_CLKOUT1_PHASE + 0.000 + + + C_PLL_CLKOUT2_PHASE + 0.000 + + + C_PLL_CLKOUT3_PHASE + 0.000 + + + C_PLL_CLKOUT4_PHASE + 0.000 + + + C_PLL_CLKOUT5_PHASE + 0.000 + + + C_CLOCK_MGR_TYPE + NA + + + C_OVERRIDE_MMCM + 0 + + + C_OVERRIDE_PLL + 0 + + + C_PRIMARY_PORT + clk_in1 + + + C_SECONDARY_PORT + clk_in2 + + + C_CLK_OUT1_PORT + clk_out1 + + + C_CLK_OUT2_PORT + clk_out2 + + + C_CLK_OUT3_PORT + clk_out3 + + + C_CLK_OUT4_PORT + clk_out4 + + + C_CLK_OUT5_PORT + clk_out5 + + + C_CLK_OUT6_PORT + clk_out6 + + + C_CLK_OUT7_PORT + clk_out7 + + + C_RESET_PORT + reset + + + C_LOCKED_PORT + locked + + + C_CLKFB_IN_PORT + clkfb_in + + + C_CLKFB_IN_P_PORT + clkfb_in_p + + + C_CLKFB_IN_N_PORT + clkfb_in_n + + + C_CLKFB_OUT_PORT + clkfb_out + + + C_CLKFB_OUT_P_PORT + clkfb_out_p + + + C_CLKFB_OUT_N_PORT + clkfb_out_n + + + C_POWER_DOWN_PORT + power_down + + + C_DADDR_PORT + daddr + + + C_DCLK_PORT + dclk + + + C_DRDY_PORT + drdy + + + C_DWE_PORT + dwe + + + C_DIN_PORT + din + + + C_DOUT_PORT + dout + + + C_DEN_PORT + den + + + C_PSCLK_PORT + psclk + + + C_PSEN_PORT + psen + + + C_PSINCDEC_PORT + psincdec + + + C_PSDONE_PORT + psdone + + + C_CLK_VALID_PORT + CLK_VALID + + + C_STATUS_PORT + STATUS + + + C_CLK_IN_SEL_PORT + clk_in_sel + + + C_INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + C_CLKFB_STOPPED_PORT + clkfb_stopped + + + C_CLKIN1_JITTER_PS + 50.0 + + + C_CLKIN2_JITTER_PS + 100.0 + + + C_PRIMITIVE + MMCM + + + C_SS_MODE + CENTER_HIGH + + + C_SS_MOD_PERIOD + 4000 + + + C_SS_MOD_TIME + 0.004 + + + C_HAS_CDDC + 0 + + + C_CDDCDONE_PORT + cddcdone + + + C_CDDCREQ_PORT + cddcreq + + + C_CLKOUTPHY_MODE + VCO + + + C_ENABLE_CLKOUTPHY + 0 + + + C_INTERFACE_SELECTION + 0 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 11 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_POWER_REG + 0000 + + + C_CLKOUT0_1 + 0000 + + + C_CLKOUT0_2 + 0000 + + + C_CLKOUT1_1 + 0000 + + + C_CLKOUT1_2 + 0000 + + + C_CLKOUT2_1 + 0000 + + + C_CLKOUT2_2 + 0000 + + + C_CLKOUT3_1 + 0000 + + + C_CLKOUT3_2 + 0000 + + + C_CLKOUT4_1 + 0000 + + + C_CLKOUT4_2 + 0000 + + + C_CLKOUT5_1 + 0000 + + + C_CLKOUT5_2 + 0000 + + + C_CLKOUT6_1 + 0000 + + + C_CLKOUT6_2 + 0000 + + + C_CLKFBOUT_1 + 0000 + + + C_CLKFBOUT_2 + 0000 + + + C_DIVCLK + 0000 + + + C_LOCK_1 + 0000 + + + C_LOCK_2 + 0000 + + + C_LOCK_3 + 0000 + + + C_FILTER_1 + 0000 + + + C_FILTER_2 + 0000 + + + C_DIVIDE1_AUTO + 1 + + + C_DIVIDE2_AUTO + 2.0 + + + C_DIVIDE3_AUTO + 2.0 + + + C_DIVIDE4_AUTO + 2.0 + + + C_DIVIDE5_AUTO + 2.0 + + + C_DIVIDE6_AUTO + 2.0 + + + C_DIVIDE7_AUTO + 2.0 + + + C_PLLBUFGCEDIV + false + + + C_MMCMBUFGCEDIV + false + + + C_PLLBUFGCEDIV1 + false + + + C_PLLBUFGCEDIV2 + false + + + C_PLLBUFGCEDIV3 + false + + + C_PLLBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV1 + false + + + C_MMCMBUFGCEDIV2 + false + + + C_MMCMBUFGCEDIV3 + false + + + C_MMCMBUFGCEDIV4 + false + + + C_MMCMBUFGCEDIV5 + false + + + C_MMCMBUFGCEDIV6 + false + + + C_MMCMBUFGCEDIV7 + false + + + C_CLKOUT1_MATCHED_ROUTING + false + + + C_CLKOUT2_MATCHED_ROUTING + false + + + C_CLKOUT3_MATCHED_ROUTING + false + + + C_CLKOUT4_MATCHED_ROUTING + false + + + C_CLKOUT5_MATCHED_ROUTING + false + + + C_CLKOUT6_MATCHED_ROUTING + false + + + C_CLKOUT7_MATCHED_ROUTING + false + + + C_CLKOUT0_ACTUAL_FREQ + 200.00000 + + + C_CLKOUT1_ACTUAL_FREQ + 100.00000 + + + C_CLKOUT2_ACTUAL_FREQ + 100.000 + + + C_CLKOUT3_ACTUAL_FREQ + 100.000 + + + C_CLKOUT4_ACTUAL_FREQ + 100.000 + + + C_CLKOUT5_ACTUAL_FREQ + 100.000 + + + C_CLKOUT6_ACTUAL_FREQ + 100.000 + + + C_M_MAX + 64.000 + + + C_M_MIN + 2.000 + + + C_D_MAX + 93.000 + + + C_D_MIN + 1.000 + + + C_O_MAX + 128.000 + + + C_O_MIN + 1.000 + + + C_VCO_MIN + 600.000 + + + C_VCO_MAX + 1440.000 + + + + + + choice_list_1d3de01d + WAVEFORM + LATENCY + + + choice_list_876bfc32 + UI + PS + + + choice_list_a9bdfce0 + LOW + HIGH + OPTIMIZED + + + choice_list_ac75ef1e + Custom + + + choice_list_b9d38208 + CLKFBOUT + CLKOUT0 + + + choice_list_d0ea4aeb + MMCM + PLL + Auto + + + choice_pairs_035ca1c3 + SYSTEM_SYNCHRONOUS + SOURCE_SYNCHRONOUS + INTERNAL + EXTERNAL + + + choice_pairs_0920eb1b + Custom + sys_diff_clock + + + choice_pairs_11d71346 + Single_ended_clock_capable_pin + Differential_clock_capable_pin + Global_buffer + No_buffer + + + choice_pairs_15c806d5 + FDBK_AUTO + FDBK_AUTO_OFFCHIP + FDBK_ONCHIP + FDBK_OFFCHIP + + + choice_pairs_340369e0 + Custom + sys_clock + sys_diff_clock + + + choice_pairs_39d99e50 + Buffer + Buffer_with_CE + BUFG + BUFGCE + BUFGCE_DIV + No_buffer + + + choice_pairs_3c2d3ec7 + SINGLE + DIFF + + + choice_pairs_77d3d587 + MMCM + PLL + BUFGCE_DIV + + + choice_pairs_8b28f1f7 + Enable_AXI + Enable_DRP + + + choice_pairs_8eea9b32 + Units_MHz + Units_ns + + + choice_pairs_94e02745 + AUTO + EXTERNAL + INTERNAL + BUF_IN + ZHOLD + + + choice_pairs_a4fbc00c + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a8642b4c + No_Jitter + Min_O_Jitter + Max_I_Jitter + + + choice_pairs_c5ef7212 + Units_UI + Units_ps + + + choice_pairs_e1c87518 + REL_PRIMARY + REL_SECONDARY + + + choice_pairs_f4e10086 + CENTER_HIGH + CENTER_LOW + DOWN_HIGH + DOWN_LOW + + + choice_pairs_f669c2f5 + frequency + Time + + + The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements. + + + Component_Name + clk_wiz_0 + + + USER_CLK_FREQ0 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ1 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ2 + User Frequency(MHz) + 100.0 + + + USER_CLK_FREQ3 + User Frequency(MHz) + 100.0 + + + ENABLE_CLOCK_MONITOR + Enable Clock Monitoring + false + + + ENABLE_USER_CLOCK0 + User Clock + false + + + ENABLE_USER_CLOCK1 + User Clock + false + + + ENABLE_USER_CLOCK2 + User Clock + false + + + ENABLE_USER_CLOCK3 + User Clock + false + + + Enable_PLL0 + User Clock + false + + + Enable_PLL1 + User Clock + false + + + REF_CLK_FREQ + Reference Frequency(MHz) + 100.0 + + + PRECISION + Tolerance(MHz) + 1 + + + PRIMITIVE + Primitive + MMCM + + + PRIMTYPE_SEL + Primtype Sel + mmcm_adv + + + CLOCK_MGR_TYPE + Clock Mgr Type + auto + + + USE_FREQ_SYNTH + true + + + USE_SPREAD_SPECTRUM + false + + + USE_PHASE_ALIGNMENT + false + + + USE_MIN_POWER + false + + + USE_DYN_PHASE_SHIFT + false + + + USE_DYN_RECONFIG + false + + + JITTER_SEL + No_Jitter + + + PRIM_IN_FREQ + 200.000 + + + PRIM_IN_TIMEPERIOD + 10.000 + + + IN_FREQ_UNITS + Units_MHz + + + PHASESHIFT_MODE + WAVEFORM + + + IN_JITTER_UNITS + Units_UI + + + RELATIVE_INCLK + REL_PRIMARY + + + USE_INCLK_SWITCHOVER + false + + + SECONDARY_IN_FREQ + 100.000 + + + SECONDARY_IN_TIMEPERIOD + 10.000 + + + SECONDARY_PORT + clk_in2 + + + SECONDARY_SOURCE + Single_ended_clock_capable_pin + + + JITTER_OPTIONS + UI + + + CLKIN1_UI_JITTER + 0.010 + + + CLKIN2_UI_JITTER + 0.010 + + + PRIM_IN_JITTER + 0.010 + + + SECONDARY_IN_JITTER + 0.010 + + + CLKIN1_JITTER_PS + 50.0 + + + CLKIN2_JITTER_PS + 100.0 + + + CLKOUT1_USED + true + + + CLKOUT2_USED + true + + + CLKOUT3_USED + false + + + CLKOUT4_USED + false + + + CLKOUT5_USED + false + + + CLKOUT6_USED + false + + + CLKOUT7_USED + false + + + NUM_OUT_CLKS + 2 + + + CLK_OUT1_USE_FINE_PS_GUI + false + + + CLK_OUT2_USE_FINE_PS_GUI + false + + + CLK_OUT3_USE_FINE_PS_GUI + false + + + CLK_OUT4_USE_FINE_PS_GUI + false + + + CLK_OUT5_USE_FINE_PS_GUI + false + + + CLK_OUT6_USE_FINE_PS_GUI + false + + + CLK_OUT7_USE_FINE_PS_GUI + false + + + PRIMARY_PORT + clk_in1 + + + CLK_OUT1_PORT + clk_out1 + + + CLK_OUT2_PORT + clk_out2 + + + CLK_OUT3_PORT + clk_out3 + + + CLK_OUT4_PORT + clk_out4 + + + CLK_OUT5_PORT + clk_out5 + + + CLK_OUT6_PORT + clk_out6 + + + CLK_OUT7_PORT + clk_out7 + + + DADDR_PORT + daddr + + + DCLK_PORT + dclk + + + DRDY_PORT + drdy + + + DWE_PORT + dwe + + + DIN_PORT + din + + + DOUT_PORT + dout + + + DEN_PORT + den + + + PSCLK_PORT + psclk + + + PSEN_PORT + psen + + + PSINCDEC_PORT + psincdec + + + PSDONE_PORT + psdone + + + CLKOUT1_REQUESTED_OUT_FREQ + 200.000 + + + CLKOUT1_REQUESTED_PHASE + 0.000 + + + CLKOUT1_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT2_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT2_REQUESTED_PHASE + 0.000 + + + CLKOUT2_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT3_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT3_REQUESTED_PHASE + 0.000 + + + CLKOUT3_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT4_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT4_REQUESTED_PHASE + 0.000 + + + CLKOUT4_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT5_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT5_REQUESTED_PHASE + 0.000 + + + CLKOUT5_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT6_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT6_REQUESTED_PHASE + 0.000 + + + CLKOUT6_REQUESTED_DUTY_CYCLE + 50.000 + + + CLKOUT7_REQUESTED_OUT_FREQ + 100.000 + + + CLKOUT7_REQUESTED_PHASE + 0.000 + + + CLKOUT7_REQUESTED_DUTY_CYCLE + 50.000 + + + USE_MAX_I_JITTER + false + + + USE_MIN_O_JITTER + false + + + CLKOUT1_MATCHED_ROUTING + false + + + CLKOUT2_MATCHED_ROUTING + false + + + CLKOUT3_MATCHED_ROUTING + false + + + CLKOUT4_MATCHED_ROUTING + false + + + CLKOUT5_MATCHED_ROUTING + false + + + CLKOUT6_MATCHED_ROUTING + false + + + CLKOUT7_MATCHED_ROUTING + false + + + PRIM_SOURCE + Differential_clock_capable_pin + + + CLKOUT1_DRIVES + Buffer + + + CLKOUT2_DRIVES + Buffer + + + CLKOUT3_DRIVES + Buffer + + + CLKOUT4_DRIVES + Buffer + + + CLKOUT5_DRIVES + Buffer + + + CLKOUT6_DRIVES + Buffer + + + CLKOUT7_DRIVES + Buffer + + + FEEDBACK_SOURCE + FDBK_AUTO + + + CLKFB_IN_SIGNALING + SINGLE + + + CLKFB_IN_PORT + clkfb_in + + + CLKFB_IN_P_PORT + clkfb_in_p + + + CLKFB_IN_N_PORT + clkfb_in_n + + + CLKFB_OUT_PORT + clkfb_out + + + CLKFB_OUT_P_PORT + clkfb_out_p + + + CLKFB_OUT_N_PORT + clkfb_out_n + + + PLATFORM + UNKNOWN + + + SUMMARY_STRINGS + empty + + + USE_LOCKED + true + + + CALC_DONE + empty + + + USE_RESET + true + + + USE_POWER_DOWN + false + + + USE_STATUS + false + + + USE_FREEZE + false + + + USE_CLK_VALID + false + + + USE_INCLK_STOPPED + false + + + USE_CLKFB_STOPPED + false + + + RESET_PORT + reset + + + LOCKED_PORT + locked + + + POWER_DOWN_PORT + power_down + + + CLK_VALID_PORT + CLK_VALID + + + STATUS_PORT + STATUS + + + CLK_IN_SEL_PORT + clk_in_sel + + + INPUT_CLK_STOPPED_PORT + input_clk_stopped + + + CLKFB_STOPPED_PORT + clkfb_stopped + + + SS_MODE + CENTER_HIGH + + + SS_MOD_FREQ + 250 + + + SS_MOD_TIME + 0.004 + + + OVERRIDE_MMCM + false + + + MMCM_NOTES + None + + + MMCM_DIVCLK_DIVIDE + 1 + + + MMCM_BANDWIDTH + OPTIMIZED + + + MMCM_CLKFBOUT_MULT_F + 5.000 + + + MMCM_CLKFBOUT_PHASE + 0.000 + + + MMCM_CLKFBOUT_USE_FINE_PS + false + + + MMCM_CLKIN1_PERIOD + 5.000 + + + MMCM_CLKIN2_PERIOD + 10.0 + + + MMCM_CLKOUT4_CASCADE + false + + + MMCM_CLOCK_HOLD + false + + + MMCM_COMPENSATION + AUTO + + + MMCM_REF_JITTER1 + 0.010 + + + MMCM_REF_JITTER2 + 0.010 + + + MMCM_STARTUP_WAIT + false + + + MMCM_CLKOUT0_DIVIDE_F + 5.000 + + + MMCM_CLKOUT0_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT0_PHASE + 0.000 + + + MMCM_CLKOUT0_USE_FINE_PS + false + + + MMCM_CLKOUT1_DIVIDE + 10 + + + MMCM_CLKOUT1_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT1_PHASE + 0.000 + + + MMCM_CLKOUT1_USE_FINE_PS + false + + + MMCM_CLKOUT2_DIVIDE + 1 + + + MMCM_CLKOUT2_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT2_PHASE + 0.000 + + + MMCM_CLKOUT2_USE_FINE_PS + false + + + MMCM_CLKOUT3_DIVIDE + 1 + + + MMCM_CLKOUT3_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT3_PHASE + 0.000 + + + MMCM_CLKOUT3_USE_FINE_PS + false + + + MMCM_CLKOUT4_DIVIDE + 1 + + + MMCM_CLKOUT4_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT4_PHASE + 0.000 + + + MMCM_CLKOUT4_USE_FINE_PS + false + + + MMCM_CLKOUT5_DIVIDE + 1 + + + MMCM_CLKOUT5_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT5_PHASE + 0.000 + + + MMCM_CLKOUT5_USE_FINE_PS + false + + + MMCM_CLKOUT6_DIVIDE + 1 + + + MMCM_CLKOUT6_DUTY_CYCLE + 0.500 + + + MMCM_CLKOUT6_PHASE + 0.000 + + + MMCM_CLKOUT6_USE_FINE_PS + false + + + OVERRIDE_PLL + false + + + PLL_NOTES + None + + + PLL_BANDWIDTH + OPTIMIZED + + + PLL_CLKFBOUT_MULT + 4 + + + PLL_CLKFBOUT_PHASE + 0.000 + + + PLL_CLK_FEEDBACK + CLKFBOUT + + + PLL_DIVCLK_DIVIDE + 1 + + + PLL_CLKIN_PERIOD + 10.000 + + + PLL_COMPENSATION + SYSTEM_SYNCHRONOUS + + + PLL_REF_JITTER + 0.010 + + + PLL_CLKOUT0_DIVIDE + 1 + + + PLL_CLKOUT0_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT0_PHASE + 0.000 + + + PLL_CLKOUT1_DIVIDE + 1 + + + PLL_CLKOUT1_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT1_PHASE + 0.000 + + + PLL_CLKOUT2_DIVIDE + 1 + + + PLL_CLKOUT2_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT2_PHASE + 0.000 + + + PLL_CLKOUT3_DIVIDE + 1 + + + PLL_CLKOUT3_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT3_PHASE + 0.000 + + + PLL_CLKOUT4_DIVIDE + 1 + + + PLL_CLKOUT4_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT4_PHASE + 0.000 + + + PLL_CLKOUT5_DIVIDE + 1 + + + PLL_CLKOUT5_DUTY_CYCLE + 0.500 + + + PLL_CLKOUT5_PHASE + 0.000 + + + RESET_TYPE + Reset Type + ACTIVE_HIGH + + + USE_SAFE_CLOCK_STARTUP + false + + + USE_CLOCK_SEQUENCING + false + + + CLKOUT1_SEQUENCE_NUMBER + 1 + + + CLKOUT2_SEQUENCE_NUMBER + 1 + + + CLKOUT3_SEQUENCE_NUMBER + 1 + + + CLKOUT4_SEQUENCE_NUMBER + 1 + + + CLKOUT5_SEQUENCE_NUMBER + 1 + + + CLKOUT6_SEQUENCE_NUMBER + 1 + + + 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GTH-CPRI_10_1G + GTH-CPRI_3G + GTH-CPRI_6G + GTH-DisplayPort_1_62G + GTH-DisplayPort_2_7G + GTH-DisplayPort_5_4G + GTH-Gigabit_Ethernet + GTH-HDMI + GTH-HD_SDI + GTH-HMC_12_5G + GTH-Interlaken_10G + GTH-Interlaken_12_5G + GTH-Interlaken_6_25G + GTH-JESD204 + GTH-JESD204_3_125G + GTH-JESD204_6_375G + GTH-OTL4_10 + GTH-OTU2 + GTH-OTU2e + GTH-QSGMII + GTH-RXAUI + GTH-SATA + GTH-SRIO_Gen2 + GTH-XAUI + GTH-XLAUI + + + choice_pairs_40d02874 + 10GBASE_KR + CUSTOM + PCIE_GEN1_GEN2 + PCIE_GEN3 + QPI + + + choice_pairs_4e550952 + NONE + EXAMPLE_DESIGN + + + choice_pairs_7b0c3758 + RX + BOTH + TX + + + choice_pairs_85f99b7f + K28.1 + K28.5 + NONE + + + choice_pairs_8846c8f0 + RAW + 8B10B + 64B66B + 64B66B_CAUI + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_88c85933 + 8B10B + 64B66B_ASYNC + 64B66B_ASYNC_CAUI + RAW + 64B66B + 64B66B_CAUI + 64B67B + 64B67B_CAUI + + + choice_pairs_93c2d4ee + CORE + EXAMPLE_DESIGN + + + choice_pairs_9c19f015 + 1 + 2 + + + choice_pairs_a537ddda + 0 + 1 + + + choice_pairs_aa541099 + AUTO + DFE + LPM + + + choice_pairs_ae574462 + OFF + PCS + PMA + AUTO + + + choice_pairs_b0974ef0 + 1 + 2 + 0 + + + choice_pairs_d4feb97d + DISABLE + ENABLE + + + choice_pairs_f05b8192 + CHANNEL + NAME + + + The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. + + + GT_TYPE + Transceiver type + For devices which contain more than one serial transceiver type, select the type of transceiver to configure + GTH + + + INTERNAL_GT_PRIM_TYPE + gthe3 + + + + false + + + + + + GT_REV + Transceiver revision + Select the serial transceiver silicon revision + 0 + + + GT_DIRECTION + Transmit and/or Receive direction + Enable transmit and/or receive + BOTH + + + RX_ENABLE + Enabled + Enable the receiver for use + true + + + + false + + + + + + TX_ENABLE + Enabled + Enable the transmitter for use + true + + + + false + + + + + + CHANNEL_ENABLE + Enable channel + Indicate whether this transceiver channel is instantiated and enabled for use + X0Y8 + + + TX_MASTER_CHANNEL + Master TX channel + Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) + X0Y8 + + + + false + + + + + + RX_MASTER_CHANNEL + Master RX channel + Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) + X0Y8 + + + + false + + + + + + INTERNAL_TOTAL_NUM_CHANNELS + Total number of channels + 1 + + + + false + + + + + + INTERNAL_TOTAL_NUM_COMMONS + Total number of commons required + 1 + + + + false + + + + + + LOCATE_COMMON + Include transceiver COMMON in the + If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. + CORE + + + INTERNAL_NUM_COMMONS_CORE + Number of commons in core + 1 + + + + false + + + + + + INTERNAL_NUM_COMMONS_EXAMPLE + Number of commons in example + 0 + + + + false + + + + + + INTERNAL_TX_USRCLK_FREQUENCY + 100.0000000 + + + + false + + + + + + INTERNAL_RX_USRCLK_FREQUENCY + 100.0000000 + + + + false + + + + + + RX_PPM_OFFSET + PPM offset between receiver and transmitter + Specify the PPM offset between received data and transmitted data + 0 + + + OOB_ENABLE + Enable Out of Band signaling (OOB)/Electrical Idle + Enable or disable Out of Band signaling (OOB)/Electrical Idle + false + + + + false + + + + + + RX_SSC_PPM + Spread spectrum clocking + Specify the spread spectrum clocking modulation in PPM + 0 + + + INS_LOSS_NYQ + Insertion loss at Nyquist (dB) + Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB + 20 + + + PCIE_CORECLK_FREQ + 250 + + + PCIE_USERCLK_FREQ + 250 + + + TX_LINE_RATE + Line rate (Gb/s) + Enter the transmitter line rate in Gb/s + 2 + + + TX_PLL_TYPE + PLL type + Select the transmitter PLL type + QPLL0 + + + TX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type + 125 + + + TX_DATA_ENCODING + Encoding + Select the encoding format for data transmission, or choose 'Raw' for no data encoding + 8B10B + + + TX_USER_DATA_WIDTH + User data width + Select the width at which the user logic will provide parallel data to the serial transceiver for transmission + 16 + + + TX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal transmitter data path + 20 + + + TX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the transmitter buffer + 1 + + + TX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection + 0 + + + + false + + + + + + TX_OUTCLK_SOURCE + TXOUTCLK source + Select the source of TXOUTCLK + TXOUTCLKPMA + + + TX_DIFF_SWING_EMPH_MODE + Differential swing and emphasis mode + Select the transmitter differential swing and emphasis mode for your application + CUSTOM + + + RX_LINE_RATE + Line rate (Gb/s) + Enter the receiver line rate in Gb/s + 2 + + + RX_PLL_TYPE + PLL type + Select the receiver PLL type + QPLL0 + + + RX_REFCLK_FREQUENCY + Actual Reference clock (MHz) + Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type + 125 + + + RX_DATA_DECODING + Decoding + Select the decoding format for data reception, or choose 'Raw' for no data decoding + 8B10B + + + RX_USER_DATA_WIDTH + User data width + Select the width at which the serial transceiver will provide received parallel data to the user logic + 16 + + + RX_INT_DATA_WIDTH + Internal data width + Select the width of the serial transceiver internal receiver data path + 20 + + + RX_BUFFER_MODE + Buffer + Select whether to enable or to bypass the receiver elastic buffer + 1 + + + RX_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection + 0 + + + + false + + + + + + RX_EQ_MODE + Equalization mode + Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. + AUTO + + + RX_JTOL_FC + Mask corner frequency (MHz) + Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. + 1.19976 + + + RX_JTOL_LF_SLOPE + Mask low frequency slope (dB/decade) + Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. + -20 + + + RX_OUTCLK_SOURCE + RXOUTCLK source + Select the source of RXOUTCLK + RXOUTCLKPMA + + + SIM_CPLL_CAL_BYPASS + 1 + + + PCIE_ENABLE + false + + + RX_TERMINATION + Termination + Select the receiver termination + PROGRAMMABLE + + + RX_TERMINATION_PROG_VALUE + Programmable termination voltage (mV) + Select the termination voltage (in mV) when in programmable mode + 800 + + + RX_COUPLING + Link coupling + Select the link coupling + AC + + + RX_BUFFER_BYPASS_MODE + Receiver elastic buffer bypass mode + Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode + MULTI + + + + false + + + + + + RX_BUFFER_RESET_ON_CB_CHANGE + Reset receiver elastic buffer on channel bonding change + Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL + ENABLE + + + + false + + + + + + RX_BUFFER_RESET_ON_COMMAALIGN + Reset receiver elastic buffer on comma alignment + Control whether the receiver elastic buffer is reset on comma alignment + DISABLE + + + RX_BUFFER_RESET_ON_RATE_CHANGE + Reset receiver elastic buffer on rate change + Control whether the receiver elastic buffer is reset on rate change + ENABLE + + + TX_BUFFER_RESET_ON_RATE_CHANGE + Reset transmitter buffer on rate change + Control whether the transmitter buffer is reset on rate change + ENABLE + + + RESET_SEQUENCE_INTERVAL + Reset sequence time interval (ns) + Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval + 0 + + + RX_COMMA_PRESET + Comma value preset + K28.5 + + + RX_COMMA_VALID_ONLY + Valid comma values for 8B/10B decoding + Select the range of comma characters decoded by the 8B/10B decoder + 0 + + + RX_COMMA_P_ENABLE + Detect plus comma + Indicate whether or not the specified bit pattern is detected as a plus comma + true + + + RX_COMMA_M_ENABLE + Detect minus comma + Indicate whether or not the specified bit pattern is detected as a minus comma + true + + + RX_COMMA_DOUBLE_ENABLE + Detect combined plus/minus (double-length) comma + Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence + false + + + RX_COMMA_P_VAL + Plus comma value + Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received + 1010000011 + + + RX_COMMA_M_VAL + Minus comma value + Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received + 0101111100 + + + RX_COMMA_MASK + Mask + Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" + 0011111111 + + + RX_COMMA_ALIGN_WORD + Alignment boundary + Select which data byte boundaries are allowed for comma alignment + 1 + + + RX_COMMA_SHOW_REALIGN_ENABLE + Show realign comma + Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency + true + + + RX_SLIDE_MODE + Manual alignment (RXSLIDE) mode + Select whether to enable manual alignment, and in what mode if enabled + OFF + + + RX_CB_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable channel bonding, and how many sequences to use if enabled + 0 + + + + false + + + + + + RX_CB_LEN_SEQ + Length of each sequence + Select the number of characters in each channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_SKEW + Sequence maximum skew + Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence + 1 + + + + false + + + + + + RX_CB_MAX_LEVEL + Maximum channel bonding level to be used + Select the maximum channel bonding level that will be used in the system channel bonding topology + 1 + + + + false + + + + + + RX_CB_MASK + 00000000 + + + + false + + + + + + RX_CB_VAL + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + + + + false + + + + + + RX_CB_K + 00000000 + + + + false + + + + + + RX_CB_DISP + 00000000 + + + + false + + + + + + RX_CB_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_0_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_0_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_0 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_0 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_1 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_1 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_2 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_2 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CB_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence + false + + + + false + + + + + + RX_CB_VAL_1_3 + Value + Specify the value for this channel bonding sequence and pattern + 00000000 + + + + false + + + + + + RX_CB_K_1_3 + K character + Indicate whether or not the corresponding channel bonding value is a K character + false + + + + false + + + + + + RX_CB_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_NUM_SEQ + Enable and select number of sequences to use + Select whether to enable clock correction, and how many sequences to use if enabled + 2 + + + RX_CC_LEN_SEQ + Length of each sequence + Select the number of characters in each channel clock correction sequence + 2 + + + RX_CC_PERIODICITY + Periodicity of the sequence (in bytes) + Specify the separation between clock correction sequences, in bytes + 5000 + + + RX_CC_KEEP_IDLE + Keep idle + Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received + DISABLE + + + RX_CC_PRECEDENCE + Precedence + Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time + ENABLE + + + + false + + + + + + RX_CC_REPEAT_WAIT + Minimum repetition + Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction + 0 + + + RX_CC_MASK + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + 00000000 + + + + false + + + + + + RX_CC_VAL + 00000000000000000000001011110000010100000000000000000000000000101111000001010000 + + + RX_CC_K + 00100010 + + + + false + + + + + + RX_CC_DISP + 00110000 + + + + false + + + + + + RX_CC_MASK_0_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_0 + Value + Specify the value for this clock correction sequence and pattern + 01010000 + + + RX_CC_K_0_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_0_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_0_1 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_0_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_0_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + RX_CC_MASK_0_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_0_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_0_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_0_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_0_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_0 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_0 + Value + Specify the value for this clock correction sequence and pattern + 01010000 + + + RX_CC_K_1_0 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + RX_CC_DISP_1_0 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + true + + + RX_CC_MASK_1_1 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + RX_CC_VAL_1_1 + Value + Specify the value for this clock correction sequence and pattern + 10111100 + + + RX_CC_K_1_1 + K character + Indicate whether or not the corresponding clock correction value is a K character + true + + + RX_CC_DISP_1_1 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + true + + + RX_CC_MASK_1_2 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_2 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_2 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_2 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + RX_CC_MASK_1_3 + Don't care + Mark this pattern "don't care" to always consider it as a match within a clock correction sequence + false + + + + false + + + + + + RX_CC_VAL_1_3 + Value + Specify the value for this clock correction sequence and pattern + 00000000 + + + + false + + + + + + RX_CC_K_1_3 + K character + Indicate whether or not the corresponding clock correction value is a K character + false + + + + false + + + + + + RX_CC_DISP_1_3 + Inverted disparity + Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error + false + + + + false + + + + + + ENABLE_OPTIONAL_PORTS + Enable optional ports + Indicate whether a port should be included + + + + RX_REFCLK_SOURCE + Receiver reference clock source + Select a reference clock input to drive the PLL chosen for receiver operation + + + + TX_REFCLK_SOURCE + Transmitter reference clock source + Select a reference clock input to drive the PLL chosen for transmitter operation + + + + RX_RECCLK_OUTPUT + Drive recovered clock out of device + Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use + + + + LOCATE_RESET_CONTROLLER + Include reset controller in the + Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + LOCATE_TX_BUFFER_BYPASS_CONTROLLER + Include transmitter buffer bypass controller in the + If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_RX_BUFFER_BYPASS_CONTROLLER + Include receiver elastic buffer bypass controller in the + If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + + false + + + + + + LOCATE_IN_SYSTEM_IBERT_CORE + Include In-System IBERT core + Indicate whether or not the In-System IBERT core should be instantiated in the example design. + NONE + + + LOCATE_TX_USER_CLOCKING + Include simple transmitter user clocking network in the + Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_RX_USER_CLOCKING + Include simple receiver user clocking network in the + Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. + EXAMPLE_DESIGN + + + LOCATE_USER_DATA_WIDTH_SIZING + Include user data width sizing in the + Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. + CORE + + + ORGANIZE_PORTS_BY + In the example design, organize ports across multiple channels by + If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) + NAME + + + + false + + + + + + PRESET + Transceiver configuration preset + You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard + None + + + INTERNAL_PRESET + Transceiver configuration preset + None + + + INTERNAL_PORT_USAGE_UPDATED + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLEMENT_UPDATED + 12 + + + + false + + + + + + INTERNAL_CHANNEL_SITES_UPDATED + 3 + + + + false + + + + + + INTERNAL_CHANNEL_COLUMN_LOC_MAX + 96 + + + + false + + + + + + INTERNAL_RX_COMMA_PRESET_UPDATE + 10 + + + + false + + + + + + INTERNAL_UPDATE_IP_SYMBOL_drpclk_in + false + + + + false + + + + + + SECONDARY_QPLL_ENABLE + Enable secondary QPLL + Enable and configure the QPLL which is not used in this core configuration + false + + + SECONDARY_QPLL_LINE_RATE + Line rate of second core (Gb/s) + Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL + 10.3125 + + + + false + + + + + + SECONDARY_QPLL_FRACN_NUMERATOR + Fractional part of QPLL feedback divider + For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection + 0 + + + + false + + + + + + SECONDARY_QPLL_REFCLK_FREQUENCY + Actual Reference clock frequency (MHz) + Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate + 257.8125 + + + + false + + + + + + TXPROGDIV_FREQ_ENABLE + Enable selectable TXOUTCLK frequency + Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency + false + + + + false + + + + + + TXPROGDIV_FREQ_SOURCE + Programmable divider clock source + Select which PLL source is used to generate the selectable TXOUTCLK frequency + QPLL0 + + + + false + + + + + + TXPROGDIV_FREQ_VAL + TXOUTCLK frequency (MHz) + Select the TXOUTCLK frequency to be generated by the TX programmable divider + 100 + + + + false + + + + + + SATA_TX_BURST_LEN + TX COM sequence burst length + Select the number of bursts that make up a SATA COM sequence + 15 + + + FREERUN_FREQUENCY + Free-running and DRP clock frequency (MHz) + Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface + 100 + + + INCLUDE_CPLL_CAL + 2 + + + USER_GTPOWERGOOD_DELAY_EN + Select 1 to enable powergood delay circuit + 1 + + + DISABLE_LOC_XDC + Select to disable generation of LOC constraints in xdc + 0 + + + ENABLE_COMMON_USRCLK + 0 + + + USB_ENABLE + false + + + PCIE_64BIT + false + + + PCIE_GEN4_EIOS + false + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGBYPASSB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGMONITORENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGPDB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK00_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0PD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1PD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1RESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD2_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD3_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLRSVD4_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RCALENB_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0DATA_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0WIDTH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1DATA_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1RESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1WIDTH_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONGPI_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONPOWERUP_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONRESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBDO_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBDRDY_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBENABLE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBGPI_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBINTR_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBIOLMBRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMBRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMREGEN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMTCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMTDI_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONGPO_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TCONRSVDOUT0_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBDADDR_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBDEN_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBDI_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBDWE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBMDMTDO_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_UBTXUART_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CDRSTEPDIR_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CDRSTEPSQ_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CDRSTEPSX_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CFGRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CLKRSVD0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CLKRSVD1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLFREQLOCK_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLLOCKDETCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLLOCKEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLPD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLREFCLKSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_CPLLRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DMONFIFORESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DMONITORCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPADDR_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPDI_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPRST_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_DRPWE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_ELPCALDVORWREN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_ELPCALPAORWREN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHICALDONE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANMODE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANRESET_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_FREQOS_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTGREFCLK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTHRXN_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTHRXP_IN + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTNORTHREFCLK1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTREFCLK1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTRESETSEL_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTRSVD_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTRXRESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTRXRESETSEL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK0_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTTXRESET_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_INCPCTRL_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTYRXN_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_GTYRXP_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_LOOPBACK_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_LOOPRSVD_IN + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_LPBKRXTXSEREN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_LPBKTXRXSEREN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIEEQRXEQADAPTDONE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERSTIDLE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIERSTTXSYNCSTART_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCIEUSERRATEDONE_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCSRSVDIN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PCSRSVDIN2_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_PMARSVDIN_IN + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_QPLL0CLK_IN + -1 + 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INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPRBSERR_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXQPISENN_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXQPISENP_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRATEDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSTATUS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_RXVALID_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDCCDONE_OUT + -1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXOUTCLK_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT + 1 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXQPISENN_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXQPISENP_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXRATEDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXRESETDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT + 0 + + + + false + + + + + + INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT + 0 + + + + false + + + + + + Component_Name + cri_gth_0_2_0_8 + + + + + UltraScale FPGAs Transceivers Wizard + 8 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.1 + + + + + + + diff --git a/media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_rx.v b/media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_rx.v new file mode 100644 index 0000000..aa4c8aa --- /dev/null +++ b/media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_rx.v @@ -0,0 +1,145 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ********************************************************************************************************************* +// IMPORTANT +// This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design. +// However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this +// core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any +// modifications you may choose to make. +// ********************************************************************************************************************* + +module cri_gth_0_2_0_8_example_gtwiz_userclk_rx #( + + parameter integer P_CONTENTS = 0, + parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1, + parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1 + +)( + + input wire gtwiz_userclk_rx_srcclk_in, + input wire gtwiz_userclk_rx_reset_in, + output wire gtwiz_userclk_rx_usrclk_out, + output wire gtwiz_userclk_rx_usrclk2_out, + output wire gtwiz_userclk_rx_active_out + +); + + + // ------------------------------------------------------------------------------------------------------------------- + // Local parameters + // ------------------------------------------------------------------------------------------------------------------- + + // Convert integer parameters with known, limited legal range to a 3-bit local parameter values + localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1; + localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0]; + localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1; + localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0]; + + + // ------------------------------------------------------------------------------------------------------------------- + // Receiver user clocking network conditional generation, based on parameter values in module instantiation + // ------------------------------------------------------------------------------------------------------------------- + generate if (1) begin: gen_gtwiz_userclk_rx_main + + // Use BUFG_GT instance(s) to drive RXUSRCLK and RXUSRCLK2, inferred for integral source to RXUSRCLK frequency ratio + if (P_CONTENTS == 0) begin + + // Drive RXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to RXUSRCLK + // frequency ratio + BUFG_GT bufg_gt_usrclk_inst ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (gtwiz_userclk_rx_reset_in), + .CLRMASK (1'b0), + .DIV (P_USRCLK_DIV), + .I (gtwiz_userclk_rx_srcclk_in), + .O (gtwiz_userclk_rx_usrclk_out) + ); + + // If RXUSRCLK and RXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive + // RXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the RXUSRCLK2 frequency. + if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1) + assign gtwiz_userclk_rx_usrclk2_out = gtwiz_userclk_rx_usrclk_out; + else begin + BUFG_GT bufg_gt_usrclk2_inst ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (gtwiz_userclk_rx_reset_in), + .CLRMASK (1'b0), + .DIV (P_USRCLK2_DIV), + .I (gtwiz_userclk_rx_srcclk_in), + .O (gtwiz_userclk_rx_usrclk2_out) + ); + end + + // Indicate active helper block functionality when the BUFG_GT divider is not held in reset + (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_meta = 1'b0; + (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_sync = 1'b0; + always @(posedge gtwiz_userclk_rx_usrclk2_out, posedge gtwiz_userclk_rx_reset_in) begin + if (gtwiz_userclk_rx_reset_in) begin + gtwiz_userclk_rx_active_meta <= 1'b0; + gtwiz_userclk_rx_active_sync <= 1'b0; + end + else begin + gtwiz_userclk_rx_active_meta <= 1'b1; + gtwiz_userclk_rx_active_sync <= gtwiz_userclk_rx_active_meta; + end + end + assign gtwiz_userclk_rx_active_out = gtwiz_userclk_rx_active_sync; + + end + + end + endgenerate + + +endmodule diff --git a/media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_tx.v b/media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_tx.v new file mode 100644 index 0000000..b6e6c35 --- /dev/null +++ b/media_interfaces/xcku/cri_gth_0_2_0_8_example_gtwiz_userclk_tx.v @@ -0,0 +1,145 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ********************************************************************************************************************* +// IMPORTANT +// This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design. +// However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this +// core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any +// modifications you may choose to make. +// ********************************************************************************************************************* + +module cri_gth_0_2_0_8_example_gtwiz_userclk_tx #( + + parameter integer P_CONTENTS = 0, + parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1, + parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1 + +)( + + input wire gtwiz_userclk_tx_srcclk_in, + input wire gtwiz_userclk_tx_reset_in, + output wire gtwiz_userclk_tx_usrclk_out, + output wire gtwiz_userclk_tx_usrclk2_out, + output wire gtwiz_userclk_tx_active_out + +); + + + // ------------------------------------------------------------------------------------------------------------------- + // Local parameters + // ------------------------------------------------------------------------------------------------------------------- + + // Convert integer parameters with known, limited legal range to a 3-bit local parameter values + localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1; + localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0]; + localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1; + localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0]; + + + // ------------------------------------------------------------------------------------------------------------------- + // Transmitter user clocking network conditional generation, based on parameter values in module instantiation + // ------------------------------------------------------------------------------------------------------------------- + generate if (1) begin: gen_gtwiz_userclk_tx_main + + // Use BUFG_GT instance(s) to drive TXUSRCLK and TXUSRCLK2, inferred for integral source to TXUSRCLK frequency ratio + if (P_CONTENTS == 0) begin + + // Drive TXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to TXUSRCLK + // frequency ratio + BUFG_GT bufg_gt_usrclk_inst ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (gtwiz_userclk_tx_reset_in), + .CLRMASK (1'b0), + .DIV (P_USRCLK_DIV), + .I (gtwiz_userclk_tx_srcclk_in), + .O (gtwiz_userclk_tx_usrclk_out) + ); + + // If TXUSRCLK and TXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive + // TXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the TXUSRCLK2 frequency. + if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1) + assign gtwiz_userclk_tx_usrclk2_out = gtwiz_userclk_tx_usrclk_out; + else begin + BUFG_GT bufg_gt_usrclk2_inst ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (gtwiz_userclk_tx_reset_in), + .CLRMASK (1'b0), + .DIV (P_USRCLK2_DIV), + .I (gtwiz_userclk_tx_srcclk_in), + .O (gtwiz_userclk_tx_usrclk2_out) + ); + end + + // Indicate active helper block functionality when the BUFG_GT divider is not held in reset + (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_meta = 1'b0; + (* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_tx_active_sync = 1'b0; + always @(posedge gtwiz_userclk_tx_usrclk2_out, posedge gtwiz_userclk_tx_reset_in) begin + if (gtwiz_userclk_tx_reset_in) begin + gtwiz_userclk_tx_active_meta <= 1'b0; + gtwiz_userclk_tx_active_sync <= 1'b0; + end + else begin + gtwiz_userclk_tx_active_meta <= 1'b1; + gtwiz_userclk_tx_active_sync <= gtwiz_userclk_tx_active_meta; + end + end + assign gtwiz_userclk_tx_active_out = gtwiz_userclk_tx_active_sync; + + end + + end + endgenerate + + +endmodule diff --git a/media_interfaces/xcku/cri_gth_0_2_0_8_example_wrapper.v b/media_interfaces/xcku/cri_gth_0_2_0_8_example_wrapper.v new file mode 100644 index 0000000..8a48032 --- /dev/null +++ b/media_interfaces/xcku/cri_gth_0_2_0_8_example_wrapper.v @@ -0,0 +1,263 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ===================================================================================================================== +// This example design wrapper module instantiates the core and any helper blocks which the user chose to exclude from +// the core, connects them as appropriate, and maps enabled ports +// ===================================================================================================================== + +module cri_gth_0_2_0_8_example_wrapper ( + input wire [0:0] gthrxn_in + ,input wire [0:0] gthrxp_in + ,output wire [0:0] gthtxn_out + ,output wire [0:0] gthtxp_out + ,input wire [0:0] gtwiz_userclk_tx_reset_in + ,output wire [0:0] gtwiz_userclk_tx_srcclk_out + ,output wire [0:0] gtwiz_userclk_tx_usrclk_out + ,output wire [0:0] gtwiz_userclk_tx_usrclk2_out + ,output wire [0:0] gtwiz_userclk_tx_active_out + ,input wire [0:0] gtwiz_userclk_rx_reset_in + ,output wire [0:0] gtwiz_userclk_rx_srcclk_out + ,output wire [0:0] gtwiz_userclk_rx_usrclk_out + ,output wire [0:0] gtwiz_userclk_rx_usrclk2_out + ,output wire [0:0] gtwiz_userclk_rx_active_out + ,input wire [0:0] gtwiz_reset_clk_freerun_in + ,input wire [0:0] gtwiz_reset_all_in + ,input wire [0:0] gtwiz_reset_tx_pll_and_datapath_in + ,input wire [0:0] gtwiz_reset_tx_datapath_in + ,input wire [0:0] gtwiz_reset_rx_pll_and_datapath_in + ,input wire [0:0] gtwiz_reset_rx_datapath_in + ,output wire [0:0] gtwiz_reset_rx_cdr_stable_out + ,output wire [0:0] gtwiz_reset_tx_done_out + ,output wire [0:0] gtwiz_reset_rx_done_out + ,input wire [15:0] gtwiz_userdata_tx_in + ,output wire [15:0] gtwiz_userdata_rx_out + ,input wire [0:0] gtrefclk00_in + ,output wire [0:0] qpll0outclk_out + ,output wire [0:0] qpll0outrefclk_out + ,input wire [0:0] rx8b10ben_in + ,input wire [0:0] rxbufreset_in + ,input wire [0:0] rxcommadeten_in + ,input wire [0:0] rxmcommaalignen_in + ,input wire [0:0] rxpcommaalignen_in + ,input wire [0:0] tx8b10ben_in + ,input wire [15:0] txctrl0_in + ,input wire [15:0] txctrl1_in + ,input wire [7:0] txctrl2_in + ,output wire [0:0] gtpowergood_out + ,output wire [2:0] rxbufstatus_out + ,output wire [0:0] rxbyteisaligned_out + ,output wire [0:0] rxbyterealign_out + ,output wire [1:0] rxclkcorcnt_out + ,output wire [0:0] rxcommadet_out + ,output wire [15:0] rxctrl0_out + ,output wire [15:0] rxctrl1_out + ,output wire [7:0] rxctrl2_out + ,output wire [7:0] rxctrl3_out + ,output wire [0:0] rxpmaresetdone_out + ,output wire [0:0] txpmaresetdone_out +); + + + // =================================================================================================================== + // PARAMETERS AND FUNCTIONS + // =================================================================================================================== + + // Declare and initialize local parameters and functions used for HDL generation + // localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000; + `include "cri_gth_q0_2_0_8_example_wrapper_functions.v" + localparam integer P_TX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); + localparam integer P_RX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); + + + // =================================================================================================================== + // HELPER BLOCKS + // =================================================================================================================== + + // Any helper blocks which the user chose to exclude from the core will appear below. In addition, some signal + // assignments related to optionally-enabled ports may appear below. + + // ------------------------------------------------------------------------------------------------------------------- + // Transmitter user clocking network helper block + // ------------------------------------------------------------------------------------------------------------------- + + wire [0:0] txusrclk_int; + wire [0:0] txusrclk2_int; + wire [0:0] txoutclk_int; + + // Generate a single module instance which is driven by a clock source associated with the master transmitter channel, + // and which drives TXUSRCLK and TXUSRCLK2 for all channels + + // The source clock is TXOUTCLK from the master transmitter channel + assign gtwiz_userclk_tx_srcclk_out = txoutclk_int[P_TX_MASTER_CH_PACKED_IDX]; + + // Instantiate a single instance of the transmitter user clocking network helper block + cri_gth_0_2_0_8_example_gtwiz_userclk_tx gtwiz_userclk_tx_inst ( + .gtwiz_userclk_tx_srcclk_in (gtwiz_userclk_tx_srcclk_out), + .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in), + .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out), + .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out), + .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out) + ); + + // Drive TXUSRCLK and TXUSRCLK2 for all channels with the respective helper block outputs + assign txusrclk_int = {1{gtwiz_userclk_tx_usrclk_out}}; + assign txusrclk2_int = {1{gtwiz_userclk_tx_usrclk2_out}}; + + // ------------------------------------------------------------------------------------------------------------------- + // Receiver user clocking network helper block + // ------------------------------------------------------------------------------------------------------------------- + + wire [0:0] rxusrclk_int; + wire [0:0] rxusrclk2_int; + wire [0:0] rxoutclk_int; + + // Generate a single module instance which is driven by a clock source associated with the master receiver channel, + // and which drives RXUSRCLK and RXUSRCLK2 for all channels + + // The source clock is RXOUTCLK from the master receiver channel + assign gtwiz_userclk_rx_srcclk_out = rxoutclk_int[P_RX_MASTER_CH_PACKED_IDX]; + + // Instantiate a single instance of the receiver user clocking network helper block + cri_gth_0_2_0_8_example_gtwiz_userclk_rx gtwiz_userclk_rx_inst ( + .gtwiz_userclk_rx_srcclk_in (gtwiz_userclk_rx_srcclk_out), + .gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in), + .gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out), + .gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out), + .gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out) + ); + + // Drive RXUSRCLK and RXUSRCLK2 for all channels with the respective helper block outputs + assign rxusrclk_int = {1{gtwiz_userclk_rx_usrclk_out}}; + assign rxusrclk2_int = {1{gtwiz_userclk_rx_usrclk2_out}}; + wire [0:0] gtpowergood_int; + + // Required assignment to expose the GTPOWERGOOD port per user request + assign gtpowergood_out = gtpowergood_int; + + // ---------------------------------------------------------------------------------------------------------------- + // Assignments to expose data ports, or data control ports, per configuration requirement or user request + // ---------------------------------------------------------------------------------------------------------------- + + wire [15:0] txctrl0_int; + + // Required assignment to expose the TXCTRL0 port per configuration requirement or user request + assign txctrl0_int = txctrl0_in; + wire [15:0] txctrl1_int; + + // Required assignment to expose the TXCTRL1 port per configuration requirement or user request + assign txctrl1_int = txctrl1_in; + wire [15:0] rxctrl0_int; + + // Required assignment to expose the RXCTRL0 port per configuration requirement or user request + assign rxctrl0_out = rxctrl0_int; + wire [15:0] rxctrl1_int; + + // Required assignment to expose the RXCTRL1 port per configuration requirement or user request + assign rxctrl1_out = rxctrl1_int; + + + // =================================================================================================================== + // CORE INSTANCE + // =================================================================================================================== + + // Instantiate the core, mapping its enabled ports to example design ports and helper blocks as appropriate + cri_gth_0_2_0_8 cri_gth_0_2_0_8_inst ( + .gthrxn_in (gthrxn_in) + ,.gthrxp_in (gthrxp_in) + ,.gthtxn_out (gthtxn_out) + ,.gthtxp_out (gthtxp_out) + ,.gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_out) + ,.gtwiz_userclk_rx_active_in (gtwiz_userclk_rx_active_out) + ,.gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in) + ,.gtwiz_reset_all_in (gtwiz_reset_all_in) + ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in) + ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in) + ,.gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in) + ,.gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in) + ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out) + ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out) + ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out) + ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_in) + ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_out) + ,.gtrefclk00_in (gtrefclk00_in) + ,.qpll0outclk_out (qpll0outclk_out) + ,.qpll0outrefclk_out (qpll0outrefclk_out) + ,.rx8b10ben_in (rx8b10ben_in) + ,.rxbufreset_in (rxbufreset_in) + ,.rxcommadeten_in (rxcommadeten_in) + ,.rxmcommaalignen_in (rxmcommaalignen_in) + ,.rxpcommaalignen_in (rxpcommaalignen_in) + ,.rxusrclk_in (rxusrclk_int) + ,.rxusrclk2_in (rxusrclk2_int) + ,.tx8b10ben_in (tx8b10ben_in) + ,.txctrl0_in (txctrl0_int) + ,.txctrl1_in (txctrl1_int) + ,.txctrl2_in (txctrl2_in) + ,.txusrclk_in (txusrclk_int) + ,.txusrclk2_in (txusrclk2_int) + ,.gtpowergood_out (gtpowergood_int) + ,.rxbufstatus_out (rxbufstatus_out) + ,.rxbyteisaligned_out (rxbyteisaligned_out) + ,.rxbyterealign_out (rxbyterealign_out) + ,.rxclkcorcnt_out (rxclkcorcnt_out) + ,.rxcommadet_out (rxcommadet_out) + ,.rxctrl0_out (rxctrl0_int) + ,.rxctrl1_out (rxctrl1_int) + ,.rxctrl2_out (rxctrl2_out) + ,.rxctrl3_out (rxctrl3_out) + ,.rxoutclk_out (rxoutclk_int) + ,.rxpmaresetdone_out (rxpmaresetdone_out) + ,.txoutclk_out (txoutclk_int) + ,.txpmaresetdone_out (txpmaresetdone_out) +); + +endmodule diff --git a/media_interfaces/xcku/cri_gth_define.vhd b/media_interfaces/xcku/cri_gth_define.vhd new file mode 100644 index 0000000..42a59d0 --- /dev/null +++ b/media_interfaces/xcku/cri_gth_define.vhd @@ -0,0 +1,56 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + + +package cri_gth_define is + + +component clk_wiz_0 is + port ( + clk_in1_p : in std_logic; + clk_in1_n : in std_logic; + --clk_in1 : in std_logic; + reset : in std_logic; + clk_out1 : out std_logic; + clk_out2 : out std_logic; + locked : out std_logic + ); +end component; + +component clk_txUsrClk is + port ( + clk_in1 : in std_logic; + reset : in std_logic; + clk_out1 : out std_logic; + clk_out2 : out std_logic; + locked : out std_logic + ); +end component; + +component IBUFDS_GTE3 is + generic ( + REFCLK_EN_TX_PATH : std_logic := '0'; + REFCLK_HROW_CK_SEL : std_logic_vector(1 downto 0) := "00"; + REFCLK_ICNTL_RX : std_logic_vector(1 downto 0) := "00" + ); + port(-- IBUFDS_GTE3_MGTREFCLK0_X0Y3_INST ( + I : in std_logic; + IB : in std_logic; + CEB : in std_logic; + O : out std_logic; + ODIV2 : out std_logic_vector(0 downto 0) + ); +end component; + +component cri_gth_q0_2_0_8_example_bit_synchronizer + port ( + clk_in : in std_logic; + i_in : in std_logic; + o_out : out std_logic + ); + end component; + + +end package; \ No newline at end of file diff --git a/media_interfaces/xcku/cri_gth_q0_2_0_8_example_bit_sync.v b/media_interfaces/xcku/cri_gth_q0_2_0_8_example_bit_sync.v new file mode 100644 index 0000000..b72c2da --- /dev/null +++ b/media_interfaces/xcku/cri_gth_q0_2_0_8_example_bit_sync.v @@ -0,0 +1,91 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ********************************************************************************************************************* +// IMPORTANT +// This block is delivered within the example design. If you wish to modify its behavior, be careful to understand the +// existing behavior and the effects of any modifications you may choose to make. +// ********************************************************************************************************************* + +module cri_gth_q0_2_0_8_example_bit_synchronizer # ( + + parameter INITIALIZE = 5'b00000, + parameter FREQUENCY = 512 + +)( + + input wire clk_in, + input wire i_in, + output wire o_out + +); + + // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to + // enable clustering. Their GSR default values are provided by the INITIALIZE parameter. + + (* ASYNC_REG = "TRUE" *) reg i_in_meta = INITIALIZE[0]; + (* ASYNC_REG = "TRUE" *) reg i_in_sync1 = INITIALIZE[1]; + (* ASYNC_REG = "TRUE" *) reg i_in_sync2 = INITIALIZE[2]; + (* ASYNC_REG = "TRUE" *) reg i_in_sync3 = INITIALIZE[3]; + reg i_in_out = INITIALIZE[4]; + + always @(posedge clk_in) begin + i_in_meta <= i_in; + i_in_sync1 <= i_in_meta; + i_in_sync2 <= i_in_sync1; + i_in_sync3 <= i_in_sync2; + i_in_out <= i_in_sync3; + end + + assign o_out = i_in_out; + + +endmodule diff --git a/media_interfaces/xcku/cri_gth_q0_2_0_8_example_reset_sync.v b/media_interfaces/xcku/cri_gth_q0_2_0_8_example_reset_sync.v new file mode 100644 index 0000000..77bcaef --- /dev/null +++ b/media_interfaces/xcku/cri_gth_q0_2_0_8_example_reset_sync.v @@ -0,0 +1,101 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ********************************************************************************************************************* +// IMPORTANT +// This block is delivered within the example design. If you wish to modify its behavior, be careful to understand the +// existing behavior and the effects of any modifications you may choose to make. +// ********************************************************************************************************************* + +module cri_gth_q0_2_0_8_example_reset_synchronizer # ( + + parameter FREQUENCY = 512 + +)( + + input wire clk_in, + input wire rst_in, + output wire rst_out + +); + + // Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to + // enable clustering. Each flip-flop in the synchronizer is asynchronously reset so that the downstream logic is also + // asynchronously reset but encounters no reset assertion latency. The removal of reset is synchronous, so that the + // downstream logic is also removed from reset synchronously. This module is designed for active-high reset use. + + (* ASYNC_REG = "TRUE" *) reg rst_in_meta = 1'b0; + (* ASYNC_REG = "TRUE" *) reg rst_in_sync1 = 1'b0; + (* ASYNC_REG = "TRUE" *) reg rst_in_sync2 = 1'b0; + (* ASYNC_REG = "TRUE" *) reg rst_in_sync3 = 1'b0; + reg rst_in_out = 1'b0; + + always @(posedge clk_in, posedge rst_in) begin + if (rst_in) begin + rst_in_meta <= 1'b1; + rst_in_sync1 <= 1'b1; + rst_in_sync2 <= 1'b1; + rst_in_sync3 <= 1'b1; + rst_in_out <= 1'b1; + end + else begin + rst_in_meta <= 1'b0; + rst_in_sync1 <= rst_in_meta; + rst_in_sync2 <= rst_in_sync1; + rst_in_sync3 <= rst_in_sync2; + rst_in_out <= rst_in_sync3; + end + end + + assign rst_out = rst_in_out; + + +endmodule diff --git a/media_interfaces/xcku/cri_gth_q0_2_0_8_example_wrapper_functions.v b/media_interfaces/xcku/cri_gth_q0_2_0_8_example_wrapper_functions.v new file mode 100644 index 0000000..d8ab0be --- /dev/null +++ b/media_interfaces/xcku/cri_gth_q0_2_0_8_example_wrapper_functions.v @@ -0,0 +1,242 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000; + + +// ===================================================================================================================== +// This file contains functions available for example design HDL generation as required +// ===================================================================================================================== + +// Function to populate a bit mapping of enabled transceiver common blocks to transceiver quads +function [47:0] f_pop_cm_en ( + input integer in_null +); +begin : main_f_pop_cm_en + integer i; + reg [47:0] tmp; + for (i = 0; i < 192; i = i + 4) begin + if ((P_CHANNEL_ENABLE[i] == 1'b1) || + (P_CHANNEL_ENABLE[i+1] == 1'b1) || + (P_CHANNEL_ENABLE[i+2] == 1'b1) || + (P_CHANNEL_ENABLE[i+3] == 1'b1)) + tmp[i/4] = 1'b1; + else + tmp[i/4] = 1'b0; + end + f_pop_cm_en = tmp; +end +endfunction + +// Function to calculate a pointer to a master channel's packed index +function integer f_calc_pk_mc_idx ( + input integer idx_mc +); +begin : main_f_calc_pk_mc_idx + integer i, j; + integer tmp; + j = 0; + for (i = 0; i < 192; i = i + 1) begin + if (P_CHANNEL_ENABLE[i] == 1'b1) begin + if (i == idx_mc) + tmp = j; + else + j = j + 1; + end + end + f_calc_pk_mc_idx = tmp; +end +endfunction + +// Function to calculate the upper bound of a transceiver common-related signal within a packed vector, for a given +// signal width and unpacked common index +function integer f_ub_cm ( + input integer width, + input integer index +); +begin : main_f_ub_cm + integer i, j; + j = 0; + for (i = 0; i <= index; i = i + 4) begin + if (P_CHANNEL_ENABLE[i] == 1'b1 || + P_CHANNEL_ENABLE[i+1] == 1'b1 || + P_CHANNEL_ENABLE[i+2] == 1'b1 || + P_CHANNEL_ENABLE[i+3] == 1'b1) + j = j + 1; + end + f_ub_cm = (width * j) - 1; +end +endfunction + +// Function to calculate the lower bound of a transceiver common-related signal within a packed vector, for a given +// signal width and unpacked common index +function integer f_lb_cm ( + input integer width, + input integer index +); +begin : main_f_lb_cm + integer i, j; + j = 0; + for (i = 0; i < index; i = i + 4) begin + if (P_CHANNEL_ENABLE[i] == 1'b1 || + P_CHANNEL_ENABLE[i+1] == 1'b1 || + P_CHANNEL_ENABLE[i+2] == 1'b1 || + P_CHANNEL_ENABLE[i+3] == 1'b1) + j = j + 1; + end + f_lb_cm = (width * j); +end +endfunction + +// Function to calculate the packed vector index of a transceiver common, provided the packed vector index of the +// associated transceiver channel +function integer f_idx_cm ( + input integer index +); +begin : main_f_idx_cm + integer i, j, k, flag, result; + j = 0; + k = 0; + flag = 0; + for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin + if (P_CHANNEL_ENABLE[i] == 1'b1 || + P_CHANNEL_ENABLE[i+1] == 1'b1 || + P_CHANNEL_ENABLE[i+2] == 1'b1 || + P_CHANNEL_ENABLE[i+3] == 1'b1) begin + k = k + 1; + if (P_CHANNEL_ENABLE[i+3] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+2] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+1] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i] == 1'b1) + j = j + 1; + end + + if (j >= (index + 1)) begin + flag = 1; + result = k; + end + end + f_idx_cm = result - 1; +end +endfunction + +// Function to calculate the packed vector index of the upper bound transceiver channel which is associated with the +// provided transceiver common packed vector index +function integer f_idx_ch_ub ( + input integer index +); +begin : main_f_idx_ch_ub + integer i, j, k, flag, result; + j = 0; + k = 0; + flag = 0; + for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin + + if (P_CHANNEL_ENABLE[i] == 1'b1 || + P_CHANNEL_ENABLE[i+1] == 1'b1 || + P_CHANNEL_ENABLE[i+2] == 1'b1 || + P_CHANNEL_ENABLE[i+3] == 1'b1) begin + k = k + 1; + if (P_CHANNEL_ENABLE[i] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+1] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+2] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+3] == 1'b1) + j = j + 1; + if (k == index + 1) begin + flag = 1; + result = j; + end + end + + end + f_idx_ch_ub = result - 1; +end +endfunction + +// Function to calculate the packed vector index of the lower bound transceiver channel which is associated with the +// provided transceiver common packed vector index +function integer f_idx_ch_lb ( + input integer index +); +begin : main_f_idx_ch_lb + integer i, j, k, flag, result; + j = 0; + k = 0; + flag = 0; + for (i = 0; (i < 192) && (flag == 0); i = i + 4) begin + + if (P_CHANNEL_ENABLE[i] == 1'b1 || + P_CHANNEL_ENABLE[i+1] == 1'b1 || + P_CHANNEL_ENABLE[i+2] == 1'b1 || + P_CHANNEL_ENABLE[i+3] == 1'b1) begin + k = k + 1; + if (k == index + 1) begin + flag = 1; + result = j + 1; + end + else begin + if (P_CHANNEL_ENABLE[i] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+1] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+2] == 1'b1) + j = j + 1; + if (P_CHANNEL_ENABLE[i+3] == 1'b1) + j = j + 1; + end + end + + end + f_idx_ch_lb = result - 1; +end +endfunction diff --git a/media_interfaces/xcku/cri_gth_reset_sync.v b/media_interfaces/xcku/cri_gth_reset_sync.v new file mode 100644 index 0000000..e4ad660 --- /dev/null +++ b/media_interfaces/xcku/cri_gth_reset_sync.v @@ -0,0 +1,281 @@ +//------------------------------------------------------------------------------ +// (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//------------------------------------------------------------------------------ + + +`timescale 1ps/1ps + +// ===================================================================================================================== +// This example design initialization module provides a demonstration of how initialization logic can be constructed to +// interact with and enhance the reset controller helper block in order to assist with successful system bring-up. This +// example initialization logic monitors for timely reset completion, retrying resets as necessary to mitigate problems +// with system bring-up such as clock or data connection readiness. This is an example and can be modified as necessary. +// ===================================================================================================================== + +module cri_gth_init # ( + + parameter real P_FREERUN_FREQUENCY = 100, + parameter real P_TX_TIMER_DURATION_US = 30000, + parameter real P_RX_TIMER_DURATION_US = 130000 + +)( + + input wire clk_freerun_in, + input wire reset_all_in, + input wire tx_init_done_in, + input wire rx_init_done_in, + input wire rx_cdr_stable_in, + output reg reset_all_out = 1'b0, + output reg reset_rx_out = 1'b0, + output reg init_done_out = 1'b0, + output reg [3:0] retry_ctr_out = 4'd0 + +); + + + // ------------------------------------------------------------------------------------------------------------------- + // Synchronizers + // ------------------------------------------------------------------------------------------------------------------- + + // Synchronize the "reset all" input signal into the free-running clock domain + // The reset_all_in input should be driven by the master "reset all" example design input + wire reset_all_sync; + (* DONT_TOUCH = "TRUE" *) + cri_gth_q0_2_0_8_example_reset_synchronizer reset_synchronizer_reset_all_inst ( + .clk_in (clk_freerun_in), + .rst_in (reset_all_in), + .rst_out (reset_all_sync) + ); + + // Synchronize the TX initialization done indicator into the free-running clock domain + // The tx_init_done_in input should be driven by the signal or logical combination of signals that represents a + // completed TX initialization process; for example, the reset helper block gtwiz_reset_tx_done_out signal, or the + // logical AND of gtwiz_reset_tx_done_out with gtwiz_buffbypass_tx_done_out if the TX buffer is bypassed. + wire tx_init_done_sync; + (* DONT_TOUCH = "TRUE" *) + cri_gth_q0_2_0_8_example_bit_synchronizer bit_synchronizer_tx_init_done_inst ( + .clk_in (clk_freerun_in), + .i_in (tx_init_done_in), + .o_out (tx_init_done_sync) + ); + + // Synchronize the RX initialization done indicator into the free-running clock domain + // The rx_init_done_in input should be driven by the signal or logical combination of signals that represents a + // completed RX initialization process; for example, the reset helper block gtwiz_reset_rx_done_out signal, or the + // logical AND of gtwiz_reset_rx_done_out with gtwiz_buffbypass_rx_done_out if the RX elastic buffer is bypassed. + wire rx_init_done_sync; + (* DONT_TOUCH = "TRUE" *) + cri_gth_q0_2_0_8_example_bit_synchronizer bit_synchronizer_rx_init_done_inst ( + .clk_in (clk_freerun_in), + .i_in (rx_init_done_in), + .o_out (rx_init_done_sync) + ); + + + wire rx_cdr_stable_in_sync; + (* DONT_TOUCH = "TRUE" *) + cri_gth_q0_2_0_8_example_bit_synchronizer bit_synchronizer_rx_cdr_stable_inst ( + .clk_in (clk_freerun_in), + .i_in (rx_cdr_stable_in), + .o_out (rx_cdr_stable_in_sync) + ); + + + // ------------------------------------------------------------------------------------------------------------------- + // Timer + // ------------------------------------------------------------------------------------------------------------------- + + // Declare registers and local parameters used for the shared TX and RX initialization timer + // The free-running clock frequency is specified by the P_FREERUN_FREQUENCY parameter. The TX initialization timer + // duration is specified by the P_TX_TIMER_DURATION_US parameter (default 30,000us), and the resulting terminal count + // is assigned to p_tx_timer_term_cyc_int. The RX initialization timer duration is specified by the + // P_RX_TIMER_DURATION_US parameter (default 130,000us), and the resulting terminal count is assigned to + // p_rx_timer_term_cyc_int. + reg timer_clr = 1'b1; + reg [24:0] timer_ctr = 25'd0; + reg tx_timer_sat = 1'b0; + reg rx_timer_sat = 1'b0; + wire [24:0] p_tx_timer_term_cyc_int = P_TX_TIMER_DURATION_US * P_FREERUN_FREQUENCY; + wire [24:0] p_rx_timer_term_cyc_int = P_RX_TIMER_DURATION_US * P_FREERUN_FREQUENCY; + + // When the timer is enabled by the initialization state machine, increment the timer_ctr counter until its value + // reaches p_rx_timer_term_cyc_int RX terminal count and rx_timer_sat is asserted. Assert tx_timer_sat when the + // counter value reaches the p_tx_timer_term_cyc_int TX terminal count. Clear the timer and remove assertions when the + // timer is disabled by the initialization state machine. + always @(posedge clk_freerun_in) begin + if (timer_clr) begin + timer_ctr <= 25'd0; + tx_timer_sat <= 1'b0; + rx_timer_sat <= 1'b0; + end + else begin + if (timer_ctr == p_tx_timer_term_cyc_int) + tx_timer_sat <= 1'b1; + + if (timer_ctr == p_rx_timer_term_cyc_int) + rx_timer_sat <= 1'b1; + else + timer_ctr <= timer_ctr + 25'd1; + end + end + + + // ------------------------------------------------------------------------------------------------------------------- + // Retry counter + // ------------------------------------------------------------------------------------------------------------------- + + // Increment the retry_ctr_out register for each TX or RX reset asserted by the initialization state machine until the + // register saturates at 4'd15. This value, which is initialized on device programming and is never reset, could be + // useful for debugging purposes. The initialization state machine will continue to retry as needed beyond the retry + // register saturation point indicated, so 4'd15 should be interpreted as "15 or more attempts since programming." + reg retry_ctr_incr = 1'b0; + + always @(posedge clk_freerun_in) begin + if ((retry_ctr_incr == 1'b1) && (retry_ctr_out != 4'd15)) + retry_ctr_out <= retry_ctr_out + 4'd1; + end + + + // ------------------------------------------------------------------------------------------------------------------- + // Initialization state machine + // ------------------------------------------------------------------------------------------------------------------- + + // Declare local parameters and state register for the initialization state machine + localparam [1:0] ST_START = 2'd0; + localparam [1:0] ST_TX_WAIT = 2'd1; + localparam [1:0] ST_RX_WAIT = 2'd2; + localparam [1:0] ST_END = 2'd3; + reg [1:0] sm_init = ST_START; + reg sm_init_active = 1'b0; + + // Implement the initialization state machine control and its outputs as a single sequential process. The state + // machine is reset by the synchronized reset_all_in input, and does not begin operating until its first use. Note + // that this state machine is designed to interact with and enhance the reset controller helper block. + always @(posedge clk_freerun_in) begin + if (reset_all_sync) begin + timer_clr <= 1'b1; + reset_all_out <= 1'b0; + reset_rx_out <= 1'b0; + retry_ctr_incr <= 1'b0; + init_done_out <= 1'b0; + sm_init_active <= 1'b1; + sm_init <= ST_START; + end + else begin + case (sm_init) + + // When starting the initialization procedure, clear the timer and remove reset outputs, then proceed to wait + // for completion of TX initialization + ST_START: begin + if (sm_init_active) begin + timer_clr <= 1'b1; + reset_all_out <= 1'b1; + reset_rx_out <= 1'b0; + retry_ctr_incr <= 1'b0; + sm_init <= ST_TX_WAIT; + end + end + + // Enable the timer. If TX initialization completes before the counter's TX terminal count, clear the timer and + // proceed to wait for RX initialization. If the TX terminal count is reached, clear the timer, assert the + // reset_all_out output (which in this example causes a master reset_all assertion), and increment the retry + // counter. Completion conditions for TX initialization are described above. + ST_TX_WAIT: begin + reset_all_out <= 1'b0; + if (tx_init_done_sync) begin + timer_clr <= 1'b1; + sm_init <= ST_RX_WAIT; + end + else begin + if (tx_timer_sat) begin + timer_clr <= 1'b1; + retry_ctr_incr <= 1'b1; + sm_init <= ST_START; + end + else begin + timer_clr <= 1'b0; + end + end + end + + // Enable the timer. When the RX terminal count is reached, check whether RX initialization has completed and + // whether the data good indicator is high. If both conditions are met, transition to the MONITOR state. If + // either condition is not met, then clear the timer, assert the reset_rx_out output (which in this example + // either drives gtwiz_reset_rx_pll_and_datapath_in or gtwiz_reset_rx_datapath_in, depending on PLL sharing), + // and increnent the retry counter. + ST_RX_WAIT: begin + reset_all_out <= 1'b0; + if (rx_init_done_sync) begin + timer_clr <= 1'b1; + sm_init <= ST_END; + end + else begin + if (rx_timer_sat) begin + timer_clr <= 1'b1; + retry_ctr_incr <= 1'b1; + reset_all_out <= 1'b1; + sm_init <= ST_RX_WAIT; + end + else begin + timer_clr <= 1'b0; + end + end + end + + // In this MONITOR state, assert the init_done_out output for use as desired. If RX initialization or the data + // good indicator is lost while in this state, reset the RX components as described in the ST_RX_WAIT state. + ST_END: begin + init_done_out <= 1'b1; + sm_init_active <= 1'b0; + end + + endcase + end + end + + +endmodule diff --git a/media_interfaces/xcku/gth_8b10b.vhd b/media_interfaces/xcku/gth_8b10b.vhd new file mode 100644 index 0000000..cbdb4a8 --- /dev/null +++ b/media_interfaces/xcku/gth_8b10b.vhd @@ -0,0 +1,368 @@ +library ieee; +use ieee.std_logic_1164.all; + +library unisim; +use unisim.vcomponents.all; + +entity gth_8b10b is + port ( + clk_100 : in std_logic; + clk_200 : in std_logic; + reset_all : in std_logic; + mgtrefclk0_x0y3_int : in std_logic; + FREECLK : in std_logic; + + ch0_gthrxn_in : in std_logic; + ch0_gthrxp_in : in std_logic; + ch0_gthtxn_out : out std_logic; + ch0_gthtxp_out : out std_logic; + + tx_clk : out std_logic; + tx_data : in std_logic_vector(7 downto 0); + tx_k : in std_logic; + + rx_clk : out std_logic; + rx_data : out std_logic_vector(7 downto 0); + rx_k : out std_logic; + + rx_cdr_stable : out std_logic; + tx_pll_reset : in std_logic; + rx_pll_reset : in std_logic; + + tx_ready : out std_logic; + rx_ready : out std_logic; + + tx_active : out std_logic; + rx_active : out std_logic; + gtpowergood : out std_logic; + + init_done : out std_logic; + + TX_USRCLK : out std_logic + ); +end entity gth_8b10b; + +architecture behavioral of gth_8b10b is + component cri_gth_0_2_0_8_example_wrapper + port ( + gthrxn_in : in std_logic; + gthrxp_in : in std_logic; + gthtxn_out : out std_logic; + gthtxp_out : out std_logic; + gtwiz_userclk_tx_reset_in : in std_logic; + gtwiz_userclk_tx_srcclk_out : out std_logic; + gtwiz_userclk_tx_usrclk_out : out std_logic; + gtwiz_userclk_tx_usrclk2_out : out std_logic; + gtwiz_userclk_tx_active_out : out std_logic; + gtwiz_userclk_rx_reset_in : in std_logic; + gtwiz_userclk_rx_srcclk_out : out std_logic; + gtwiz_userclk_rx_usrclk_out : out std_logic; + gtwiz_userclk_rx_usrclk2_out : out std_logic; + gtwiz_userclk_rx_active_out : out std_logic; + gtwiz_reset_clk_freerun_in : in std_logic; + gtwiz_reset_all_in : in std_logic; + gtwiz_reset_tx_pll_and_datapath_in : in std_logic; + gtwiz_reset_tx_datapath_in : in std_logic; + gtwiz_reset_rx_pll_and_datapath_in : in std_logic; + gtwiz_reset_rx_datapath_in : in std_logic; + gtwiz_reset_rx_cdr_stable_out : out std_logic; + gtwiz_reset_tx_done_out : out std_logic; + gtwiz_reset_rx_done_out : out std_logic; + gtwiz_userdata_tx_in : in std_logic_vector(15 downto 0); + gtwiz_userdata_rx_out : out std_logic_vector(15 downto 0); + gtrefclk00_in : in std_logic; + qpll0outclk_out : out std_logic; + qpll0outrefclk_out : out std_logic; + rx8b10ben_in : in std_logic; + rxbufreset_in : in std_logic; + rxcommadeten_in : in std_logic; + rxmcommaalignen_in : in std_logic; + rxpcommaalignen_in : in std_logic; + tx8b10ben_in : in std_logic; + txctrl0_in : in std_logic_vector(15 downto 0); + txctrl1_in : in std_logic_vector(15 downto 0); + txctrl2_in : in std_logic_vector(7 downto 0); + gtpowergood_out : out std_logic; + rxbufstatus_out : out std_logic_vector(2 downto 0); + rxbyteisaligned_out : out std_logic; + rxbyterealign_out : out std_logic; + rxclkcorcnt_out : out std_logic_vector(1 downto 0); + rxcommadet_out : out std_logic; + rxctrl0_out : out std_logic_vector(15 downto 0); + rxctrl1_out : out std_logic_vector(15 downto 0); + rxctrl2_out : out std_logic_vector(7 downto 0); + rxctrl3_out : out std_logic_vector(7 downto 0); + rxpmaresetdone_out : out std_logic; + txpmaresetdone_out : out std_logic + ); + end component; + + component cri_gth_init is + generic ( + P_FREERUN_FREQUENCY : integer := 100; + P_TX_TIMER_DURATION_US : integer := 30000; + P_RX_TIMER_DURATION_US : integer := 130000 + ); + port ( + clk_freerun_in : in std_logic; + reset_all_in : in std_logic; + tx_init_done_in : in std_logic; + rx_init_done_in : in std_logic; + reset_all_out : out std_logic := '0'; + reset_rx_out : out std_logic := '0'; + init_done_out : out std_logic := '0'; + retry_ctr_out : out std_logic_vector(3 downto 0) := x"0" + ); + end component; + + signal gtpowergood_i : std_logic; + signal reset_rx_cdr_stable_i : std_logic; + signal reset_tx_done_i : std_logic; + signal reset_rx_done_i : std_logic; + signal userclk_tx_active_i : std_logic; + signal userclk_tx_reset_i : std_logic := '0'; + signal userclk_tx_srcclk_i : std_logic; + signal userclk_tx_usrclk_i : std_logic; + signal userclk_tx_usrclk2_i : std_logic; + signal userclk_rx_reset_i : std_logic := '0'; + signal userclk_rx_srcclk_i : std_logic; + signal userclk_rx_usrclk_i : std_logic; + signal userclk_rx_usrclk2_i : std_logic; + signal userclk_rx_active_i : std_logic; + signal reset_tx_pll_and_datapath_i : std_logic; + signal reset_tx_datapath_i : std_logic := '0'; + signal reset_rx_pll_and_datapath_i : std_logic; + signal reset_rx_datapath_i : std_logic := '0'; + signal qpll0outclk_i : std_logic; + signal qpll0outrefclk_i : std_logic; + signal txctrl0_i : std_logic_vector(15 downto 0); + signal txctrl1_i : std_logic_vector(15 downto 0); + signal txctrl2_i : std_logic_vector(7 downto 0); + signal userdata_tx_i : std_logic_vector(15 downto 0); + signal userdata_rx_i : std_logic_vector(15 downto 0); + signal rxpmaresetdone_i : std_logic; + signal txpmaresetdone_i : std_logic; + + signal rxctrl0_i : std_logic_vector(15 downto 0); + signal rxctrl1_i : std_logic_vector(15 downto 0); + signal rxctrl2_i : std_logic_vector(7 downto 0); + signal rxctrl3_i : std_logic_vector(7 downto 0); + + signal gthrxp_i : std_logic; + signal gthrxn_i : std_logic; + signal gthtxp_i : std_logic; + signal gthtxn_i : std_logic; + + signal reset_all_i : std_logic; + signal reset_all_init : std_logic; + + signal rxcommadeten_i : std_logic; + signal rxmcommaalignen_i : std_logic; + signal rxpcommaalignen_i : std_logic; + + signal rxcommadet_i : std_logic; + signal rxbyteisaligned_i : std_logic; + signal rxbyterealign_i : std_logic; + + signal init_done_i : std_logic; + signal enable_i : std_logic; + + --VIO + signal rxclkcorcnt_i : std_logic_vector(1 downto 0); + signal rxbufstatus_i : std_logic_vector(2 downto 0); + + --RX FIFO + signal rx_empty : std_logic; + + --TX FIFO + signal tx_fifo_full_i : std_logic; + signal tx_fifo_empty_i : std_logic; + signal tx_fifo_valid_i : std_logic; + signal tx_fifo_almempty_i : std_logic; + signal tx_fifo_almfull_i : std_logic; + signal tx_fifo_wr_cnt : std_logic_vector( 9 downto 0); + signal tx_fifo_wren_i : std_logic; + + attribute MARK_DEBUG : string; + attribute MARK_DEBUG of clk_200 : signal is "TRUE"; + attribute MARK_DEBUG of tx_data : signal is "TRUE"; + attribute MARK_DEBUG of tx_k : signal is "TRUE"; + attribute MARK_DEBUG of tx_fifo_full_i : signal is "TRUE"; + attribute MARK_DEBUG of tx_fifo_almfull_i : signal is "TRUE"; + attribute MARK_DEBUG of tx_fifo_wr_cnt : signal is "TRUE"; + attribute MARK_DEBUG of userclk_tx_usrclk2_i : signal is "TRUE"; + attribute MARK_DEBUG of reset_all : signal is "TRUE"; + attribute MARK_DEBUG of userclk_tx_active_i : signal is "TRUE"; + attribute MARK_DEBUG of reset_tx_done_i : signal is "TRUE"; + attribute MARK_DEBUG of userdata_tx_i : signal is "TRUE"; + attribute MARK_DEBUG of txctrl2_i : signal is "TRUE"; + attribute MARK_DEBUG of tx_fifo_empty_i : signal is "TRUE"; + attribute MARK_DEBUG of tx_fifo_valid_i : signal is "TRUE"; + attribute KEEP : string; + attribute KEEP of clk_200 : signal is "TRUE"; + attribute KEEP of tx_data : signal is "TRUE"; + attribute KEEP of tx_k : signal is "TRUE"; + attribute KEEP of tx_fifo_full_i : signal is "TRUE"; + attribute KEEP of tx_fifo_almfull_i : signal is "TRUE"; + attribute KEEP of tx_fifo_wr_cnt : signal is "TRUE"; + attribute KEEP of userclk_tx_usrclk2_i : signal is "TRUE"; + attribute KEEP of reset_all : signal is "TRUE"; + attribute KEEP of userclk_tx_active_i : signal is "TRUE"; + attribute KEEP of reset_tx_done_i : signal is "TRUE"; + attribute KEEP of userdata_tx_i : signal is "TRUE"; + attribute KEEP of txctrl2_i : signal is "TRUE"; + attribute KEEP of tx_fifo_empty_i : signal is "TRUE"; + attribute KEEP of tx_fifo_valid_i : signal is "TRUE"; +begin + init_done <= init_done_i; + tx_clk <= userclk_tx_usrclk2_i; + txctrl0_i <= x"0000"; + txctrl1_i <= x"0000"; + txctrl2_i(7 downto 2) <= "000000"; + + rx_clk <= userclk_rx_usrclk2_i; + + rx_cdr_stable <= reset_rx_cdr_stable_i; + reset_tx_pll_and_datapath_i <= tx_pll_reset; + reset_rx_pll_and_datapath_i <= rx_pll_reset; + + tx_ready <= reset_tx_done_i; + rx_ready <= reset_rx_done_i; + + tx_active <= userclk_tx_active_i; + rx_active <= userclk_rx_active_i; + + gthrxn_i <= ch0_gthrxn_in; + gthrxp_i <= ch0_gthrxp_in; + ch0_gthtxn_out <= gthtxn_i; + ch0_gthtxp_out <= gthtxp_i; + + reset_all_init <= reset_all; + userclk_tx_reset_i <= not (txpmaresetdone_i); --AND over all + userclk_rx_reset_i <= not (rxpmaresetdone_i); --AND over all + + reset_rx_datapath_i <= '0'; + reset_tx_datapath_i <= '0'; + + gtpowergood <= gtpowergood_i; + + --enable Comma detection on K28.5 + rxcommadeten_i <= '1'; + rxmcommaalignen_i <= '1'; + rxpcommaalignen_i <= '1'; + TX_USRCLK <= userclk_tx_usrclk2_i; + + THE_INIT : cri_gth_init + port map ( + clk_freerun_in => FREECLK, + reset_all_in => reset_all_init, + tx_init_done_in => reset_tx_done_i, + rx_init_done_in => reset_rx_done_i, + reset_all_out => reset_all_i, + reset_rx_out => open, + init_done_out => init_done_i, + retry_ctr_out => open + ); + + enable_i <= '1'; + THE_RX_FIFO : entity work.fifo_16x18x9_oreg + port map ( + Data(17) => rxctrl2_i(0), + Data(16 downto 9) => userdata_rx_i( 7 downto 0), + Data( 8) => rxctrl2_i(1), + Data( 7 downto 0) => userdata_rx_i(15 downto 8), + WrClock => userclk_rx_usrclk2_i, + RdClock => clk_200, + WrEn => enable_i, + RdEn => enable_i, + Reset => reset_all, + Q(7 downto 0) => rx_data, + Q(8) => rx_k, + Empty => rx_empty, + Full => open, + AlmostEmpty => open, + AlmostFull => open + ); + + THE_TX_FIFO : entity work.fifo_1024x9x18_oreg_wcnt + port map ( + Data(8) => tx_k, + Data(7 downto 0) => tx_data, + WrClock => clk_200, + RdClock => userclk_tx_usrclk2_i, + WrEn => tx_fifo_wren_i, + RdEn => enable_i, + Reset => reset_all, + Q( 7 downto 0) => userdata_tx_i(15 downto 8), + Q( 8) => txctrl2_i(1), + Q(16 downto 9) => userdata_tx_i( 7 downto 0), + Q(17) => txctrl2_i(0), + WCNT => tx_fifo_wr_cnt, + Empty => tx_fifo_empty_i, + Full => tx_fifo_full_i, + AlmostEmpty => tx_fifo_almempty_i, + AlmostFull => tx_fifo_almfull_i + ); + + process (userclk_tx_usrclk2_i) is + begin + if rising_edge(userclk_tx_usrclk2_i) then + tx_fifo_valid_i <= enable_i and not tx_fifo_empty_i; + end if; + end process; + + tx_fifo_wren_i <= userclk_tx_active_i and reset_tx_done_i; + + THE_GTH : cri_gth_0_2_0_8_example_wrapper + port map( + gtwiz_userclk_tx_reset_in => userclk_tx_reset_i, + gtwiz_userclk_tx_srcclk_out => userclk_tx_srcclk_i, + gtwiz_userclk_tx_usrclk_out => userclk_tx_usrclk_i, + gtwiz_userclk_tx_usrclk2_out => userclk_tx_usrclk2_i, + gtwiz_userclk_tx_active_out => userclk_tx_active_i, + gtwiz_userclk_rx_reset_in => userclk_rx_reset_i, + gtwiz_userclk_rx_srcclk_out => userclk_rx_srcclk_i, + gtwiz_userclk_rx_usrclk_out => userclk_rx_usrclk_i, + gtwiz_userclk_rx_usrclk2_out => userclk_rx_usrclk2_i, + gtwiz_userclk_rx_active_out => userclk_rx_active_i, + gtwiz_reset_clk_freerun_in => FREECLK, + gtwiz_reset_all_in => reset_all_i, + gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath_i, + gtwiz_reset_tx_datapath_in => reset_tx_datapath_i, + gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath_i, + gtwiz_reset_rx_datapath_in => reset_rx_datapath_i, + gtwiz_reset_rx_cdr_stable_out => reset_rx_cdr_stable_i, + gtwiz_reset_tx_done_out => reset_tx_done_i, + gtwiz_reset_rx_done_out => reset_rx_done_i, + gtwiz_userdata_tx_in => userdata_tx_i, + gtwiz_userdata_rx_out => userdata_rx_i, + gtrefclk00_in => mgtrefclk0_x0y3_int, + qpll0outclk_out => qpll0outclk_i, + qpll0outrefclk_out => qpll0outrefclk_i, + gthrxn_in => gthrxn_i, + gthrxp_in => gthrxp_i, + rx8b10ben_in => '1', + rxbufreset_in => '0', + rxcommadeten_in => rxcommadeten_i, + rxmcommaalignen_in => rxmcommaalignen_i, + rxpcommaalignen_in => rxpcommaalignen_i, + tx8b10ben_in => '1', + txctrl0_in => txctrl0_i, + txctrl1_in => txctrl1_i, + txctrl2_in => txctrl2_i, + gthtxn_out => gthtxn_i, + gthtxp_out => gthtxp_i, + gtpowergood_out => gtpowergood_i, + rxbufstatus_out => rxbufstatus_i, + rxbyteisaligned_out => rxbyteisaligned_i, + rxbyterealign_out => rxbyterealign_i, + rxclkcorcnt_out => rxclkcorcnt_i, + rxcommadet_out => rxcommadet_i, + rxctrl0_out => rxctrl0_i, + rxctrl1_out => rxctrl1_i, + rxctrl2_out => rxctrl2_i, + rxctrl3_out => rxctrl3_i, + rxpmaresetdone_out => rxpmaresetdone_i, + txpmaresetdone_out => txpmaresetdone_i + ); +end architecture behavioral; diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 0105c9f..075c8e5 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -45,7 +45,7 @@ entity trb_net16_endpoint_hades_full is REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; REGIO_INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR + REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR,c_I2C,c_XDNA REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; CLOCK_FREQUENCY : integer range 1 to 200 := 100 ); @@ -654,6 +654,25 @@ begin REGIO_ONEWIRE_MONITOR_OUT <= '0'; end generate; + gen_XilinxDNA : if REGIO_USE_1WIRE_INTERFACE = c_XDNA generate + + REGIO_IDRAM_DATA_OUT <= (others => '0'); + STAT_ONEWIRE <= (others => '0'); + REGIO_ONEWIRE_MONITOR_OUT <= '0'; + REGIO_ONEWIRE_INOUT <= '0'; + + XilinxDNA : entity work.trb_net_xdna + port map( + CLK => CLK, + RESET => RESET, + DATA_OUT => ONEWIRE_DATA, + ADDR_OUT => ONEWIRE_ADDR, + WRITE_OUT=> ONEWIRE_WRITE, + TEMP_OUT => temperature, + ID_OUT => UNIQUE_ID_OUT + ); + end generate; + gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate diff --git a/trb_net16_endpoint_hades_full_handler_record.vhd b/trb_net16_endpoint_hades_full_handler_record.vhd index c2fcdf8..6fc6f2e 100644 --- a/trb_net16_endpoint_hades_full_handler_record.vhd +++ b/trb_net16_endpoint_hades_full_handler_record.vhd @@ -20,7 +20,7 @@ entity trb_net16_endpoint_hades_full_handler_record is BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; - REGIO_USE_1WIRE_INTERFACE : integer range 0 to 3 := c_YES; + REGIO_USE_1WIRE_INTERFACE : integer range 0 to 4 := c_YES; TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; --Configure data handler DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 3b1466f..b581d92 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -64,6 +64,7 @@ package trb_net_std is constant c_NO : integer := 0; constant c_MONITOR : integer := 2; constant c_I2C : integer := 3; + constant c_XDNA : integer := 4; --standard values constant std_SBUF_VERSION : integer := c_SBUF_FULL; diff --git a/xilinx/xcku/fifo_1024x9x18_oreg_wcnt.vhd b/xilinx/xcku/fifo_1024x9x18_oreg_wcnt.vhd new file mode 100644 index 0000000..515a2dc --- /dev/null +++ b/xilinx/xcku/fifo_1024x9x18_oreg_wcnt.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_1024x9x18_oreg_wcnt is + port ( + Data : in std_logic_vector(8 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(17 downto 0); + WCNT : out std_logic_vector(9 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic; + AlmostFull : out std_logic + ); +end entity fifo_1024x9x18_oreg_wcnt; + +architecture structural of fifo_1024x9x18_oreg_wcnt is + component fifo_1024x9x18_oreg_wcnt_xcku + port ( + rst : in std_logic; + wr_clk : in std_logic; + rd_clk : in std_logic; + din : in std_logic_vector(8 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(17 downto 0); + full : out std_logic; + almost_full : out std_logic; + empty : out std_logic; + almost_empty : out std_logic; + wr_data_count : out std_logic_vector(9 downto 0) + ); + end component; +begin + fifo : fifo_1024x9x18_oreg_wcnt_xcku + port map ( + rst => Reset, + wr_clk => WrClock, + rd_clk => RdClock, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + dout => Q, + full => Full, + almost_full => AlmostFull, + empty => Empty, + almost_empty => AlmostEmpty, + wr_data_count => WCNT + ); +end architecture structural; diff --git a/xilinx/xcku/fifo_1024x9x18_oreg_wcnt_xcku/fifo_1024x9x18_oreg_wcnt_xcku.xci b/xilinx/xcku/fifo_1024x9x18_oreg_wcnt_xcku/fifo_1024x9x18_oreg_wcnt_xcku.xci new file mode 100644 index 0000000..651bf34 --- /dev/null +++ b/xilinx/xcku/fifo_1024x9x18_oreg_wcnt_xcku/fifo_1024x9x18_oreg_wcnt_xcku.xci @@ -0,0 +1,569 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_1024x9x18_oreg_wcnt_xcku + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 10 + BlankString + 9 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 18 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintexu + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 2 + 1 + 1kx18 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1021 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 1020 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 9 + 512 + 1 + 9 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + true + true + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_1024x9x18_oreg_wcnt_xcku + 64 + false + 10 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 1021 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 1020 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 9 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 512 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 9 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + true + false + false + false + Active_High + 0 + false + Active_High + 1 + true + 10 + true + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintexu + + + xcku115 + flvf1924 + VHDL + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2020.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/xcku/fifo_1024x9x18_oreg_wcnt_xcku/fifo_1024x9x18_oreg_wcnt_xcku.xml b/xilinx/xcku/fifo_1024x9x18_oreg_wcnt_xcku/fifo_1024x9x18_oreg_wcnt_xcku.xml new file mode 100644 index 0000000..e441297 --- /dev/null +++ b/xilinx/xcku/fifo_1024x9x18_oreg_wcnt_xcku/fifo_1024x9x18_oreg_wcnt_xcku.xml @@ -0,0 +1,10745 @@ + + + xilinx.com + customized_ip + fifo_1024x9x18_oreg_wcnt_xcku + 1.0 + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TDEST + + + m_axis_tdest + + + + + TID + + + m_axis_tid + + + + + TKEEP + + + m_axis_tkeep + + + + + TLAST + + + m_axis_tlast + + + + + TREADY + + + m_axis_tready + + + + + TSTRB + + + m_axis_tstrb + + + + + TUSER + + + m_axis_tuser + + + + + TVALID + + + m_axis_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + LAYERED_METADATA + undef + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + + + + false + + + + + + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TDEST + + + s_axis_tdest + + + + + TID + + + s_axis_tid + + + + + TKEEP + + + s_axis_tkeep + + + + + TLAST + + + s_axis_tlast + + + + + TREADY + + + s_axis_tready + + + + + TSTRB + + + s_axis_tstrb + + + + + TUSER + + + s_axis_tuser + + + + + TVALID + + + s_axis_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + 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+ 0 + + + C_APPLICATION_TYPE_RACH + 0 + + + C_APPLICATION_TYPE_RDCH + 0 + + + C_APPLICATION_TYPE_AXIS + 0 + + + C_PRIM_FIFO_TYPE_WACH + 512x36 + + + C_PRIM_FIFO_TYPE_WDCH + 512x72 + + + C_PRIM_FIFO_TYPE_WRCH + 512x36 + + + C_PRIM_FIFO_TYPE_RACH + 512x36 + + + C_PRIM_FIFO_TYPE_RDCH + 512x72 + + + C_PRIM_FIFO_TYPE_AXIS + 1kx18 + + + C_USE_ECC_WACH + 0 + + + C_USE_ECC_WDCH + 0 + + + C_USE_ECC_WRCH + 0 + + + C_USE_ECC_RACH + 0 + + + C_USE_ECC_RDCH + 0 + + + C_USE_ECC_AXIS + 0 + + + C_ERROR_INJECTION_TYPE_WACH + 0 + + + C_ERROR_INJECTION_TYPE_WDCH + 0 + + + C_ERROR_INJECTION_TYPE_WRCH + 0 + + + C_ERROR_INJECTION_TYPE_RACH + 0 + + + C_ERROR_INJECTION_TYPE_RDCH + 0 + + + C_ERROR_INJECTION_TYPE_AXIS + 0 + + + C_DIN_WIDTH_WACH + 1 + + + C_DIN_WIDTH_WDCH + 64 + + + C_DIN_WIDTH_WRCH + 2 + + + C_DIN_WIDTH_RACH + 32 + + + C_DIN_WIDTH_RDCH + 64 + + + C_DIN_WIDTH_AXIS + 1 + + + C_WR_DEPTH_WACH + 16 + + + C_WR_DEPTH_WDCH + 1024 + + + C_WR_DEPTH_WRCH + 16 + + + C_WR_DEPTH_RACH + 16 + + + C_WR_DEPTH_RDCH + 1024 + + + C_WR_DEPTH_AXIS + 1024 + + + C_WR_PNTR_WIDTH_WACH + 4 + + + C_WR_PNTR_WIDTH_WDCH + 10 + + + C_WR_PNTR_WIDTH_WRCH + 4 + + + C_WR_PNTR_WIDTH_RACH + 4 + + + C_WR_PNTR_WIDTH_RDCH + 10 + + + C_WR_PNTR_WIDTH_AXIS + 10 + + + C_HAS_DATA_COUNTS_WACH + 0 + + + C_HAS_DATA_COUNTS_WDCH + 0 + + + C_HAS_DATA_COUNTS_WRCH + 0 + + + C_HAS_DATA_COUNTS_RACH + 0 + + + C_HAS_DATA_COUNTS_RDCH + 0 + + + C_HAS_DATA_COUNTS_AXIS + 0 + + + C_HAS_PROG_FLAGS_WACH + 0 + + + C_HAS_PROG_FLAGS_WDCH + 0 + + + C_HAS_PROG_FLAGS_WRCH + 0 + + + C_HAS_PROG_FLAGS_RACH + 0 + + + C_HAS_PROG_FLAGS_RDCH + 0 + + + C_HAS_PROG_FLAGS_AXIS + 0 + + + C_PROG_FULL_TYPE_WACH + 0 + + + C_PROG_FULL_TYPE_WDCH + 0 + + + C_PROG_FULL_TYPE_WRCH + 0 + + + C_PROG_FULL_TYPE_RACH + 0 + + + C_PROG_FULL_TYPE_RDCH + 0 + + + C_PROG_FULL_TYPE_AXIS + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WRCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_165ed04b + 64 + + + choice_list_26900833 + 9 + 18 + 36 + 72 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_0721dec1 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Multiple_Programmable_Empty_Threshold_Constants + Single_Programmable_Empty_Threshold_Input_Port + Multiple_Programmable_Empty_Threshold_Input_Ports + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_26bda4ef + Asynchronous_Reset + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_541ed8d9 + Embedded_Reg + Fabric_Reg + Both + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_88535724 + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Multiple_Programmable_Full_Threshold_Constants + Single_Programmable_Full_Threshold_Input_Port + Multiple_Programmable_Full_Threshold_Input_Ports + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + fifo_1024x9x18_oreg_wcnt_xcku + + + + true + + + + + + Fifo_Implementation + Independent_Clocks_Block_RAM + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + true + + + + true + + + + + + Input_Data_Width + 9 + + + + true + + + + + + Input_Depth + 1024 + + + + true + + + + + + Output_Data_Width + 18 + + + + true + + + + + + Output_Depth + 512 + + + + false + + + + + + Enable_ECC + false + + + + false + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + true + + + + + + Enable_Reset_Synchronization + true + + + + true + + + + + + Reset_Type + Asynchronous_Reset + + + + false + + + + + + Full_Flags_Reset_Value + 1 + + + + true + + + + + + Use_Dout_Reset + true + + + + true + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + false + + + + + + Almost_Full_Flag + true + + + + true + + + + + + Almost_Empty_Flag + true + + + + true + + + + + + Valid_Flag + false + + + + true + + + + + + Valid_Sense + Active_High + + + + false + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + false + + + + false + + + + + + Data_Count_Width + 10 + + + + false + + + + + + Write_Data_Count + true + + + + true + + + + + + Write_Data_Count_Width + 10 + + + + true + + + + + + Read_Data_Count + false + + + + true + + + + + + Read_Data_Count_Width + 9 + + + + false + + + + + + Disable_Timing_Violations + false + + + + true + + + + + + Read_Clock_Frequency + 1 + + + + false + + + + + + Write_Clock_Frequency + 1 + + + + false + + + + + + Programmable_Full_Type + No_Programmable_Full_Threshold + + + + true + + + + + + Full_Threshold_Assert_Value + 1021 + + + + false + + + + + + Full_Threshold_Negate_Value + 1020 + + + + false + + + + + + Programmable_Empty_Type + No_Programmable_Empty_Threshold + + + + true + + + + + + Empty_Threshold_Assert_Value + 2 + + + + false + + + + + + Empty_Threshold_Negate_Value + 3 + + + + false + + + + + + PROTOCOL + AXI4 + + + + false + + + + + + Clock_Type_AXI + Common_Clock + + + + true + + + + + + HAS_ACLKEN + false + + + + false + + + + + + Clock_Enable_Type + Slave_Interface_Clock_Enable + + + + false + + + + + + READ_WRITE_MODE + READ_WRITE + + + + true + + + + + + ID_WIDTH + 0 + + + + false + + + + + + ADDRESS_WIDTH + 32 + + + + false + + + + + + DATA_WIDTH + 64 + + + + false + + + + + + AWUSER_Width + 0 + + + + false + + + + + + WUSER_Width + 0 + + + + false + + + + + + BUSER_Width + 0 + + + + false + + + + + + ARUSER_Width + 0 + + + + false + + + + + + RUSER_Width + 0 + + + + false + + + + + + TDATA_NUM_BYTES + 1 + + + + true + + + + + + TID_WIDTH + 0 + + + + false + + + + + + TDEST_WIDTH + 0 + + + + false + + + + + + TUSER_WIDTH + 4 + + + + false + + + + + + Enable_TREADY + true + + + + false + + + + + + Enable_TLAST + false + + + + true + + + + + + HAS_TSTRB + false + + + + false + + + + + + TSTRB_WIDTH + 1 + + + + false + + + + + + HAS_TKEEP + false + + + + false + + + + + + TKEEP_WIDTH + 1 + + + + false + + + + + + wach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wach + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wach + false + + + + false + + + + + + Inject_Sbit_Error_wach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wach + false + + + + false + + + + + + Input_Depth_wach + 16 + + + + true + + + + + + Enable_Data_Counts_wach + false + + + + false + + + + + + Programmable_Full_Type_wach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wdch + false + + + + false + + + + + + Inject_Sbit_Error_wdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wdch + false + + + + false + + + + + + Input_Depth_wdch + 1024 + + + + true + + + + + + Enable_Data_Counts_wdch + false + + + + false + + + + + + Programmable_Full_Type_wdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wrch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wrch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wrch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wrch + false + + + + false + + + + + + Inject_Sbit_Error_wrch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wrch + false + + + + false + + + + + + Input_Depth_wrch + 16 + + + + true + + + + + + Enable_Data_Counts_wrch + false + + + + false + + + + + + Programmable_Full_Type_wrch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wrch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wrch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wrch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rach + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rach + false + + + + false + + + + + + Inject_Sbit_Error_rach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rach + false + + + + false + + + + + + Input_Depth_rach + 16 + + + + true + + + + + + Enable_Data_Counts_rach + false + + + + false + + + + + + Programmable_Full_Type_rach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rdch + false + + + + false + + + + + + Inject_Sbit_Error_rdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rdch + false + + + + false + + + + + + Input_Depth_rdch + 1024 + + + + true + + + + + + Enable_Data_Counts_rdch + false + + + + false + + + + + + Programmable_Full_Type_rdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + axis_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_axis + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_axis + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_axis + false + + + + false + + + + + + Inject_Sbit_Error_axis + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_axis + Double Bit Error Injection + false + + + + false + + + + + + Input_Depth_axis + 1024 + + + + true + + + + + + Enable_Data_Counts_axis + false + + + + false + + + + + + Programmable_Full_Type_axis + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_axis + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_axis + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_axis + Empty Threshold Assert Value + 1022 + + + + false + + + + + + Register_Slice_Mode_wach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wrch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_axis + Register Slice Options + Fully_Registered + + + + true + + + + + + Underflow_Flag_AXI + Underflow Flag + false + + + + false + + + + + + Underflow_Sense_AXI + Underflow (Read Error) + Active_High + + + + false + + + + + + Overflow_Flag_AXI + Overflow Flag + false + + + + false + + + + + + Overflow_Sense_AXI + Overflow (Write Error) + Active_High + + + + false + + + + + + Disable_Timing_Violations_AXI + false + + + + true + + + + + + Add_NGC_Constraint_AXI + false + + + + true + + + + + + Enable_Common_Underflow + false + + + + true + + + + + + Enable_Common_Overflow + false + + + + true + + + + + + enable_read_pointer_increment_by2 + false + + + + true + + + + + + Use_Embedded_Registers_axis + false + + + + false + + + + + + enable_low_latency + false + + + + false + + + + + + use_dout_register + false + + + + false + + + + + + Master_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Slave_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Output_Register_Type + Embedded_Reg + + + + true + + + + + + Enable_Safety_Circuit + false + + + + true + + + + + + Enable_ECC_Type + Hard_ECC + + + + false + + + + + + C_SELECT_XPM + 0 + + + + + FIFO Generator + + XPM_MEMORY + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + diff --git a/xilinx/xcku/fifo_16x18x9_oreg.vhd b/xilinx/xcku/fifo_16x18x9_oreg.vhd new file mode 100644 index 0000000..8feddd6 --- /dev/null +++ b/xilinx/xcku/fifo_16x18x9_oreg.vhd @@ -0,0 +1,51 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_16x18x9_oreg is + port ( + Data : in std_logic_vector(17 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(8 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic; + AlmostFull : out std_logic + ); +end entity fifo_16x18x9_oreg; + +architecture structural of fifo_16x18x9_oreg is + component fifo_16x18x9_oreg_xcku + port ( + rst : in std_logic; + wr_clk : in std_logic; + rd_clk : in std_logic; + din : in std_logic_vector(17 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(8 downto 0); + full : out std_logic; + almost_full : out std_logic; + empty : out std_logic; + almost_empty : out std_logic + ); + end component; +begin + fifo : fifo_16x18x9_oreg_xcku + port map ( + rst => Reset, + wr_clk => WrClock, + rd_clk => RdClock, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + dout => Q, + full => Full, + almost_full => AlmostFull, + empty => Empty, + almost_empty => AlmostEmpty + ); +end architecture structural; diff --git a/xilinx/xcku/fifo_16x18x9_oreg_xcku/fifo_16x18x9_oreg_xcku.xci b/xilinx/xcku/fifo_16x18x9_oreg_xcku/fifo_16x18x9_oreg_xcku.xci new file mode 100644 index 0000000..f2f10c9 --- /dev/null +++ b/xilinx/xcku/fifo_16x18x9_oreg_xcku/fifo_16x18x9_oreg_xcku.xci @@ -0,0 +1,571 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_16x18x9_oreg_xcku + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 4 + BlankString + 18 + 1 + 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b/xilinx/xcku/fifo_16x18x9_oreg_xcku/fifo_16x18x9_oreg_xcku.xml new file mode 100644 index 0000000..18d23e6 --- /dev/null +++ b/xilinx/xcku/fifo_16x18x9_oreg_xcku/fifo_16x18x9_oreg_xcku.xml @@ -0,0 +1,10745 @@ + + + xilinx.com + customized_ip + fifo_16x18x9_oreg_xcku + 1.0 + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TDEST + + + m_axis_tdest + + + + + TID + + + m_axis_tid + + + + + TKEEP + + + m_axis_tkeep + + + + + TLAST + + + m_axis_tlast + + + + + TREADY + + + m_axis_tready + + + + + TSTRB + + + m_axis_tstrb + + + + + TUSER + + + m_axis_tuser + + + + + TVALID + + + m_axis_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + HAS_TREADY + 0 + + + none + + + + + HAS_TSTRB + 0 + + + none + + + + + HAS_TKEEP + 0 + + + none + + + + + HAS_TLAST + 0 + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + 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+ C_HAS_RST + 1 + + + C_HAS_SRST + 0 + + + C_HAS_UNDERFLOW + 0 + + + C_HAS_VALID + 0 + + + C_HAS_WR_ACK + 0 + + + C_HAS_WR_DATA_COUNT + 0 + + + C_HAS_WR_RST + 0 + + + C_IMPLEMENTATION_TYPE + 2 + + + C_INIT_WR_PNTR_VAL + 0 + + + C_MEMORY_TYPE + 1 + + + C_MIF_FILE_NAME + BlankString + + + C_OPTIMIZATION_MODE + 0 + + + C_OVERFLOW_LOW + 0 + + + C_PRELOAD_LATENCY + 2 + + + C_PRELOAD_REGS + 1 + + + C_PRIM_FIFO_TYPE + 512x36 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL + 2 + + + C_PROG_EMPTY_THRESH_NEGATE_VAL + 3 + + + C_PROG_EMPTY_TYPE + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL + 13 + + + C_PROG_FULL_THRESH_NEGATE_VAL + 12 + + + C_PROG_FULL_TYPE + 0 + + + C_RD_DATA_COUNT_WIDTH + 5 + + + C_RD_DEPTH + 32 + + + C_RD_FREQ + 1 + + + C_RD_PNTR_WIDTH + 5 + + + C_UNDERFLOW_LOW + 0 + + + C_USE_DOUT_RST + 1 + + + C_USE_ECC + 0 + + + C_USE_EMBEDDED_REG + 1 + + + C_USE_PIPELINE_REG + 0 + + + C_POWER_SAVING_MODE + 0 + + + C_USE_FIFO16_FLAGS + 0 + + + C_USE_FWFT_DATA_COUNT + 0 + + + C_VALID_LOW + 0 + + + C_WR_ACK_LOW + 0 + + + C_WR_DATA_COUNT_WIDTH + 4 + + + C_WR_DEPTH + 16 + + + C_WR_FREQ + 1 + + + C_WR_PNTR_WIDTH + 4 + + + C_WR_RESPONSE_LATENCY + 1 + + + C_MSGON_VAL + 1 + + + C_ENABLE_RST_SYNC + 1 + + + C_EN_SAFETY_CKT + 0 + + + C_ERROR_INJECTION_TYPE + 0 + + + C_SYNCHRONIZER_STAGE + 2 + + + C_INTERFACE_TYPE + 0 + + + C_AXI_TYPE + 1 + + + C_HAS_AXI_WR_CHANNEL + 1 + + + C_HAS_AXI_RD_CHANNEL + 1 + + + C_HAS_SLAVE_CE + 0 + + + C_HAS_MASTER_CE + 0 + + + C_ADD_NGC_CONSTRAINT + 0 + + + C_USE_COMMON_OVERFLOW + 0 + + + C_USE_COMMON_UNDERFLOW + 0 + + + C_USE_DEFAULT_SETTINGS + 0 + + + C_AXI_ID_WIDTH + 1 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 64 + + + C_AXI_LEN_WIDTH + 8 + + + C_AXI_LOCK_WIDTH + 1 + + + C_HAS_AXI_ID + 0 + + + C_HAS_AXI_AWUSER + 0 + + + C_HAS_AXI_WUSER + 0 + + + C_HAS_AXI_BUSER + 0 + + + C_HAS_AXI_ARUSER + 0 + + + C_HAS_AXI_RUSER + 0 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_HAS_AXIS_TDATA + 1 + + + C_HAS_AXIS_TID + 0 + + + C_HAS_AXIS_TDEST + 0 + + + C_HAS_AXIS_TUSER + 1 + + + C_HAS_AXIS_TREADY + 1 + + + C_HAS_AXIS_TLAST + 0 + + + C_HAS_AXIS_TSTRB + 0 + + + C_HAS_AXIS_TKEEP + 0 + + + C_AXIS_TDATA_WIDTH + 8 + + + C_AXIS_TID_WIDTH + 1 + + + C_AXIS_TDEST_WIDTH + 1 + + + C_AXIS_TUSER_WIDTH + 4 + + + C_AXIS_TSTRB_WIDTH + 1 + + + C_AXIS_TKEEP_WIDTH + 1 + + + C_WACH_TYPE + 0 + + + C_WDCH_TYPE + 0 + + + C_WRCH_TYPE + 0 + + + C_RACH_TYPE + 0 + + + C_RDCH_TYPE + 0 + + + C_AXIS_TYPE + 0 + + + C_IMPLEMENTATION_TYPE_WACH + 1 + + + C_IMPLEMENTATION_TYPE_WDCH + 1 + + + C_IMPLEMENTATION_TYPE_WRCH + 1 + + + C_IMPLEMENTATION_TYPE_RACH + 1 + + + C_IMPLEMENTATION_TYPE_RDCH + 1 + + + C_IMPLEMENTATION_TYPE_AXIS + 1 + + + C_APPLICATION_TYPE_WACH + 0 + + + C_APPLICATION_TYPE_WDCH + 0 + + + C_APPLICATION_TYPE_WRCH + 0 + + + C_APPLICATION_TYPE_RACH + 0 + + + C_APPLICATION_TYPE_RDCH + 0 + + + C_APPLICATION_TYPE_AXIS + 0 + + + C_PRIM_FIFO_TYPE_WACH + 512x36 + + + C_PRIM_FIFO_TYPE_WDCH + 512x72 + + + C_PRIM_FIFO_TYPE_WRCH + 512x36 + + + C_PRIM_FIFO_TYPE_RACH + 512x36 + + + C_PRIM_FIFO_TYPE_RDCH + 512x72 + + + C_PRIM_FIFO_TYPE_AXIS + 1kx18 + + + C_USE_ECC_WACH + 0 + + + C_USE_ECC_WDCH + 0 + + + C_USE_ECC_WRCH + 0 + + + C_USE_ECC_RACH + 0 + + + C_USE_ECC_RDCH + 0 + + + C_USE_ECC_AXIS + 0 + + + C_ERROR_INJECTION_TYPE_WACH + 0 + + + C_ERROR_INJECTION_TYPE_WDCH + 0 + + + C_ERROR_INJECTION_TYPE_WRCH + 0 + + + C_ERROR_INJECTION_TYPE_RACH + 0 + + + C_ERROR_INJECTION_TYPE_RDCH + 0 + + + C_ERROR_INJECTION_TYPE_AXIS + 0 + + + C_DIN_WIDTH_WACH + 1 + + + C_DIN_WIDTH_WDCH + 64 + + + C_DIN_WIDTH_WRCH + 2 + + + C_DIN_WIDTH_RACH + 32 + + + C_DIN_WIDTH_RDCH + 64 + + + C_DIN_WIDTH_AXIS + 1 + + + C_WR_DEPTH_WACH + 16 + + + C_WR_DEPTH_WDCH + 1024 + + + C_WR_DEPTH_WRCH + 16 + + + C_WR_DEPTH_RACH + 16 + + + C_WR_DEPTH_RDCH + 1024 + + + C_WR_DEPTH_AXIS + 1024 + + + C_WR_PNTR_WIDTH_WACH + 4 + + + C_WR_PNTR_WIDTH_WDCH + 10 + + + C_WR_PNTR_WIDTH_WRCH + 4 + + + C_WR_PNTR_WIDTH_RACH + 4 + + + C_WR_PNTR_WIDTH_RDCH + 10 + + + C_WR_PNTR_WIDTH_AXIS + 10 + + + C_HAS_DATA_COUNTS_WACH + 0 + + + C_HAS_DATA_COUNTS_WDCH + 0 + + + C_HAS_DATA_COUNTS_WRCH + 0 + + + C_HAS_DATA_COUNTS_RACH + 0 + + + C_HAS_DATA_COUNTS_RDCH + 0 + + + C_HAS_DATA_COUNTS_AXIS + 0 + + + C_HAS_PROG_FLAGS_WACH + 0 + + + C_HAS_PROG_FLAGS_WDCH + 0 + + + C_HAS_PROG_FLAGS_WRCH + 0 + + + C_HAS_PROG_FLAGS_RACH + 0 + + + C_HAS_PROG_FLAGS_RDCH + 0 + + + C_HAS_PROG_FLAGS_AXIS + 0 + + + C_PROG_FULL_TYPE_WACH + 0 + + + C_PROG_FULL_TYPE_WDCH + 0 + + + C_PROG_FULL_TYPE_WRCH + 0 + + + C_PROG_FULL_TYPE_RACH + 0 + + + C_PROG_FULL_TYPE_RDCH + 0 + + + C_PROG_FULL_TYPE_AXIS + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WRCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_165ed04b + 64 + + + choice_list_537e964c + 9 + 18 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_0721dec1 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Multiple_Programmable_Empty_Threshold_Constants + Single_Programmable_Empty_Threshold_Input_Port + Multiple_Programmable_Empty_Threshold_Input_Ports + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_26bda4ef + Asynchronous_Reset + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_541ed8d9 + Embedded_Reg + Fabric_Reg + Both + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_88535724 + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Multiple_Programmable_Full_Threshold_Constants + Single_Programmable_Full_Threshold_Input_Port + Multiple_Programmable_Full_Threshold_Input_Ports + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + fifo_16x18x9_oreg_xcku + + + + true + + + + + + Fifo_Implementation + Independent_Clocks_Block_RAM + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + true + + + + true + + + + + + Input_Data_Width + 18 + + + + true + + + + + + Input_Depth + 16 + + + + true + + + + + + Output_Data_Width + 9 + + + + true + + + + + + Output_Depth + 32 + + + + false + + + + + + Enable_ECC + false + + + + false + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + true + + + + + + Enable_Reset_Synchronization + true + + + + true + + + + + + Reset_Type + Asynchronous_Reset + + + + false + + + + + + Full_Flags_Reset_Value + 1 + + + + true + + + + + + Use_Dout_Reset + true + + + + true + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + false + + + + + + Almost_Full_Flag + true + + + + true + + + + + + Almost_Empty_Flag + true + + + + true + + + + + + Valid_Flag + false + + + + true + + + + + + Valid_Sense + Active_High + + + + false + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + false + + + + false + + + + + + Data_Count_Width + 4 + + + + false + + + + + + Write_Data_Count + false + + + + true + + + + + + Write_Data_Count_Width + 4 + + + + false + + + + + + Read_Data_Count + false + + + + true + + + + + + Read_Data_Count_Width + 5 + + + + false + + + + + + Disable_Timing_Violations + false + + + + true + + + + + + Read_Clock_Frequency + 1 + + + + false + + + + + + Write_Clock_Frequency + 1 + + + + false + + + + + + Programmable_Full_Type + No_Programmable_Full_Threshold + + + + true + + + + + + Full_Threshold_Assert_Value + 13 + + + + false + + + + + + Full_Threshold_Negate_Value + 12 + + + + false + + + + + + Programmable_Empty_Type + No_Programmable_Empty_Threshold + + + + true + + + + + + Empty_Threshold_Assert_Value + 2 + + + + false + + + + + + Empty_Threshold_Negate_Value + 3 + + + + false + + + + + + PROTOCOL + AXI4 + + + + false + + + + + + Clock_Type_AXI + Common_Clock + + + + true + + + + + + HAS_ACLKEN + false + + + + false + + + + + + Clock_Enable_Type + Slave_Interface_Clock_Enable + + + + false + + + + + + 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RPReset : in std_logic; + Q : out std_logic_vector(17 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); +end entity fifo_18x16_dualport_oreg; + +architecture structural of fifo_18x16_dualport_oreg is + component fifo_18x16_dualport_oreg_xcku + port ( + rst : in std_logic; + wr_clk : in std_logic; + rd_clk : in std_logic; + din : in std_logic_vector(17 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(17 downto 0); + full : out std_logic; + empty : out std_logic; + prog_full : out std_logic + ); + end component; +begin + fifo : fifo_18x16_dualport_oreg_xcku + port map ( + rst => Reset, + wr_clk => WrClock, + rd_clk => RdClock, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + dout => Q, + full => Full, + empty => Empty, + prog_full => AlmostFull + ); +end architecture structural; diff --git a/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci 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C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_165ed04b + 64 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_list_fa1519db + 18 + 9 + 18 + + + choice_pairs_0721dec1 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Multiple_Programmable_Empty_Threshold_Constants + Single_Programmable_Empty_Threshold_Input_Port + Multiple_Programmable_Empty_Threshold_Input_Ports + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_26bda4ef + Asynchronous_Reset + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_541ed8d9 + Embedded_Reg + Fabric_Reg + Both + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_88535724 + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Multiple_Programmable_Full_Threshold_Constants + Single_Programmable_Full_Threshold_Input_Port + Multiple_Programmable_Full_Threshold_Input_Ports + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + fifo_18x16_dualport_oreg_xcku + + + + true + + + + + + Fifo_Implementation + Independent_Clocks_Block_RAM + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + false + + + + true + + + + + + Input_Data_Width + 18 + + + + true + + + + + + Input_Depth + 16 + + + + true + + + + + + Output_Data_Width + 18 + + + + false + + + + + + Output_Depth + 16 + + + + false + + + + + + Enable_ECC + false + + + + true + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + true + + + + + + Enable_Reset_Synchronization + true + + + + true + + + + + + Reset_Type + Asynchronous_Reset + + + + false + + + + + + Full_Flags_Reset_Value + 1 + + + + true + + + + + + Use_Dout_Reset + true + + + + true + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + false + + + + + + Almost_Full_Flag + false + + + + true + + + + + + Almost_Empty_Flag + false + + + + true + + + + + + Valid_Flag + false + + + + true + + + + + + Valid_Sense + Active_High + + + + false + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + false + + + + false + + + + + + Data_Count_Width + 4 + + + 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+ + + + + + READ_WRITE_MODE + READ_WRITE + + + + true + + + + + + ID_WIDTH + 0 + + + + false + + + + + + ADDRESS_WIDTH + 32 + + + + false + + + + + + DATA_WIDTH + 64 + + + + false + + + + + + AWUSER_Width + 0 + + + + false + + + + + + WUSER_Width + 0 + + + + false + + + + + + BUSER_Width + 0 + + + + false + + + + + + ARUSER_Width + 0 + + + + false + + + + + + RUSER_Width + 0 + + + + false + + + + + + TDATA_NUM_BYTES + 1 + + + + true + + + + + + TID_WIDTH + 0 + + + + false + + + + + + TDEST_WIDTH + 0 + + + + false + + + + + + TUSER_WIDTH + 4 + + + + false + + + + + + Enable_TREADY + true + + + + false + + + + + + Enable_TLAST + false + + + + true + + + + + + HAS_TSTRB + false + + + + false + + + + + + TSTRB_WIDTH + 1 + + + + false + + + + + + HAS_TKEEP + false + + + + false + + + + + + TKEEP_WIDTH + 1 + + + + false + + + + + + wach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wach + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wach + false + + + + false + + + + + + Inject_Sbit_Error_wach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wach + false + + + + false + + + + + + Input_Depth_wach + 16 + + + + true + + + + + + Enable_Data_Counts_wach + false + + + + false + + + + + + Programmable_Full_Type_wach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wdch + false + + + + false + + + + + + Inject_Sbit_Error_wdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wdch + false + + + + false + + + + + + Input_Depth_wdch + 1024 + + + + true + + + + + + Enable_Data_Counts_wdch + false + + + + false + + + + + + Programmable_Full_Type_wdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wrch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wrch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wrch + FIFO Application Type + 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+ + Enable_ECC_rach + false + + + + false + + + + + + Inject_Sbit_Error_rach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rach + false + + + + false + + + + + + Input_Depth_rach + 16 + + + + true + + + + + + Enable_Data_Counts_rach + false + + + + false + + + + + + Programmable_Full_Type_rach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rdch + false + + + + false + + + + + + Inject_Sbit_Error_rdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rdch + false + + + + false + + + + + + Input_Depth_rdch + 1024 + + + + true + + + + + + Enable_Data_Counts_rdch + false + + + + false + + + + + + Programmable_Full_Type_rdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + axis_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_axis + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_axis + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_axis + false + + + + false + + + + + + Inject_Sbit_Error_axis + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_axis + Double Bit Error Injection + false + + + + false + + + + + + Input_Depth_axis + 1024 + + + + true + + + + + + Enable_Data_Counts_axis + false + + + + false + + + + + + Programmable_Full_Type_axis + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_axis + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_axis + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_axis + Empty Threshold Assert Value + 1022 + + + + false + + + + + + Register_Slice_Mode_wach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wrch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_axis + Register Slice Options + Fully_Registered + + + + true + + + + + + Underflow_Flag_AXI + Underflow Flag + false + + + + false + + + + + + Underflow_Sense_AXI + Underflow (Read Error) + Active_High + + + + false + + + + + + Overflow_Flag_AXI + Overflow Flag + false + + + + false + + + + + + Overflow_Sense_AXI + Overflow (Write Error) + Active_High + + + + false + + + + + + Disable_Timing_Violations_AXI + false + + + + true + + + + + + Add_NGC_Constraint_AXI + false + + + + true + + + + + + Enable_Common_Underflow + false + + + + true + + + + + + Enable_Common_Overflow + false + + + + true + + + + + + enable_read_pointer_increment_by2 + false + + + + true + + + + + + Use_Embedded_Registers_axis + false + + + + false + + + + + + enable_low_latency + false + + + + false + + + + + + use_dout_register + false + + + + false + + + + + + Master_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Slave_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Output_Register_Type + Embedded_Reg + + + + true + + + + + + Enable_Safety_Circuit + false + + + + true + + + + + + Enable_ECC_Type + Hard_ECC + + + + false + + + + + + C_SELECT_XPM + 0 + + + + + FIFO Generator + + XPM_MEMORY + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + diff --git a/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci b/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci new file mode 100644 index 0000000..32f8df1 --- /dev/null +++ b/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci @@ -0,0 +1,561 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_18x1k_xcku + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 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1kx18 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL + 2 + + + C_PROG_EMPTY_THRESH_NEGATE_VAL + 3 + + + C_PROG_EMPTY_TYPE + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL + 1020 + + + C_PROG_FULL_THRESH_NEGATE_VAL + 1019 + + + C_PROG_FULL_TYPE + 1 + + + C_RD_DATA_COUNT_WIDTH + 10 + + + C_RD_DEPTH + 1024 + + + C_RD_FREQ + 1 + + + C_RD_PNTR_WIDTH + 10 + + + C_UNDERFLOW_LOW + 0 + + + C_USE_DOUT_RST + 1 + + + C_USE_ECC + 0 + + + C_USE_EMBEDDED_REG + 0 + + + C_USE_PIPELINE_REG + 0 + + + C_POWER_SAVING_MODE + 0 + + + C_USE_FIFO16_FLAGS + 0 + + + C_USE_FWFT_DATA_COUNT + 0 + + + C_VALID_LOW + 0 + + + C_WR_ACK_LOW + 0 + + + C_WR_DATA_COUNT_WIDTH + 10 + + + C_WR_DEPTH + 1024 + + + C_WR_FREQ + 1 + + + C_WR_PNTR_WIDTH + 10 + + + C_WR_RESPONSE_LATENCY + 1 + + + C_MSGON_VAL + 1 + + + C_ENABLE_RST_SYNC + 1 + + + C_EN_SAFETY_CKT + 0 + + + C_ERROR_INJECTION_TYPE + 0 + + + C_SYNCHRONIZER_STAGE + 2 + + + C_INTERFACE_TYPE + 0 + + + C_AXI_TYPE + 1 + + + C_HAS_AXI_WR_CHANNEL + 1 + + + C_HAS_AXI_RD_CHANNEL + 1 + + + C_HAS_SLAVE_CE + 0 + + + C_HAS_MASTER_CE + 0 + + + C_ADD_NGC_CONSTRAINT + 0 + + + C_USE_COMMON_OVERFLOW + 0 + + + C_USE_COMMON_UNDERFLOW + 0 + + + C_USE_DEFAULT_SETTINGS + 0 + + + C_AXI_ID_WIDTH + 1 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 64 + + + C_AXI_LEN_WIDTH + 8 + + + C_AXI_LOCK_WIDTH + 1 + + + C_HAS_AXI_ID + 0 + + + C_HAS_AXI_AWUSER + 0 + + + C_HAS_AXI_WUSER + 0 + + + C_HAS_AXI_BUSER + 0 + + + C_HAS_AXI_ARUSER + 0 + + + C_HAS_AXI_RUSER + 0 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_HAS_AXIS_TDATA + 1 + + + C_HAS_AXIS_TID + 0 + + + C_HAS_AXIS_TDEST + 0 + + + C_HAS_AXIS_TUSER + 1 + + + C_HAS_AXIS_TREADY + 1 + + + C_HAS_AXIS_TLAST + 0 + + + C_HAS_AXIS_TSTRB + 0 + + + C_HAS_AXIS_TKEEP + 0 + + + C_AXIS_TDATA_WIDTH + 8 + + + C_AXIS_TID_WIDTH + 1 + + + C_AXIS_TDEST_WIDTH + 1 + + + C_AXIS_TUSER_WIDTH + 4 + + + C_AXIS_TSTRB_WIDTH + 1 + + + C_AXIS_TKEEP_WIDTH + 1 + + + C_WACH_TYPE + 0 + + + C_WDCH_TYPE + 0 + + + C_WRCH_TYPE + 0 + + + C_RACH_TYPE + 0 + + + C_RDCH_TYPE + 0 + + + C_AXIS_TYPE + 0 + + + C_IMPLEMENTATION_TYPE_WACH + 1 + + + C_IMPLEMENTATION_TYPE_WDCH + 1 + + + C_IMPLEMENTATION_TYPE_WRCH + 1 + + + C_IMPLEMENTATION_TYPE_RACH + 1 + + + C_IMPLEMENTATION_TYPE_RDCH + 1 + + + C_IMPLEMENTATION_TYPE_AXIS + 1 + + + C_APPLICATION_TYPE_WACH + 0 + + + C_APPLICATION_TYPE_WDCH + 0 + + + C_APPLICATION_TYPE_WRCH + 0 + + + C_APPLICATION_TYPE_RACH + 0 + + + C_APPLICATION_TYPE_RDCH + 0 + + + C_APPLICATION_TYPE_AXIS + 0 + + + C_PRIM_FIFO_TYPE_WACH + 512x36 + + + C_PRIM_FIFO_TYPE_WDCH + 512x72 + + + C_PRIM_FIFO_TYPE_WRCH + 512x36 + + + C_PRIM_FIFO_TYPE_RACH + 512x36 + + + C_PRIM_FIFO_TYPE_RDCH + 512x72 + + + C_PRIM_FIFO_TYPE_AXIS + 1kx18 + + + C_USE_ECC_WACH + 0 + + + C_USE_ECC_WDCH + 0 + + + C_USE_ECC_WRCH + 0 + + + C_USE_ECC_RACH + 0 + + + C_USE_ECC_RDCH + 0 + + + C_USE_ECC_AXIS + 0 + + + C_ERROR_INJECTION_TYPE_WACH + 0 + + + C_ERROR_INJECTION_TYPE_WDCH + 0 + + + C_ERROR_INJECTION_TYPE_WRCH + 0 + + + C_ERROR_INJECTION_TYPE_RACH + 0 + + + C_ERROR_INJECTION_TYPE_RDCH + 0 + + + C_ERROR_INJECTION_TYPE_AXIS + 0 + + + C_DIN_WIDTH_WACH + 1 + + + C_DIN_WIDTH_WDCH + 64 + + + C_DIN_WIDTH_WRCH + 2 + + + C_DIN_WIDTH_RACH + 32 + + + C_DIN_WIDTH_RDCH + 64 + + + C_DIN_WIDTH_AXIS + 1 + + + C_WR_DEPTH_WACH + 16 + + + C_WR_DEPTH_WDCH + 1024 + + + C_WR_DEPTH_WRCH + 16 + + + C_WR_DEPTH_RACH + 16 + + + C_WR_DEPTH_RDCH + 1024 + + + C_WR_DEPTH_AXIS + 1024 + + + C_WR_PNTR_WIDTH_WACH + 4 + + + C_WR_PNTR_WIDTH_WDCH + 10 + + + C_WR_PNTR_WIDTH_WRCH + 4 + + + C_WR_PNTR_WIDTH_RACH + 4 + + + C_WR_PNTR_WIDTH_RDCH + 10 + + + C_WR_PNTR_WIDTH_AXIS + 10 + + + C_HAS_DATA_COUNTS_WACH + 0 + + + C_HAS_DATA_COUNTS_WDCH + 0 + + + C_HAS_DATA_COUNTS_WRCH + 0 + + + C_HAS_DATA_COUNTS_RACH + 0 + + + C_HAS_DATA_COUNTS_RDCH + 0 + + + C_HAS_DATA_COUNTS_AXIS + 0 + + + C_HAS_PROG_FLAGS_WACH + 0 + + + C_HAS_PROG_FLAGS_WDCH + 0 + + + C_HAS_PROG_FLAGS_WRCH + 0 + + + C_HAS_PROG_FLAGS_RACH + 0 + + + C_HAS_PROG_FLAGS_RDCH + 0 + + + C_HAS_PROG_FLAGS_AXIS + 0 + + + C_PROG_FULL_TYPE_WACH + 0 + + + C_PROG_FULL_TYPE_WDCH + 0 + + + C_PROG_FULL_TYPE_WRCH + 0 + + + C_PROG_FULL_TYPE_RACH + 0 + + + C_PROG_FULL_TYPE_RDCH + 0 + + + C_PROG_FULL_TYPE_AXIS + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WRCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_165ed04b + 64 + + + choice_list_1936dea0 + 18 + 9 + 18 + 36 + 72 + 144 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_0721dec1 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Multiple_Programmable_Empty_Threshold_Constants + Single_Programmable_Empty_Threshold_Input_Port + Multiple_Programmable_Empty_Threshold_Input_Ports + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_541ed8d9 + Embedded_Reg + Fabric_Reg + Both + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_88535724 + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Multiple_Programmable_Full_Threshold_Constants + Single_Programmable_Full_Threshold_Input_Port + Multiple_Programmable_Full_Threshold_Input_Ports + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_ae1178b5 + Asynchronous_Reset + Synchronous_Reset + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + fifo_18x1k_xcku + + + + true + + + + + + Fifo_Implementation + Common_Clock_Block_RAM + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + false + + + + true + + + + + + Input_Data_Width + 18 + + + + true + + + + + + Input_Depth + 1024 + + + + true + + + + + + Output_Data_Width + 18 + + + + false + + + + + + Output_Depth + 1024 + + + + false + + + + + + Enable_ECC + false + + + + true + + + + + + Use_Embedded_Registers + false + + + + true + + + + + + Reset_Pin + true + + + + true + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + true + + + + + + Full_Flags_Reset_Value + 0 + + + + false + + + + + + Use_Dout_Reset + true + + + + true + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + false + + + + + + Almost_Full_Flag + false + + + + true + + + + + + Almost_Empty_Flag + false + + + + true + + + + + + Valid_Flag + false + + + + true + + + + + + Valid_Sense + Active_High + + + + false + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + false + + + + true + + + + + + Data_Count_Width + 10 + + + + false + + + + + + Write_Data_Count + false + + + + false + + + + + + Write_Data_Count_Width + 10 + + + + false + + + + + + Read_Data_Count + false + + + + false + + + + + + Read_Data_Count_Width + 10 + + + + false + + + + + + Disable_Timing_Violations + false + + + + false + + + + + + Read_Clock_Frequency + 1 + + + + false + + + + + + Write_Clock_Frequency + 1 + + + + false + + + + + + Programmable_Full_Type + Single_Programmable_Full_Threshold_Constant + + + + true + + + + + + Full_Threshold_Assert_Value + 1020 + + + + true + + + + + + Full_Threshold_Negate_Value + 1019 + + + + false + + + + + + Programmable_Empty_Type + No_Programmable_Empty_Threshold + + + + true + + + + + + Empty_Threshold_Assert_Value + 2 + + + + false + + + + + + Empty_Threshold_Negate_Value + 3 + + + + false + + + + + + PROTOCOL + AXI4 + + + + false + + + + + + Clock_Type_AXI + Common_Clock + + + + true + + + + + + HAS_ACLKEN + false + + + + false + + + + + + Clock_Enable_Type + Slave_Interface_Clock_Enable + + + + false + + + + + + READ_WRITE_MODE + READ_WRITE + + + + true + + + + + + ID_WIDTH + 0 + + + + false + + + + + + ADDRESS_WIDTH + 32 + + + + false + + + + + + DATA_WIDTH + 64 + + + + false + + + + + + AWUSER_Width + 0 + + + + false + + + + + + WUSER_Width + 0 + + + + false + + + + + + BUSER_Width + 0 + + + + false + + + + + + ARUSER_Width + 0 + + + + false + + + + + + RUSER_Width + 0 + + + + false + + + + + + TDATA_NUM_BYTES + 1 + + + + true + + + + + + TID_WIDTH + 0 + + + + false + + + + + + TDEST_WIDTH + 0 + + + + false + + + + + + TUSER_WIDTH + 4 + + + + false + + + + + + Enable_TREADY + true + + + + false + + + + + + Enable_TLAST + false + + + + true + + + + + + HAS_TSTRB + false + + + + false + + + + + + TSTRB_WIDTH + 1 + + + + false + + + + + + HAS_TKEEP + false + + + + false + + + + + + TKEEP_WIDTH + 1 + + + + false + + + + + + wach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wach + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wach + false + + + + false + + + + + + Inject_Sbit_Error_wach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wach + false + + + + false + + + + + + Input_Depth_wach + 16 + + + + true + + + + + + Enable_Data_Counts_wach + false + + + + false + + + + + + Programmable_Full_Type_wach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wdch + false + + + + false + + + + + + Inject_Sbit_Error_wdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wdch + false + + + + false + + + + + + Input_Depth_wdch + 1024 + + + + true + + + + + + Enable_Data_Counts_wdch + false + + + + false + + + + + + Programmable_Full_Type_wdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wrch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wrch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wrch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wrch + false + + + + false + + + + + + Inject_Sbit_Error_wrch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wrch + false + + + + false + + + + + + Input_Depth_wrch + 16 + + + + true + + + + + + Enable_Data_Counts_wrch + false + + + + false + + + + + + Programmable_Full_Type_wrch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wrch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wrch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wrch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rach + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rach + false + + + + false + + + + + + Inject_Sbit_Error_rach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rach + false + + + + false + + + + + + Input_Depth_rach + 16 + + + + true + + + + + + Enable_Data_Counts_rach + false + + + + false + + + + + + Programmable_Full_Type_rach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rdch + false + + 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Inject_Sbit_Error_axis + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_axis + Double Bit Error Injection + false + + + + false + + + + + + Input_Depth_axis + 1024 + + + + true + + + + + + Enable_Data_Counts_axis + false + + + + false + + + + + + Programmable_Full_Type_axis + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_axis + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_axis + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_axis + Empty Threshold Assert Value + 1022 + + + + false + + + + + + Register_Slice_Mode_wach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wrch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rach 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: out std_logic_vector(17 downto 0); + WCNT : out std_logic_vector(9 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); +end fifo_18x512_oreg; + +architecture structural of fifo_18x512_oreg is + component fifo_18x512_oreg_xcku + port ( + clk : in std_logic; + srst : in std_logic; + din : in std_logic_vector(17 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + prog_full_thresh : in std_logic_vector(8 downto 0); + dout : out std_logic_vector(17 downto 0); + full : out std_logic; + empty : out std_logic; + data_count : out std_logic_vector(8 downto 0); + prog_full : out std_logic; + wr_rst_busy : out std_logic; + rd_rst_busy : out std_logic + ); + end component; +begin + fifo : fifo_18x512_oreg_xcku + port map ( + clk => Clock, + srst => Reset, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + prog_full_thresh => AmFullThresh, + dout => Q, + full => Full, + empty => Empty, + data_count => WCNT(8 downto 0), + prog_full => AlmostFull, + wr_rst_busy => open, + rd_rst_busy => open + ); + + -- TODO: Check impact of different count values + WCNT(9) <= '0'; +end architecture structural; diff --git a/xilinx/xcku/fifo_18x512_oreg_xcku/fifo_18x512_oreg_xcku.xci b/xilinx/xcku/fifo_18x512_oreg_xcku/fifo_18x512_oreg_xcku.xci new file mode 100644 index 0000000..65fdc29 --- /dev/null +++ b/xilinx/xcku/fifo_18x512_oreg_xcku/fifo_18x512_oreg_xcku.xci @@ -0,0 +1,566 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_18x512_oreg_xcku + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 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512 + + + choice_list_165ed04b + 64 + + + choice_list_1936dea0 + 18 + 9 + 18 + 36 + 72 + 144 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_0721dec1 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Multiple_Programmable_Empty_Threshold_Constants + Single_Programmable_Empty_Threshold_Input_Port + Multiple_Programmable_Empty_Threshold_Input_Ports + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_541ed8d9 + Embedded_Reg + Fabric_Reg + Both + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_88535724 + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Multiple_Programmable_Full_Threshold_Constants + Single_Programmable_Full_Threshold_Input_Port + Multiple_Programmable_Full_Threshold_Input_Ports + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_ae1178b5 + Asynchronous_Reset + Synchronous_Reset + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + fifo_18x512_oreg_xcku + + + + true + + + + + + Fifo_Implementation + Common_Clock_Block_RAM + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + false + + + + true + + + + + + Input_Data_Width + 18 + + + + true + + + + + + Input_Depth + 512 + + + + true + + + + + + Output_Data_Width + 18 + + + + false + + + + + + Output_Depth + 512 + + + + false + + + + + + Enable_ECC + false + + + + true + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + true + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + true + + + + + + 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false + + + + false + + + + + + Master_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Slave_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Output_Register_Type + Embedded_Reg + + + + true + + + + + + Enable_Safety_Circuit + false + + + + false + + + + + + Enable_ECC_Type + Hard_ECC + + + + false + + + + + + C_SELECT_XPM + 0 + + + + + FIFO Generator + + XPM_MEMORY + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + diff --git a/xilinx/xcku/fifo_19x16_obuf.vhd b/xilinx/xcku/fifo_19x16_obuf.vhd new file mode 100644 index 0000000..77914a0 --- /dev/null +++ b/xilinx/xcku/fifo_19x16_obuf.vhd @@ -0,0 +1,58 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_19x16_obuf is + port ( + Data : in std_logic_vector(18 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(3 downto 0); + Q : out std_logic_vector(18 downto 0); + WCNT : out std_logic_vector(4 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); +end entity fifo_19x16_obuf; + +architecture structural of fifo_19x16_obuf is + component fifo_19x16_obuf_xcku + port ( + clk : in std_logic; + srst : in std_logic; + din : in std_logic_vector(18 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + prog_full_thresh : in std_logic_vector(3 downto 0); + dout : out std_logic_vector(18 downto 0); + full : out std_logic; + empty : out std_logic; + data_count : out std_logic_vector(3 downto 0); + prog_full : out std_logic; + wr_rst_busy : out std_logic; + rd_rst_busy : out std_logic + ); + end component; +begin + fifo : fifo_19x16_obuf_xcku + port map ( + clk => Clock, + srst => Reset, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + prog_full_thresh => AmFullThresh, + dout => Q, + full => Full, + empty => Empty, + data_count => WCNT(3 downto 0), + prog_full => AlmostFull, + wr_rst_busy => open, + rd_rst_busy => open + ); + + -- TODO: Check impact of different count values + WCNT(4) <= '0'; +end architecture structural; diff --git a/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xci b/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xci new file mode 100644 index 0000000..0e81e3e --- /dev/null +++ b/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xci @@ -0,0 +1,569 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_19x16_obuf_xcku + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 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TRUE + IP_Flow + 5 + TRUE + . + + . + 2020.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xml b/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xml new file mode 100644 index 0000000..38d632d --- /dev/null +++ b/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xml @@ -0,0 +1,10744 @@ + + + xilinx.com + customized_ip + fifo_19x16_obuf_xcku + 1.0 + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TDEST + + + m_axis_tdest + + + + + TID + + + m_axis_tid + + + + + TKEEP + + + m_axis_tkeep + + + + + TLAST + + + m_axis_tlast + + + + + TREADY + + + m_axis_tready + + + + + TSTRB + + + m_axis_tstrb + + + + + TUSER + + + m_axis_tuser + + + + + TVALID + + + m_axis_tvalid + + + + + + TDATA_NUM_BYTES + 0 + + + none + + + + + TDEST_WIDTH + 0 + + + none + + + + + TID_WIDTH + 0 + + + none + + + + + TUSER_WIDTH + 0 + + + none + + + + + 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C_IMPLEMENTATION_TYPE_AXIS + 1 + + + C_APPLICATION_TYPE_WACH + 0 + + + C_APPLICATION_TYPE_WDCH + 0 + + + C_APPLICATION_TYPE_WRCH + 0 + + + C_APPLICATION_TYPE_RACH + 0 + + + C_APPLICATION_TYPE_RDCH + 0 + + + C_APPLICATION_TYPE_AXIS + 0 + + + C_PRIM_FIFO_TYPE_WACH + 512x36 + + + C_PRIM_FIFO_TYPE_WDCH + 512x72 + + + C_PRIM_FIFO_TYPE_WRCH + 512x36 + + + C_PRIM_FIFO_TYPE_RACH + 512x36 + + + C_PRIM_FIFO_TYPE_RDCH + 512x72 + + + C_PRIM_FIFO_TYPE_AXIS + 1kx18 + + + C_USE_ECC_WACH + 0 + + + C_USE_ECC_WDCH + 0 + + + C_USE_ECC_WRCH + 0 + + + C_USE_ECC_RACH + 0 + + + C_USE_ECC_RDCH + 0 + + + C_USE_ECC_AXIS + 0 + + + C_ERROR_INJECTION_TYPE_WACH + 0 + + + C_ERROR_INJECTION_TYPE_WDCH + 0 + + + C_ERROR_INJECTION_TYPE_WRCH + 0 + + + C_ERROR_INJECTION_TYPE_RACH + 0 + + + C_ERROR_INJECTION_TYPE_RDCH + 0 + + + C_ERROR_INJECTION_TYPE_AXIS + 0 + + + C_DIN_WIDTH_WACH + 1 + + + C_DIN_WIDTH_WDCH + 64 + + + C_DIN_WIDTH_WRCH + 2 + + + C_DIN_WIDTH_RACH + 32 + + + C_DIN_WIDTH_RDCH + 64 + + + C_DIN_WIDTH_AXIS + 1 + + + C_WR_DEPTH_WACH + 16 + + + C_WR_DEPTH_WDCH + 1024 + + + C_WR_DEPTH_WRCH + 16 + + + C_WR_DEPTH_RACH + 16 + + + C_WR_DEPTH_RDCH + 1024 + + + C_WR_DEPTH_AXIS + 1024 + + + C_WR_PNTR_WIDTH_WACH + 4 + + + C_WR_PNTR_WIDTH_WDCH + 10 + + + C_WR_PNTR_WIDTH_WRCH + 4 + + + C_WR_PNTR_WIDTH_RACH + 4 + + + C_WR_PNTR_WIDTH_RDCH + 10 + + + C_WR_PNTR_WIDTH_AXIS + 10 + + + C_HAS_DATA_COUNTS_WACH + 0 + + + C_HAS_DATA_COUNTS_WDCH + 0 + + + C_HAS_DATA_COUNTS_WRCH + 0 + + + C_HAS_DATA_COUNTS_RACH + 0 + + + C_HAS_DATA_COUNTS_RDCH + 0 + + + C_HAS_DATA_COUNTS_AXIS + 0 + + + C_HAS_PROG_FLAGS_WACH + 0 + + + C_HAS_PROG_FLAGS_WDCH + 0 + + + C_HAS_PROG_FLAGS_WRCH + 0 + + + C_HAS_PROG_FLAGS_RACH + 0 + + + C_HAS_PROG_FLAGS_RDCH + 0 + + + C_HAS_PROG_FLAGS_AXIS + 0 + + + C_PROG_FULL_TYPE_WACH + 0 + + + C_PROG_FULL_TYPE_WDCH + 0 + + + C_PROG_FULL_TYPE_WRCH + 0 + + + C_PROG_FULL_TYPE_RACH + 0 + + + C_PROG_FULL_TYPE_RDCH + 0 + + + C_PROG_FULL_TYPE_AXIS + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WRCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_08ae7940 + 19 + 19 + + + choice_list_165ed04b + 64 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_0721dec1 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Multiple_Programmable_Empty_Threshold_Constants + Single_Programmable_Empty_Threshold_Input_Port + Multiple_Programmable_Empty_Threshold_Input_Ports + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_541ed8d9 + Embedded_Reg + Fabric_Reg + Both + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_88535724 + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Multiple_Programmable_Full_Threshold_Constants + Single_Programmable_Full_Threshold_Input_Port + Multiple_Programmable_Full_Threshold_Input_Ports + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_ae1178b5 + Asynchronous_Reset + Synchronous_Reset + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + fifo_19x16_obuf_xcku + + + + true + + + + + + Fifo_Implementation + Common_Clock_Block_RAM + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + false + + + + true + + + + + + Input_Data_Width + 19 + + + + true + + + + + + Input_Depth + 16 + + + + true + + + + + + Output_Data_Width + 19 + + + + false + + + + + + Output_Depth + 16 + + + + false + + + + + + Enable_ECC + false + + + + true + + + + + + Use_Embedded_Registers + false + + + + true + + + + + + Reset_Pin + true + + + + true + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + true + + + + + + Full_Flags_Reset_Value + 0 + + + + false + + + + + + Use_Dout_Reset + true + + + + true + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + false + + + + + + Almost_Full_Flag + false + + + + true + + + + + + Almost_Empty_Flag + false + + + + true + + + + + + Valid_Flag + false + + + + true + + + + + + Valid_Sense + Active_High + + + + false + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + true + + + + true + + + + + + Data_Count_Width + 4 + + + + true + + + + + + Write_Data_Count + false + + + + false + + + + + + Write_Data_Count_Width + 4 + + + + false + + + + + + Read_Data_Count + false + + + + false + + + + + + Read_Data_Count_Width + 4 + + + + false + + + + + + Disable_Timing_Violations + false + + + + false + + + + + + Read_Clock_Frequency + 1 + + + + false + + + + + + Write_Clock_Frequency + 1 + + + + false + + + + + + Programmable_Full_Type + Single_Programmable_Full_Threshold_Input_Port + + + + true + + + + + + Full_Threshold_Assert_Value + 14 + + + + false + + + + + + Full_Threshold_Negate_Value + 13 + + + + false + + + + + + Programmable_Empty_Type + No_Programmable_Empty_Threshold + + + + true + + + + + + Empty_Threshold_Assert_Value + 2 + + + + false + + + + + + Empty_Threshold_Negate_Value + 3 + + + + false + + + + + + PROTOCOL + AXI4 + + + + false + + + + + + Clock_Type_AXI + Common_Clock + + + + true + + + + + + HAS_ACLKEN + false + + + + false + + + + + + Clock_Enable_Type + Slave_Interface_Clock_Enable + + + + false + + + + + + READ_WRITE_MODE + READ_WRITE + + + + true + + + + + + ID_WIDTH + 0 + + + + false + + + + + + ADDRESS_WIDTH + 32 + + + + false + + + + + + DATA_WIDTH + 64 + + + + false + + + + + + AWUSER_Width + 0 + + + + false + + + + + + WUSER_Width + 0 + + + + false + + + + + + BUSER_Width + 0 + + + + false + + + + + + ARUSER_Width + 0 + + + + false + + + + + + RUSER_Width + 0 + + + + false + + + + + + TDATA_NUM_BYTES + 1 + + + + true + + + + + + TID_WIDTH + 0 + + + + false + + + + + + TDEST_WIDTH + 0 + + + + false + + + + + + TUSER_WIDTH + 4 + + + + false + + + + + + Enable_TREADY + true + + + + false + + + + + + Enable_TLAST + false + + + + true + + + + + + HAS_TSTRB + false + + + + false + + + + + + TSTRB_WIDTH + 1 + + + + false + + + + + + HAS_TKEEP + false + + + + false + + + + + + TKEEP_WIDTH + 1 + + + + false + + + + + + wach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wach + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wach + false + + + + false + + + + + + Inject_Sbit_Error_wach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wach + false + + + + false + + + + + + Input_Depth_wach + 16 + + + + true + + + + + + Enable_Data_Counts_wach + false + + + + false + + + + + + Programmable_Full_Type_wach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wdch + false + + + + false + + + + + + Inject_Sbit_Error_wdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wdch + false + + + + false + + + + + + Input_Depth_wdch + 1024 + + + + true + + + + + + Enable_Data_Counts_wdch + false + + + + false + + + + + + Programmable_Full_Type_wdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wrch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wrch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wrch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wrch + false + + + + false + + + + + + Inject_Sbit_Error_wrch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wrch + false + + + + false + + + + + + Input_Depth_wrch + 16 + + + + true + + + + + + Enable_Data_Counts_wrch + false + + + + false + + + + + + Programmable_Full_Type_wrch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wrch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wrch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wrch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rach + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rach + false + + + + false + + + + + + Inject_Sbit_Error_rach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rach + false + + + + false + + + + + + Input_Depth_rach + 16 + + + + true + + + + + + Enable_Data_Counts_rach + false + + + + false + + + + + + Programmable_Full_Type_rach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rdch + false + + + + false + + + + + + Inject_Sbit_Error_rdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rdch + false + + + + false + + + + + + Input_Depth_rdch + 1024 + + + + true + + + + + + Enable_Data_Counts_rdch + false + + + + false + + + + + + Programmable_Full_Type_rdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + axis_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_axis + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_axis + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_axis + false + + + + false + + + + + + Inject_Sbit_Error_axis + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_axis + Double Bit Error Injection + false + + + + false + + + + + + Input_Depth_axis + 1024 + + + + true + + + + + + Enable_Data_Counts_axis + false + + + + false + + + + + + Programmable_Full_Type_axis + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_axis + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_axis + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_axis + Empty Threshold Assert Value + 1022 + + + + false + + + + + + Register_Slice_Mode_wach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wrch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_axis + Register Slice Options + Fully_Registered + + + + true + + + + + + Underflow_Flag_AXI + Underflow Flag + false + + + + false + + + + + + Underflow_Sense_AXI + Underflow (Read Error) + Active_High + + + + false + + + + + + Overflow_Flag_AXI + Overflow Flag + false + + + + false + + + + + + Overflow_Sense_AXI + Overflow (Write Error) + Active_High + + + + false + + + + + + Disable_Timing_Violations_AXI + false + + + + true + + + + + + Add_NGC_Constraint_AXI + false + + + + true + + + + + + Enable_Common_Underflow + false + + + + true + + + + + + Enable_Common_Overflow + false + + + + true + + + + + + enable_read_pointer_increment_by2 + false + + + + true + + + + + + Use_Embedded_Registers_axis + false + + + + false + + + + + + enable_low_latency + false + + + + false + + + + + + use_dout_register + false + + + + false + + + + + + Master_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Slave_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Output_Register_Type + Embedded_Reg + + + + false + + + + + + Enable_Safety_Circuit + false + + + + false + + + + + + Enable_ECC_Type + Hard_ECC + + + + false + + + + + + C_SELECT_XPM + 0 + + + + + FIFO Generator + + XPM_MEMORY + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + diff --git a/xilinx/xcku/fifo_36x512_oreg.vhd b/xilinx/xcku/fifo_36x512_oreg.vhd new file mode 100644 index 0000000..622b7d9 --- /dev/null +++ b/xilinx/xcku/fifo_36x512_oreg.vhd @@ -0,0 +1,58 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_36x512_oreg is + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(8 downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(9 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); +end entity fifo_36x512_oreg; + +architecture structural of fifo_36x512_oreg is + component fifo_36x512_oreg_xcku + port ( + clk : in std_logic; + srst : in std_logic; + din : in std_logic_vector(35 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + prog_full_thresh : in std_logic_vector(8 downto 0); + dout : out std_logic_vector(35 downto 0); + full : out std_logic; + empty : out std_logic; + data_count : out std_logic_vector(8 downto 0); + prog_full : out std_logic; + wr_rst_busy : out std_logic; + rd_rst_busy : out std_logic + ); + end component; +begin + fifo : fifo_36x512_oreg_xcku + port map ( + clk => Clock, + srst => Reset, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + prog_full_thresh => AmFullThresh, + dout => Q, + full => Full, + empty => Empty, + data_count => WCNT(8 downto 0), + prog_full => AlmostFull, + wr_rst_busy => open, + rd_rst_busy => open + ); + + -- TODO: Check impact of different count values + WCNT(9) <= '0'; +end architecture structural; diff --git a/xilinx/xcku/fifo_36x512_oreg_xcku/fifo_36x512_oreg_xcku.xci b/xilinx/xcku/fifo_36x512_oreg_xcku/fifo_36x512_oreg_xcku.xci new file mode 100644 index 0000000..9fef5f5 --- /dev/null +++ b/xilinx/xcku/fifo_36x512_oreg_xcku/fifo_36x512_oreg_xcku.xci @@ -0,0 +1,568 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_36x512_oreg_xcku + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 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+ + C_FULL_FLAGS_RST_VAL + 0 + + + C_HAS_ALMOST_EMPTY + 0 + + + C_HAS_ALMOST_FULL + 0 + + + C_HAS_BACKUP + 0 + + + C_HAS_DATA_COUNT + 1 + + + C_HAS_INT_CLK + 0 + + + C_HAS_MEMINIT_FILE + 0 + + + C_HAS_OVERFLOW + 0 + + + C_HAS_RD_DATA_COUNT + 0 + + + C_HAS_RD_RST + 0 + + + C_HAS_RST + 0 + + + C_HAS_SRST + 1 + + + C_HAS_UNDERFLOW + 0 + + + C_HAS_VALID + 0 + + + C_HAS_WR_ACK + 0 + + + C_HAS_WR_DATA_COUNT + 0 + + + C_HAS_WR_RST + 0 + + + C_IMPLEMENTATION_TYPE + 0 + + + C_INIT_WR_PNTR_VAL + 0 + + + C_MEMORY_TYPE + 1 + + + C_MIF_FILE_NAME + BlankString + + + C_OPTIMIZATION_MODE + 0 + + + C_OVERFLOW_LOW + 0 + + + C_PRELOAD_LATENCY + 2 + + + C_PRELOAD_REGS + 1 + + + C_PRIM_FIFO_TYPE + 512x36 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL + 2 + + + C_PROG_EMPTY_THRESH_NEGATE_VAL + 3 + + + C_PROG_EMPTY_TYPE + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL + 510 + + + C_PROG_FULL_THRESH_NEGATE_VAL + 509 + + + C_PROG_FULL_TYPE + 3 + + + C_RD_DATA_COUNT_WIDTH + 9 + + + C_RD_DEPTH + 512 + + + C_RD_FREQ + 1 + + + C_RD_PNTR_WIDTH + 9 + + + C_UNDERFLOW_LOW + 0 + + + C_USE_DOUT_RST + 1 + + + C_USE_ECC + 0 + + + C_USE_EMBEDDED_REG + 1 + + + C_USE_PIPELINE_REG + 0 + + + C_POWER_SAVING_MODE + 0 + + + C_USE_FIFO16_FLAGS + 0 + + + C_USE_FWFT_DATA_COUNT + 0 + + + C_VALID_LOW + 0 + + + C_WR_ACK_LOW + 0 + + + C_WR_DATA_COUNT_WIDTH + 9 + + + C_WR_DEPTH + 512 + + + C_WR_FREQ + 1 + + + C_WR_PNTR_WIDTH + 9 + + + C_WR_RESPONSE_LATENCY + 1 + + + C_MSGON_VAL + 1 + + + C_ENABLE_RST_SYNC + 1 + + + C_EN_SAFETY_CKT + 0 + + + C_ERROR_INJECTION_TYPE + 0 + + + C_SYNCHRONIZER_STAGE + 2 + + + C_INTERFACE_TYPE + 0 + + + C_AXI_TYPE + 1 + + + C_HAS_AXI_WR_CHANNEL + 1 + + + C_HAS_AXI_RD_CHANNEL + 1 + + + C_HAS_SLAVE_CE + 0 + + + C_HAS_MASTER_CE + 0 + + + C_ADD_NGC_CONSTRAINT + 0 + + + C_USE_COMMON_OVERFLOW + 0 + + + C_USE_COMMON_UNDERFLOW + 0 + + + C_USE_DEFAULT_SETTINGS + 0 + + + C_AXI_ID_WIDTH + 1 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 64 + + + C_AXI_LEN_WIDTH + 8 + + + C_AXI_LOCK_WIDTH + 1 + + + C_HAS_AXI_ID + 0 + + + C_HAS_AXI_AWUSER + 0 + + + C_HAS_AXI_WUSER + 0 + + + C_HAS_AXI_BUSER + 0 + + + C_HAS_AXI_ARUSER + 0 + + + C_HAS_AXI_RUSER + 0 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_HAS_AXIS_TDATA + 1 + + + C_HAS_AXIS_TID + 0 + + + C_HAS_AXIS_TDEST + 0 + + + C_HAS_AXIS_TUSER + 1 + + + C_HAS_AXIS_TREADY + 1 + + + C_HAS_AXIS_TLAST + 0 + + + C_HAS_AXIS_TSTRB + 0 + + + C_HAS_AXIS_TKEEP + 0 + + + C_AXIS_TDATA_WIDTH + 8 + + + C_AXIS_TID_WIDTH + 1 + + + C_AXIS_TDEST_WIDTH + 1 + + + C_AXIS_TUSER_WIDTH + 4 + + + C_AXIS_TSTRB_WIDTH + 1 + + + C_AXIS_TKEEP_WIDTH + 1 + + + C_WACH_TYPE + 0 + + + C_WDCH_TYPE + 0 + + + C_WRCH_TYPE + 0 + + + C_RACH_TYPE + 0 + + + C_RDCH_TYPE + 0 + + + C_AXIS_TYPE + 0 + + + C_IMPLEMENTATION_TYPE_WACH + 1 + + + C_IMPLEMENTATION_TYPE_WDCH + 1 + + + C_IMPLEMENTATION_TYPE_WRCH + 1 + + + C_IMPLEMENTATION_TYPE_RACH + 1 + + + C_IMPLEMENTATION_TYPE_RDCH + 1 + + + C_IMPLEMENTATION_TYPE_AXIS + 1 + + + C_APPLICATION_TYPE_WACH + 0 + + + C_APPLICATION_TYPE_WDCH + 0 + + + C_APPLICATION_TYPE_WRCH + 0 + + + C_APPLICATION_TYPE_RACH + 0 + + + C_APPLICATION_TYPE_RDCH + 0 + + + C_APPLICATION_TYPE_AXIS + 0 + + + C_PRIM_FIFO_TYPE_WACH + 512x36 + + + C_PRIM_FIFO_TYPE_WDCH + 512x72 + + + C_PRIM_FIFO_TYPE_WRCH + 512x36 + + + C_PRIM_FIFO_TYPE_RACH + 512x36 + + + C_PRIM_FIFO_TYPE_RDCH + 512x72 + + + C_PRIM_FIFO_TYPE_AXIS + 1kx18 + + + C_USE_ECC_WACH + 0 + + + C_USE_ECC_WDCH + 0 + + + C_USE_ECC_WRCH + 0 + + + C_USE_ECC_RACH + 0 + + + C_USE_ECC_RDCH + 0 + + + C_USE_ECC_AXIS + 0 + + + C_ERROR_INJECTION_TYPE_WACH + 0 + + + C_ERROR_INJECTION_TYPE_WDCH + 0 + + + C_ERROR_INJECTION_TYPE_WRCH + 0 + + + C_ERROR_INJECTION_TYPE_RACH + 0 + + + C_ERROR_INJECTION_TYPE_RDCH + 0 + + + C_ERROR_INJECTION_TYPE_AXIS + 0 + + + C_DIN_WIDTH_WACH + 1 + + + C_DIN_WIDTH_WDCH + 64 + + + C_DIN_WIDTH_WRCH + 2 + + + C_DIN_WIDTH_RACH + 32 + + + C_DIN_WIDTH_RDCH + 64 + + + C_DIN_WIDTH_AXIS + 1 + + + C_WR_DEPTH_WACH + 16 + + + C_WR_DEPTH_WDCH + 1024 + + + C_WR_DEPTH_WRCH + 16 + + + C_WR_DEPTH_RACH + 16 + + + C_WR_DEPTH_RDCH + 1024 + + + C_WR_DEPTH_AXIS + 1024 + + + C_WR_PNTR_WIDTH_WACH + 4 + + + C_WR_PNTR_WIDTH_WDCH + 10 + + + C_WR_PNTR_WIDTH_WRCH + 4 + + + C_WR_PNTR_WIDTH_RACH + 4 + + + C_WR_PNTR_WIDTH_RDCH + 10 + + + C_WR_PNTR_WIDTH_AXIS + 10 + + + C_HAS_DATA_COUNTS_WACH + 0 + + + C_HAS_DATA_COUNTS_WDCH + 0 + + + C_HAS_DATA_COUNTS_WRCH + 0 + + + C_HAS_DATA_COUNTS_RACH + 0 + + + C_HAS_DATA_COUNTS_RDCH + 0 + + + C_HAS_DATA_COUNTS_AXIS + 0 + + + C_HAS_PROG_FLAGS_WACH + 0 + + + C_HAS_PROG_FLAGS_WDCH + 0 + + + C_HAS_PROG_FLAGS_WRCH + 0 + + + C_HAS_PROG_FLAGS_RACH + 0 + + + C_HAS_PROG_FLAGS_RDCH + 0 + + + C_HAS_PROG_FLAGS_AXIS + 0 + + + C_PROG_FULL_TYPE_WACH + 0 + + + C_PROG_FULL_TYPE_WDCH + 0 + + + C_PROG_FULL_TYPE_WRCH + 0 + + + C_PROG_FULL_TYPE_RACH + 0 + + + C_PROG_FULL_TYPE_RDCH + 0 + + + C_PROG_FULL_TYPE_AXIS + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WRCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_165ed04b + 64 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_list_f3564c51 + 36 + 9 + 18 + 36 + 72 + 144 + 288 + + + choice_pairs_0721dec1 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Multiple_Programmable_Empty_Threshold_Constants + Single_Programmable_Empty_Threshold_Input_Port + Multiple_Programmable_Empty_Threshold_Input_Ports + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_541ed8d9 + Embedded_Reg + Fabric_Reg + Both + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_88535724 + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Multiple_Programmable_Full_Threshold_Constants + Single_Programmable_Full_Threshold_Input_Port + Multiple_Programmable_Full_Threshold_Input_Ports + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_ae1178b5 + Asynchronous_Reset + Synchronous_Reset + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + fifo_36x512_oreg_xcku + + + + true + + + + + + Fifo_Implementation + Common_Clock_Block_RAM + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + false + + + + true + + + + + + Input_Data_Width + 36 + + + + true + + + + + + Input_Depth + 512 + + + + true + + + + + + Output_Data_Width + 36 + + + + false + + + + + + Output_Depth + 512 + + + + false + + + + + + Enable_ECC + false + + + + true + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + true + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + true + + + + + + Full_Flags_Reset_Value + 0 + + + + false + + + + + + Use_Dout_Reset + true + + + + true + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + false + + + + + + Almost_Full_Flag + false + + + + true + + + + + + Almost_Empty_Flag + false + + + + true + + + + + + Valid_Flag + false + + + + true + + + + + + Valid_Sense + Active_High + + + + false + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + true + + + + true + + + + + + Data_Count_Width + 9 + + + + true + + + + + + Write_Data_Count + false + + + + false + + + + + + Write_Data_Count_Width + 9 + + + + false + + + + + + Read_Data_Count + false + + + + false + + + + + + Read_Data_Count_Width + 9 + + + + false + + + + + + Disable_Timing_Violations + false + + + + false + + + + + + Read_Clock_Frequency + 1 + + + + false + + + + + + Write_Clock_Frequency + 1 + + + + false + + + + + + Programmable_Full_Type + Single_Programmable_Full_Threshold_Input_Port + + + + true + + + + + + Full_Threshold_Assert_Value + 510 + + + + false + + + + + + Full_Threshold_Negate_Value + 509 + + + + false + + + + + + Programmable_Empty_Type + No_Programmable_Empty_Threshold + + + + true + + + + + + Empty_Threshold_Assert_Value + 2 + + + + false + + + + + + Empty_Threshold_Negate_Value + 3 + + + + false + + + + + + PROTOCOL + AXI4 + + + + false + + + + + + Clock_Type_AXI + Common_Clock + + + + true + + + + + + HAS_ACLKEN + false + + + + false + + + + + + Clock_Enable_Type + Slave_Interface_Clock_Enable + + + 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downto 0); + Q : out std_logic_vector(35 downto 0); + WCNT : out std_logic_vector(13 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); +end fifo_36x8k_oreg; + +architecture structural of fifo_36x8k_oreg is + component fifo_36x8k_oreg_xcku + port ( + clk : in std_logic; + srst : in std_logic; + din : in std_logic_vector(35 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + prog_full_thresh : in std_logic_vector(12 downto 0); + dout : out std_logic_vector(35 downto 0); + full : out std_logic; + empty : out std_logic; + data_count : out std_logic_vector(12 downto 0); + prog_full : out std_logic; + wr_rst_busy : out std_logic; + rd_rst_busy : out std_logic + ); + end component; +begin + fifo : fifo_36x8k_oreg_xcku + port map ( + clk => Clock, + srst => Reset, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + prog_full_thresh => AmFullThresh, + dout => Q, + full => Full, + empty => Empty, + data_count => WCNT(12 downto 0), + prog_full => AlmostFull, + wr_rst_busy => open, + rd_rst_busy => open + ); + + -- TODO: Check impact of different count values + WCNT(13) <= '0'; +end architecture structural; diff --git a/xilinx/xcku/fifo_36x8k_oreg_xcku/fifo_36x8k_oreg_xcku.xci b/xilinx/xcku/fifo_36x8k_oreg_xcku/fifo_36x8k_oreg_xcku.xci new file mode 100644 index 0000000..b272c86 --- /dev/null +++ b/xilinx/xcku/fifo_36x8k_oreg_xcku/fifo_36x8k_oreg_xcku.xci @@ -0,0 +1,569 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_36x8k_oreg_xcku + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 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512 + + + choice_list_165ed04b + 64 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_list_f3564c51 + 36 + 9 + 18 + 36 + 72 + 144 + 288 + + + choice_pairs_0721dec1 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Multiple_Programmable_Empty_Threshold_Constants + Single_Programmable_Empty_Threshold_Input_Port + Multiple_Programmable_Empty_Threshold_Input_Ports + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_541ed8d9 + Embedded_Reg + Fabric_Reg + Both + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_88535724 + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Multiple_Programmable_Full_Threshold_Constants + Single_Programmable_Full_Threshold_Input_Port + Multiple_Programmable_Full_Threshold_Input_Ports + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_ae1178b5 + Asynchronous_Reset + Synchronous_Reset + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + fifo_36x8k_oreg_xcku + + + + true + + + + + + Fifo_Implementation + Common_Clock_Block_RAM + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + false + + + + true + + + + + + Input_Data_Width + 36 + + + + true + + + + + + Input_Depth + 8192 + + + + true + + + + + + Output_Data_Width + 36 + + + + false + + + + + + Output_Depth + 8192 + + + + false + + + + + + Enable_ECC + false + + + + true + + + + + + Use_Embedded_Registers + true + + + + true + + + + + + Reset_Pin + true + + + + true + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + true + + + + + + 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false + + + + false + + + + + + Master_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Slave_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Output_Register_Type + Embedded_Reg + + + + true + + + + + + Enable_Safety_Circuit + false + + + + false + + + + + + Enable_ECC_Type + Hard_ECC + + + + false + + + + + + C_SELECT_XPM + 0 + + + + + FIFO Generator + + XPM_MEMORY + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + diff --git a/xilinx/xcku/fifo_sbuf.vhd b/xilinx/xcku/fifo_sbuf.vhd new file mode 100644 index 0000000..ce42804 --- /dev/null +++ b/xilinx/xcku/fifo_sbuf.vhd @@ -0,0 +1,49 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_sbuf is + port ( + Data : in std_logic_vector(18 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(18 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic + ); +end entity fifo_sbuf; + +architecture structural of fifo_sbuf is + component fifo_sbuf_xcku + port ( + clk : in std_logic; + srst : in std_logic; + din : in std_logic_vector(18 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(18 downto 0); + full : out std_logic; + empty : out std_logic; + prog_full : out std_logic; + wr_rst_busy : out std_logic; + rd_rst_busy : out std_logic + ); + end component; +begin + fifo : fifo_sbuf_xcku + PORT MAP ( + clk => Clock, + srst => Reset, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + dout => Q, + full => Full, + empty => Empty, + prog_full => AlmostFull, + wr_rst_busy => open, + rd_rst_busy => open + ); +end architecture structural; diff --git a/xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xci b/xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xci new file mode 100644 index 0000000..e49f937 --- /dev/null +++ b/xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xci @@ -0,0 +1,571 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_sbuf_xcku + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 1 + 0 + 4 + BlankString + 19 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 19 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintexu + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 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C_MEMORY_TYPE + 1 + + + C_MIF_FILE_NAME + BlankString + + + C_OPTIMIZATION_MODE + 0 + + + C_OVERFLOW_LOW + 0 + + + C_PRELOAD_LATENCY + 1 + + + C_PRELOAD_REGS + 0 + + + C_PRIM_FIFO_TYPE + 512x36 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL + 2 + + + C_PROG_EMPTY_THRESH_NEGATE_VAL + 3 + + + C_PROG_EMPTY_TYPE + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL + 5 + + + C_PROG_FULL_THRESH_NEGATE_VAL + 4 + + + C_PROG_FULL_TYPE + 1 + + + C_RD_DATA_COUNT_WIDTH + 4 + + + C_RD_DEPTH + 16 + + + C_RD_FREQ + 1 + + + C_RD_PNTR_WIDTH + 4 + + + C_UNDERFLOW_LOW + 0 + + + C_USE_DOUT_RST + 1 + + + C_USE_ECC + 0 + + + C_USE_EMBEDDED_REG + 0 + + + C_USE_PIPELINE_REG + 0 + + + C_POWER_SAVING_MODE + 0 + + + C_USE_FIFO16_FLAGS + 0 + + + C_USE_FWFT_DATA_COUNT + 0 + + + C_VALID_LOW + 0 + + + C_WR_ACK_LOW + 0 + + + C_WR_DATA_COUNT_WIDTH + 4 + + + C_WR_DEPTH + 16 + + + C_WR_FREQ + 1 + + + C_WR_PNTR_WIDTH + 4 + + + C_WR_RESPONSE_LATENCY + 1 + + + C_MSGON_VAL + 1 + + + C_ENABLE_RST_SYNC + 1 + + + C_EN_SAFETY_CKT + 0 + + + C_ERROR_INJECTION_TYPE + 0 + + + C_SYNCHRONIZER_STAGE + 2 + + + C_INTERFACE_TYPE + 0 + + + C_AXI_TYPE + 1 + + + C_HAS_AXI_WR_CHANNEL + 1 + + + C_HAS_AXI_RD_CHANNEL + 1 + + + C_HAS_SLAVE_CE + 0 + + + C_HAS_MASTER_CE + 0 + + + C_ADD_NGC_CONSTRAINT + 0 + + + C_USE_COMMON_OVERFLOW + 0 + + + C_USE_COMMON_UNDERFLOW + 0 + + + C_USE_DEFAULT_SETTINGS + 0 + + + C_AXI_ID_WIDTH + 1 + + + C_AXI_ADDR_WIDTH + 32 + + + C_AXI_DATA_WIDTH + 64 + + + C_AXI_LEN_WIDTH + 8 + + + C_AXI_LOCK_WIDTH + 1 + + + C_HAS_AXI_ID + 0 + + + C_HAS_AXI_AWUSER + 0 + + + C_HAS_AXI_WUSER + 0 + + + C_HAS_AXI_BUSER + 0 + + + C_HAS_AXI_ARUSER + 0 + + + C_HAS_AXI_RUSER + 0 + + + C_AXI_ARUSER_WIDTH + 1 + + + C_AXI_AWUSER_WIDTH + 1 + + + C_AXI_WUSER_WIDTH + 1 + + + C_AXI_BUSER_WIDTH + 1 + + + C_AXI_RUSER_WIDTH + 1 + + + C_HAS_AXIS_TDATA + 1 + + + C_HAS_AXIS_TID + 0 + + + C_HAS_AXIS_TDEST + 0 + + + C_HAS_AXIS_TUSER + 1 + + + C_HAS_AXIS_TREADY + 1 + + + C_HAS_AXIS_TLAST + 0 + + + C_HAS_AXIS_TSTRB + 0 + + + C_HAS_AXIS_TKEEP + 0 + + + C_AXIS_TDATA_WIDTH + 8 + + + C_AXIS_TID_WIDTH + 1 + + + C_AXIS_TDEST_WIDTH + 1 + + + C_AXIS_TUSER_WIDTH + 4 + + + C_AXIS_TSTRB_WIDTH + 1 + + + C_AXIS_TKEEP_WIDTH + 1 + + + C_WACH_TYPE + 0 + + + C_WDCH_TYPE + 0 + + + C_WRCH_TYPE + 0 + + + C_RACH_TYPE + 0 + + + C_RDCH_TYPE + 0 + + + C_AXIS_TYPE + 0 + + + C_IMPLEMENTATION_TYPE_WACH + 1 + + + C_IMPLEMENTATION_TYPE_WDCH + 1 + + + C_IMPLEMENTATION_TYPE_WRCH + 1 + + + C_IMPLEMENTATION_TYPE_RACH + 1 + + + C_IMPLEMENTATION_TYPE_RDCH + 1 + + + C_IMPLEMENTATION_TYPE_AXIS + 1 + + + C_APPLICATION_TYPE_WACH + 0 + + + C_APPLICATION_TYPE_WDCH + 0 + + + C_APPLICATION_TYPE_WRCH + 0 + + + C_APPLICATION_TYPE_RACH + 0 + + + C_APPLICATION_TYPE_RDCH + 0 + + + C_APPLICATION_TYPE_AXIS + 0 + + + C_PRIM_FIFO_TYPE_WACH + 512x36 + + + C_PRIM_FIFO_TYPE_WDCH + 512x72 + + + C_PRIM_FIFO_TYPE_WRCH + 512x36 + + + C_PRIM_FIFO_TYPE_RACH + 512x36 + + + C_PRIM_FIFO_TYPE_RDCH + 512x72 + + + C_PRIM_FIFO_TYPE_AXIS + 1kx18 + + + C_USE_ECC_WACH + 0 + + + C_USE_ECC_WDCH + 0 + + + C_USE_ECC_WRCH + 0 + + + C_USE_ECC_RACH + 0 + + + C_USE_ECC_RDCH + 0 + + + C_USE_ECC_AXIS + 0 + + + C_ERROR_INJECTION_TYPE_WACH + 0 + + + C_ERROR_INJECTION_TYPE_WDCH + 0 + + + C_ERROR_INJECTION_TYPE_WRCH + 0 + + + C_ERROR_INJECTION_TYPE_RACH + 0 + + + C_ERROR_INJECTION_TYPE_RDCH + 0 + + + C_ERROR_INJECTION_TYPE_AXIS + 0 + + + C_DIN_WIDTH_WACH + 1 + + + C_DIN_WIDTH_WDCH + 64 + + + C_DIN_WIDTH_WRCH + 2 + + + C_DIN_WIDTH_RACH + 32 + + + C_DIN_WIDTH_RDCH + 64 + + + C_DIN_WIDTH_AXIS + 1 + + + C_WR_DEPTH_WACH + 16 + + + C_WR_DEPTH_WDCH + 1024 + + + C_WR_DEPTH_WRCH + 16 + + + C_WR_DEPTH_RACH + 16 + + + C_WR_DEPTH_RDCH + 1024 + + + C_WR_DEPTH_AXIS + 1024 + + + C_WR_PNTR_WIDTH_WACH + 4 + + + C_WR_PNTR_WIDTH_WDCH + 10 + + + C_WR_PNTR_WIDTH_WRCH + 4 + + + C_WR_PNTR_WIDTH_RACH + 4 + + + C_WR_PNTR_WIDTH_RDCH + 10 + + + C_WR_PNTR_WIDTH_AXIS + 10 + + + C_HAS_DATA_COUNTS_WACH + 0 + + + C_HAS_DATA_COUNTS_WDCH + 0 + + + C_HAS_DATA_COUNTS_WRCH + 0 + + + C_HAS_DATA_COUNTS_RACH + 0 + + + C_HAS_DATA_COUNTS_RDCH + 0 + + + C_HAS_DATA_COUNTS_AXIS + 0 + + + C_HAS_PROG_FLAGS_WACH + 0 + + + C_HAS_PROG_FLAGS_WDCH + 0 + + + C_HAS_PROG_FLAGS_WRCH + 0 + + + C_HAS_PROG_FLAGS_RACH + 0 + + + C_HAS_PROG_FLAGS_RDCH + 0 + + + C_HAS_PROG_FLAGS_AXIS + 0 + + + C_PROG_FULL_TYPE_WACH + 0 + + + C_PROG_FULL_TYPE_WDCH + 0 + + + C_PROG_FULL_TYPE_WRCH + 0 + + + C_PROG_FULL_TYPE_RACH + 0 + + + C_PROG_FULL_TYPE_RDCH + 0 + + + C_PROG_FULL_TYPE_AXIS + 0 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_WRCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RACH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_RDCH + 1023 + + + C_PROG_FULL_THRESH_ASSERT_VAL_AXIS + 1023 + + + C_PROG_EMPTY_TYPE_WACH + 0 + + + C_PROG_EMPTY_TYPE_WDCH + 0 + + + C_PROG_EMPTY_TYPE_WRCH + 0 + + + C_PROG_EMPTY_TYPE_RACH + 0 + + + C_PROG_EMPTY_TYPE_RDCH + 0 + + + C_PROG_EMPTY_TYPE_AXIS + 0 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH + 1022 + + + C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS + 1022 + + + C_REG_SLICE_MODE_WACH + 0 + + + C_REG_SLICE_MODE_WDCH + 0 + + + C_REG_SLICE_MODE_WRCH + 0 + + + C_REG_SLICE_MODE_RACH + 0 + + + C_REG_SLICE_MODE_RDCH + 0 + + + C_REG_SLICE_MODE_AXIS + 0 + + + + + + choice_list_087d29fa + 0 + 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 + 512 + + + choice_list_08ae7940 + 19 + 19 + + + choice_list_165ed04b + 64 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_8af5a703 + 0 + 1 + + + choice_list_bf1143fa + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + 8192 + 16384 + 32768 + 65536 + 131072 + + + choice_pairs_0721dec1 + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Multiple_Programmable_Empty_Threshold_Constants + Single_Programmable_Empty_Threshold_Input_Port + Multiple_Programmable_Empty_Threshold_Input_Ports + + + choice_pairs_08e28d5f + Active_High + Active_Low + + + choice_pairs_0d7cd34d + Common_Clock_Builtin_FIFO + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + Common_Clock_Shift_Register + Independent_Clocks_Builtin_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + + + choice_pairs_3c123ec0 + Common_Clock_Block_RAM + Common_Clock_Distributed_RAM + + + choice_pairs_53eba4dc + Native + AXI_MEMORY_MAPPED + AXI_STREAM + + + choice_pairs_541ed8d9 + Embedded_Reg + Fabric_Reg + Both + + + choice_pairs_5548b404 + Common_Clock + Independent_Clock + + + choice_pairs_5f1451ad + Standard_FIFO + First_Word_Fall_Through + + + choice_pairs_619f3529 + AXI4 + AXI3 + AXI4_Lite + + + choice_pairs_8334cf20 + Data_FIFO + Packet_FIFO + Low_Latency_Data_FIFO + + + choice_pairs_88535724 + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Multiple_Programmable_Full_Threshold_Constants + Single_Programmable_Full_Threshold_Input_Port + Multiple_Programmable_Full_Threshold_Input_Ports + + + choice_pairs_9b232fe1 + Slave_Interface_Clock_Enable + Master_Interface_Clock_Enable + + + choice_pairs_a8c5818a + Fully_Registered + Light_Weight + + + choice_pairs_ae1178b5 + Asynchronous_Reset + Synchronous_Reset + + + choice_pairs_b3e9d19b + FIFO + Register_Slice + Pass_Through_Wire + + + choice_pairs_bec132cf + FIFO + Register_Slice + + + choice_pairs_c94a1851 + Hard_ECC + Soft_ECC + + + choice_pairs_ccb14e2b + READ_WRITE + READ_ONLY + WRITE_ONLY + + + choice_pairs_eb98f74b + No_Programmable_Empty_Threshold + Single_Programmable_Empty_Threshold_Constant + Single_Programmable_Empty_Threshold_Input_Port + + + choice_pairs_ec2b452f + No_Programmable_Full_Threshold + Single_Programmable_Full_Threshold_Constant + Single_Programmable_Full_Threshold_Input_Port + + + The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. + + + Component_Name + fifo_sbuf_xcku + + + + true + + + + + + Fifo_Implementation + Common_Clock_Block_RAM + + + + true + + + + + + synchronization_stages + 2 + + + + true + + + + + + synchronization_stages_axi + 2 + + + + true + + + + + + INTERFACE_TYPE + Native + + + + true + + + + + + Performance_Options + Standard_FIFO + + + + true + + + + + + asymmetric_port_width + false + + + + true + + + + + + Input_Data_Width + 19 + + + + true + + + + + + Input_Depth + 16 + + + + true + + + + + + Output_Data_Width + 19 + + + + false + + + + + + Output_Depth + 16 + + + + false + + + + + + Enable_ECC + false + + + + true + + + + + + Use_Embedded_Registers + false + + + + true + + + + + + Reset_Pin + true + + + + true + + + + + + Enable_Reset_Synchronization + true + + + + false + + + + + + Reset_Type + Synchronous_Reset + + + + true + + + + + + Full_Flags_Reset_Value + 0 + + + + false + + + + + + Use_Dout_Reset + true + + + + true + + + + + + Dout_Reset_Value + 0 + + + + true + + + + + + dynamic_power_saving + false + + + + false + + + + + + Almost_Full_Flag + false + + + + true + + + + + + Almost_Empty_Flag + false + + + + true + + + + + + Valid_Flag + false + + + + true + + + + + + Valid_Sense + Active_High + + + + false + + + + + + Underflow_Flag + false + + + + true + + + + + + Underflow_Sense + Active_High + + + + false + + + + + + Write_Acknowledge_Flag + false + + + + true + + + + + + Write_Acknowledge_Sense + Active_High + + + + false + + + + + + Overflow_Flag + false + + + + true + + + + + + Overflow_Sense + Active_High + + + + false + + + + + + Inject_Sbit_Error + false + + + + false + + + + + + Inject_Dbit_Error + false + + + + false + + + + + + ecc_pipeline_reg + false + + + + false + + + + + + Use_Extra_Logic + false + + + + false + + + + + + Data_Count + false + + + + true + + + + + + Data_Count_Width + 4 + + + + false + + + + + + Write_Data_Count + false + + + + false + + + + + + Write_Data_Count_Width + 4 + + + + false + + + + + + Read_Data_Count + false + + + + false + + + + + + Read_Data_Count_Width + 4 + + + + false + + + + + + Disable_Timing_Violations + false + + + + false + + + + + + Read_Clock_Frequency + 1 + + + + false + + + + + + Write_Clock_Frequency + 1 + + + + false + + + + + + Programmable_Full_Type + Single_Programmable_Full_Threshold_Constant + + + + true + + + + + + Full_Threshold_Assert_Value + 5 + + + + true + + + + + + Full_Threshold_Negate_Value + 4 + + + + false + + + + + + Programmable_Empty_Type + No_Programmable_Empty_Threshold + + + + true + + + + + + Empty_Threshold_Assert_Value + 2 + + + + false + + + + + + Empty_Threshold_Negate_Value + 3 + + + + false + + + + + + PROTOCOL + AXI4 + + + + false + + + + + + Clock_Type_AXI + Common_Clock + + + + true + + + + + + HAS_ACLKEN + false + + + + false + + + + + + Clock_Enable_Type + Slave_Interface_Clock_Enable + + + + false + + + + + + READ_WRITE_MODE + READ_WRITE + + + + true + + + + + + ID_WIDTH + 0 + + + + false + + + + + + ADDRESS_WIDTH + 32 + + + + false + + + + + + DATA_WIDTH + 64 + + + + false + + + + + + AWUSER_Width + 0 + + + + false + + + + + + WUSER_Width + 0 + + + + false + + + + + + BUSER_Width + 0 + + + + false + + + + + + ARUSER_Width + 0 + + + + false + + + + + + RUSER_Width + 0 + + + + false + + + + + + TDATA_NUM_BYTES + 1 + + + + true + + + + + + TID_WIDTH + 0 + + + + false + + + + + + TDEST_WIDTH + 0 + + + + false + + + + + + TUSER_WIDTH + 4 + + + + false + + + + + + Enable_TREADY + true + + + + false + + + + + + Enable_TLAST + false + + + + true + + + + + + HAS_TSTRB + false + + + + false + + + + + + TSTRB_WIDTH + 1 + + + + false + + + + + + HAS_TKEEP + false + + + + false + + + + + + TKEEP_WIDTH + 1 + + + + false + + + + + + wach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wach + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wach + false + + + + false + + + + + + Inject_Sbit_Error_wach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wach + false + + + + false + + + + + + Input_Depth_wach + 16 + + + + true + + + + + + Enable_Data_Counts_wach + false + + + + false + + + + + + Programmable_Full_Type_wach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wdch + false + + + + false + + + + + + Inject_Sbit_Error_wdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wdch + false + + + + false + + + + + + Input_Depth_wdch + 1024 + + + + true + + + + + + Enable_Data_Counts_wdch + false + + + + false + + + + + + Programmable_Full_Type_wdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + wrch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_wrch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_wrch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_wrch + false + + + + false + + + + + + Inject_Sbit_Error_wrch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_wrch + false + + + + false + + + + + + Input_Depth_wrch + 16 + + + + true + + + + + + Enable_Data_Counts_wrch + false + + + + false + + + + + + Programmable_Full_Type_wrch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_wrch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_wrch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_wrch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rach_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rach + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rach + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rach + false + + + + false + + + + + + Inject_Sbit_Error_rach + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rach + false + + + + false + + + + + + Input_Depth_rach + 16 + + + + true + + + + + + Enable_Data_Counts_rach + false + + + + false + + + + + + Programmable_Full_Type_rach + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rach + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rach + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rach + Empty Threshold Assert Value + 1022 + + + + false + + + + + + rdch_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_rdch + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_rdch + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_rdch + false + + + + false + + + + + + Inject_Sbit_Error_rdch + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_rdch + false + + + + false + + + + + + Input_Depth_rdch + 1024 + + + + true + + + + + + Enable_Data_Counts_rdch + false + + + + false + + + + + + Programmable_Full_Type_rdch + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_rdch + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_rdch + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_rdch + Empty Threshold Assert Value + 1022 + + + + false + + + + + + axis_type + Configuration Options + FIFO + + + + true + + + + + + FIFO_Implementation_axis + FIFO Implementation Type + Common_Clock_Block_RAM + + + + true + + + + + + FIFO_Application_Type_axis + FIFO Application Type + Data_FIFO + + + + false + + + + + + Enable_ECC_axis + false + + + + false + + + + + + Inject_Sbit_Error_axis + Single Bit Error Injection + false + + + + false + + + + + + Inject_Dbit_Error_axis + Double Bit Error Injection + false + + + + false + + + + + + Input_Depth_axis + 1024 + + + + true + + + + + + Enable_Data_Counts_axis + false + + + + false + + + + + + Programmable_Full_Type_axis + Deassert READY When + No_Programmable_Full_Threshold + + + + false + + + + + + Full_Threshold_Assert_Value_axis + Full Threshold Assert Value + 1023 + + + + false + + + + + + Programmable_Empty_Type_axis + Deassert VALID When + No_Programmable_Empty_Threshold + + + + false + + + + + + Empty_Threshold_Assert_Value_axis + Empty Threshold Assert Value + 1022 + + + + false + + + + + + Register_Slice_Mode_wach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_wrch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rach + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_rdch + Register Slice Options + Fully_Registered + + + + true + + + + + + Register_Slice_Mode_axis + Register Slice Options + Fully_Registered + + + + true + + + + + + Underflow_Flag_AXI + Underflow Flag + false + + + + false + + + + + + Underflow_Sense_AXI + Underflow (Read Error) + Active_High + + + + false + + + + + + Overflow_Flag_AXI + Overflow Flag + false + + + + false + + + + + + Overflow_Sense_AXI + Overflow (Write Error) + Active_High + + + + false + + + + + + Disable_Timing_Violations_AXI + false + + + + true + + + + + + Add_NGC_Constraint_AXI + false + + + + true + + + + + + Enable_Common_Underflow + false + + + + true + + + + + + Enable_Common_Overflow + false + + + + true + + + + + + enable_read_pointer_increment_by2 + false + + + + true + + + + + + Use_Embedded_Registers_axis + false + + + + false + + + + + + enable_low_latency + false + + + + false + + + + + + use_dout_register + false + + + + false + + + + + + Master_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Slave_interface_Clock_enable_memory_mapped + false + + + + false + + + + + + Output_Register_Type + Embedded_Reg + + + + false + + + + + + Enable_Safety_Circuit + false + + + + false + + + + + + Enable_ECC_Type + Hard_ECC + + + + false + + + + + + C_SELECT_XPM + 0 + + + + + FIFO Generator + + XPM_MEMORY + XPM_CDC + + 5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2019.2 + + + + + + + + diff --git a/xilinx/xcku/read_dna_address.vhd b/xilinx/xcku/read_dna_address.vhd new file mode 100644 index 0000000..cab8234 --- /dev/null +++ b/xilinx/xcku/read_dna_address.vhd @@ -0,0 +1,197 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +Library UNISIM; +use UNISIM.vcomponents.all; + + +entity read_dna_address is + generic (SIM_DNA_VALUE : std_logic_vector := X"80000000BEEF000000000002" ); + port ( + SYSCLK : in std_logic; + SYS_RESET : in std_logic; + SRL_O : out std_logic_vector(95 downto 0); + DNA_VALID : out std_logic; + DS_OUT : out std_logic_vector(15 downto 0); + DS_ADDR : out std_logic_vector(1 downto 0); + DS_WR : out std_logic +); +end read_dna_address; + +architecture Behavioral of read_dna_address is + +------------State Type Declaration---------------------------- +type CONTROLLER_STATE is (S_RESET,S_DNA,S_DONE); + +------------DNA Component Declaration------------------- + +COMPONENT DNA_PORTE2 is + generic ( + SIM_DNA_VALUE : std_logic_vector -- Specifies a sample 96-bit DNA value for simulation + ); + PORT ( + DOUT : out std_logic; --std_logic_vector(95 downto 0); -- 1-bit output: DNA output data + CLK : in std_logic; -- 1-bit input: Clock input + DIN : in std_logic; -- 1-bit input: User data input pin + READ : in std_logic; -- 1-bit input: Active-High load DNA, active-Low read input + SHIFT : in std_logic -- 1-bit input: Active-High shift enable input + ); +END COMPONENT; + + + +------------Signal Declarations---------------------------- +signal CURR_STATE, NEXT_STATE : CONTROLLER_STATE; --- State Signals +signal O: std_logic; --- DNA Output +signal CLK: std_logic; --- Clock signal +signal I: std_logic := '0'; --- DNA Input +signal RD: std_logic := '0'; --- DNA Read +signal SFT: std_logic := '0'; --- DNA Shift +signal RESET: std_logic := '1'; --- Reset Control + +signal SFT_cnt : integer range 0 to 94 := 0; --Shift assert count +signal COUNT : integer range 0 to 3 := 0; --- FSM Count +signal DONE_DNA : std_logic := '0'; + + +signal SLR_tmp : std_logic_vector(95 downto 0); + + + +begin + + DNA_VALID <= DONE_DNA; + SRL_O <= SLR_tmp; + CLK <= SYSCLK; + + + DNA_PORTE2_inst : DNA_PORTE2 + generic map ( + SIM_DNA_VALUE => X"5000_0000_BEEF_0000_1234_0001" -- Specifies a sample 96-bit DNA value for simulation + ) + port map ( + DOUT => O, -- 1-bit output: DNA output data + CLK => CLK, -- 1-bit input: Clock input + DIN => I, -- 1-bit input: User data input pin + READ => RD, -- 1-bit input: Active-High load DNA, active-Low read input + SHIFT => SFT -- 1-bit input: Active-High shift enable input + ); + +SYNC_PROC: process(SYSCLK) + begin + if(Rising_edge(SYSCLK)) then + if (RESET = '1') then + CURR_STATE <= S_RESET; + else + CURR_STATE <= NEXT_STATE; + end if; + end if; +end process SYNC_PROC; + +MAIN_PROC: process(CURR_STATE,SYS_RESET,DONE_DNA) +begin + case CURR_STATE is + when S_RESET => + if(SYS_RESET = '1') then + NEXT_STATE <= S_RESET;--S_DNA; + else + NEXT_STATE <= S_DNA;--S_RESET; + end if; + when S_DNA => + if(DONE_DNA = '1') then + NEXT_STATE <= S_DONE; + else + NEXT_STATE <= S_DNA; + end if; + when S_DONE => + NEXT_STATE <= S_DONE; + + when others=> + end case;--NEXT_STATE +end process MAIN_PROC; + + +-----Process to read DNA----------- + +PROC: process(SYSCLK) +begin + if(Rising_edge(SYSCLK)) then + case NEXT_STATE is + when S_RESET => + RD <= '0'; + SFT <= '0'; + RESET <= '0'; --de-assert reset (initially asserted) + when S_DNA => + case COUNT is + when 0 => + RD <= '1'; --Assert read Parallel loads output shift register + SFT <= '1'; + COUNT <= COUNT + 1; + when 1 => + RD <= '0'; -- Read should be deasserted after 1 CLK + SFT <= '1'; + COUNT <= COUNT + 1; + when 2 => + RD <= '0'; + SFT <= '1'; --Assert SHIFT, hold asserted for 96 CLKs + IF (SFT_cnt < 94) THEN + SFT_cnt <= SFT_cnt + 1; + COUNT <= 2; + ELSE + COUNT <= COUNT + 1; + SFT <= '0'; + END IF; + when 3 => + RD <= '0'; + SFT <= '0'; + DONE_DNA <= '1'; + COUNT <= COUNT + 1; + + when others=> + COUNT <= COUNT + 1; + end case; + + when S_DONE => + RD <= '0'; + SFT <= '0'; + + when others => + RESET <= '1'; --re-assert reset + end case; + end if; +end process PROC; + +---SIPO SRL---- + +THE_SIPO_SLR : process +begin + wait until rising_edge(SYSCLK); + if SFT = '1' then + SLR_tmp <= O & SLR_tmp (95 downto 1); + end if; +end process; + + +--small output (16 bit) for trbnet entity +THE_SMALL_DATA : process +begin + wait until rising_edge(SYSCLK); + DS_OUT <= SLR_tmp(95 downto 80); + DS_ADDR <= "00"; + DS_WR <= '0'; + if SFT_cnt = 15 then --DNA ADDRESS (15:00) + DS_ADDR <= "00"; + DS_WR <= '1'; + elsif SFT_cnt = 31 then --DNA ADDRESS (31:16) + DS_ADDR <= "01"; + DS_WR <= '1'; + elsif SFT_cnt = 47 then --DNA ADDRESS (47:32) + DS_ADDR <= "10"; + DS_WR <= '1'; + elsif SFT_cnt = 63 then --DNA ADDRESS (63:48) + DS_ADDR <= "11"; + DS_WR <= '1'; + end if; +end process; + + +end Behavioral; diff --git a/xilinx/xcku/trb_net16_fifo_arch.vhd b/xilinx/xcku/trb_net16_fifo_arch.vhd new file mode 100644 index 0000000..f65c9bd --- /dev/null +++ b/xilinx/xcku/trb_net16_fifo_arch.vhd @@ -0,0 +1,170 @@ +library ieee; + +use ieee.std_logic_1164.all; +USE ieee.std_logic_signed.ALL; +USE IEEE.numeric_std.ALL; +use work.trb_net_std.all; + +entity trb_net16_fifo is + generic ( + USE_VENDOR_CORES : integer range 0 to 1 := c_NO; + use_data_count : integer range 0 to 1 := c_NO; + DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(15 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(15 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); -- Input data + DATA_COUNT_OUT : out std_logic_vector(10 downto 0); + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic + ); +end entity; + +architecture arch_trb_net16_fifo of trb_net16_fifo is +component fifo_18x1k_xcku is + port ( + clk: in std_logic; + srst: in std_logic; + din: in std_logic_vector(17 downto 0); + wr_en: in std_logic; + rd_en: in std_logic; + dout: out std_logic_vector(17 downto 0); + full: out std_logic; + empty: out std_logic; + prog_full: out std_logic; + wr_rst_busy: out std_logic; + rd_rst_busy: out std_logic); +end component; + + +-- component lattice_ecp2m_fifo_18x16 is +-- port ( +-- Data: in std_logic_vector(17 downto 0); +-- WrClock: in std_logic; +-- RdClock: in std_logic; +-- WrEn: in std_logic; +-- RdEn: in std_logic; +-- Reset: in std_logic; +-- RPReset: in std_logic; +-- Q: out std_logic_vector(17 downto 0); +-- Empty: out std_logic; +-- Full: out std_logic); +-- end component; +-- +-- component lattice_ecp2m_fifo_18x32 is +-- port ( +-- Data: in std_logic_vector(17 downto 0); +-- WrClock: in std_logic; +-- RdClock: in std_logic; +-- WrEn: in std_logic; +-- RdEn: in std_logic; +-- Reset: in std_logic; +-- RPReset: in std_logic; +-- Q: out std_logic_vector(17 downto 0); +-- Empty: out std_logic; +-- Full: out std_logic); +-- end component; +-- +-- component lattice_ecp2m_fifo_18x64 is +-- port ( +-- Data: in std_logic_vector(17 downto 0); +-- WrClock: in std_logic; +-- RdClock: in std_logic; +-- WrEn: in std_logic; +-- RdEn: in std_logic; +-- Reset: in std_logic; +-- RPReset: in std_logic; +-- Q: out std_logic_vector(17 downto 0); +-- Empty: out std_logic; +-- Full: out std_logic); +-- end component; + + + signal din, dout : std_logic_vector(c_DATA_WIDTH +1 downto 0); + +begin + din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; + din(c_DATA_WIDTH + 1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; + DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 1 downto c_DATA_WIDTH); + DATA_COUNT_OUT <= (others => '0'); + +-- gen_FIFO6 : if DEPTH = 6 generate + fifo:fifo_18x1k_xcku + port map ( + clk => CLK, + srst => RESET, + din => din, + wr_en => WRITE_ENABLE_IN, + rd_en => READ_ENABLE_IN, + dout => dout, + full => FULL_OUT, + empty => EMPTY_OUT, + prog_full => open, + wr_rst_busy => open, + rd_rst_busy => open + ); +-- end generate; + + +-- gen_FIFO1 : if DEPTH = 1 generate +-- fifo:lattice_ecp2m_fifo_18x16 +-- port map ( +-- Data => din, +-- WrClock => CLK, +-- RdClock => CLK, +-- WrEn => WRITE_ENABLE_IN, +-- RdEn => READ_ENABLE_IN, +-- Reset => RESET, +-- RPReset => RESET, +-- Q => dout, +-- Empty => EMPTY_OUT, +-- Full => FULL_OUT +-- ); +-- end generate; +-- +-- gen_FIFO2 : if DEPTH = 2 generate +-- fifo:lattice_ecp2m_fifo_18x32 +-- port map ( +-- Data => din, +-- WrClock => CLK, +-- RdClock => CLK, +-- WrEn => WRITE_ENABLE_IN, +-- RdEn => READ_ENABLE_IN, +-- Reset => RESET, +-- RPReset => RESET, +-- Q => dout, +-- Empty => EMPTY_OUT, +-- Full => FULL_OUT +-- ); +-- end generate; +-- +-- +-- gen_FIFO3 : if DEPTH = 3 generate +-- fifo:lattice_ecp2m_fifo_18x64 +-- port map ( +-- Data => din, +-- WrClock => CLK, +-- RdClock => CLK, +-- WrEn => WRITE_ENABLE_IN, +-- RdEn => READ_ENABLE_IN, +-- Reset => RESET, +-- RPReset => RESET, +-- Q => dout, +-- Empty => EMPTY_OUT, +-- Full => FULL_OUT +-- ); +-- end generate; + + +end architecture; + + + diff --git a/xilinx/xcku/trb_net_xdna.vhd b/xilinx/xcku/trb_net_xdna.vhd new file mode 100644 index 0000000..79ba2ce --- /dev/null +++ b/xilinx/xcku/trb_net_xdna.vhd @@ -0,0 +1,59 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +entity trb_net_xdna is +port( + CLK : in std_logic; + RESET : in std_logic; + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector( 2 downto 0); + WRITE_OUT : out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + ID_OUT : out std_logic_vector(63 downto 0) + ); +end trb_net_xdna; + +architecture Behavioral of trb_net_xdna is + + signal address : std_logic_vector(95 downto 0); + signal dna_valid : std_logic; + signal ds_out : std_logic_vector(15 downto 0); + signal ds_addr : std_logic_vector( 1 downto 0); + signal ds_wr : std_logic; + +begin + + THE_XDNA : entity work.read_dna_address + port map( + SYSCLK => CLK, + SYS_RESET => RESET, + SRL_O => address, + DNA_VALID => dna_valid, + DS_OUT => ds_out, + DS_ADDR => ds_addr, + DS_WR => ds_wr + ); + + PROC_STORE_ID : process begin + wait until rising_edge(CLK); + if ds_wr = '1' then + case ds_addr is + when "00" => ID_OUT(15 downto 0) <= ds_out; + when "01" => ID_OUT(31 downto 16) <= ds_out; + when "10" => ID_OUT(47 downto 32) <= ds_out; + when "11" => ID_OUT(63 downto 48) <= ds_out; + when others => null; + end case; + end if; + end process; + + DATA_OUT <= ds_out; + ADDR_OUT <= '0'& ds_addr; + WRITE_OUT <= ds_wr; + TEMP_OUT <= (others => '0'); + +end Behavioral;