From: hadeshyp Date: Tue, 12 Jan 2010 10:28:21 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~351 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d03b651e499cc113ce54e71f13ad8c32c09561dc;p=trbnet.git *** empty log message *** --- diff --git a/lattice/ecp2m/pll_in100_out100.lpc b/lattice/ecp2m/pll_in100_out100.lpc index 3dcd8af..8b7f814 100644 --- a/lattice/ecp2m/pll_in100_out100.lpc +++ b/lattice/ecp2m/pll_in100_out100.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PLL -CoreRevision=5.0 +CoreRevision=5.1 ModuleName=pll_in100_out100 SourceFormat=Schematic/VHDL ParameterFileVersion=1.0 -Date=07/06/2009 -Time=13:48:26 +Date=12/18/2009 +Time=18:25:31 [Parameters] Verilog=0 diff --git a/lattice/ecp2m/pll_in100_out100.vhd b/lattice/ecp2m/pll_in100_out100.vhd index 58336fe..d292a70 100644 --- a/lattice/ecp2m/pll_in100_out100.vhd +++ b/lattice/ecp2m/pll_in100_out100.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) --- Module Version: 5.0 ---/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out100 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -noclkos -noclkok -norst -e +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 5.1 +--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out100 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -noclkos -noclkok -norst -e --- Mon Jul 6 13:48:27 2009 +-- Fri Dec 18 18:25:31 2009 library IEEE; use IEEE.std_logic_1164.all; @@ -16,8 +16,8 @@ entity pll_in100_out100 is CLK: in std_logic; CLKOP: out std_logic; LOCK: out std_logic); - attribute dont_touch : string; - attribute dont_touch of pll_in100_out100 : entity is "true"; + attribute dont_touch : boolean; + attribute dont_touch of pll_in100_out100 : entity is true; end pll_in100_out100; architecture Structure of pll_in100_out100 is diff --git a/media_interfaces/trb_net16_lsm_sfp.vhd b/media_interfaces/trb_net16_lsm_sfp.vhd index fed385a..6f26af8 100644 --- a/media_interfaces/trb_net16_lsm_sfp.vhd +++ b/media_interfaces/trb_net16_lsm_sfp.vhd @@ -76,7 +76,7 @@ signal rst_cctr : std_logic; signal buf_swap_bytes : std_logic; signal timing_ctr : std_logic_vector(28 downto 0); -signal cv_ctr : std_logic_vector(15 downto 0); +signal cv_ctr : std_logic_vector(3 downto 0); signal link_status_led : std_logic; @@ -164,8 +164,10 @@ begin end process STATE_MEM; -- state transitions -PROC_STATE_TRANSFORM: process( CURRENT_STATE, sfp_missing_in, sfp_los_in, timing_ctr, sd_alignment_in, cv_ctr, - sd_los_in, sd_link_ok_in, sd_txclk_bad_in, sd_rxclk_bad_in, sd_retry_in, rst_tctr ) +PROC_STATE_TRANSFORM: process( CURRENT_STATE, sfp_missing_in, sfp_los_in, + timing_ctr, sd_alignment_in, cv_ctr, + sd_txclk_bad_in, sd_rxclk_bad_in, sd_retry_in, + rst_tctr, reset, sd_cv_in ) begin NEXT_STATE <= QRST; -- avoid latches next_ce_tctr <= '0'; diff --git a/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd b/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd index b87fbde..f4d6f0e 100755 --- a/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd +++ b/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd @@ -740,16 +740,18 @@ begin empty_out => fifo_rx_empty(i) ); - fifo_rx_reset(i) <= reset_i(i) or not rx_allow_q(i); - fifo_rx_rd_en(i) <= '1'; + fifo_rx_reset(i) <= CLEAR or reset_i(i) or not rx_allow_q(i); + fifo_rx_rd_en(i) <= not fifo_rx_reset(i); --------------------------------------------------------------------- -- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path --------------------------------------------------------------------- - THE_BYTE_SWAP_PROC: process( SYSCLK ) + THE_BYTE_SWAP_PROC: process( CLEAR, SYSCLK ) begin - if( rising_edge(SYSCLK) ) then + if (CLEAR = '1') then + fifo_rx_wr_en(i) <= '0'; + elsif( rising_edge(SYSCLK) ) then last_rx(9*i+8 downto 9*i) <= rx_k(i*2+1) & rx_data(i*16+15 downto i*16+8); if( swap_bytes_qrx(i) = '0' ) then fifo_rx_din(i*18+17 downto i*18) <= rx_k(i*2+1) & rx_k(i*2) & rx_data(i*16+15 downto i*16+8) @@ -856,10 +858,10 @@ begin empty_out => fifo_tx_empty(i) ); - fifo_tx_reset(i) <= reset_i(i) or not tx_allow_q(i); + fifo_tx_reset(i) <= CLEAR or reset_i(i) or not tx_allow_q(i); fifo_tx_din(i*18+17 downto i*18) <= med_packet_num_in(i*3+2) & med_packet_num_in(i*3+0)& med_data_in(i*16+15 downto i*16); - fifo_tx_wr_en(i) <= med_dataready_in(i) and tx_allow(i); - fifo_tx_rd_en(i) <= '1'; + fifo_tx_wr_en(i) <= not CLEAR and med_dataready_in(i) and tx_allow(i); + fifo_tx_rd_en(i) <= not fifo_tx_reset(i); diff --git a/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd index 5adfe15..dcc04d4 100755 --- a/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd +++ b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd @@ -14,7 +14,8 @@ use work.trb_net_components.all; entity trb_net16_med_ecp_sfp_gbe is generic( SERDES_NUM : integer range 0 to 3 := 2; - EXT_CLOCK : integer range 0 to 1 := c_NO + EXT_CLOCK : integer range 0 to 1 := c_NO; + USE_200_MHZ: integer range 0 to 1 := c_NO ); port( CLK : in std_logic; -- SerDes clock @@ -60,7 +61,7 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp_gbe is attribute syn_sharing : string; attribute syn_sharing of med_ecp_sfp : architecture is "off"; - COMPONENT serdes_gbe_0_extclock + component serdes_gbe_0_extclock PORT( refclkp : IN std_logic; refclkn : IN std_logic; @@ -103,7 +104,53 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp_gbe is refck2core : OUT std_logic; ffs_plol : OUT std_logic ); - END COMPONENT; + end component; + + + component serdes_gbe_0_200_ext + PORT( + refclkp : IN std_logic; + refclkn : IN std_logic; + hdinp0 : IN std_logic; + hdinn0 : IN std_logic; + ff_rxiclk_ch0 : IN std_logic; + ff_txiclk_ch0 : IN std_logic; + ff_ebrd_clk_0 : IN std_logic; + ff_txdata_ch0 : IN std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch0 : IN std_logic_vector(1 downto 0); + ff_xmit_ch0 : IN std_logic_vector(1 downto 0); + ff_correct_disp_ch0 : IN std_logic_vector(1 downto 0); + ffc_rrst_ch0 : IN std_logic; + ffc_lane_tx_rst_ch0 : IN std_logic; + ffc_lane_rx_rst_ch0 : IN std_logic; + ffc_txpwdnb_ch0 : IN std_logic; + ffc_rxpwdnb_ch0 : IN std_logic; + ffc_macro_rst : IN std_logic; + ffc_quad_rst : IN std_logic; + ffc_trst : IN std_logic; + hdoutp0 : OUT std_logic; + hdoutn0 : OUT std_logic; + ff_rxdata_ch0 : OUT std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch0 : OUT std_logic_vector(1 downto 0); + ff_rxfullclk_ch0 : OUT std_logic; + ff_rxhalfclk_ch0 : OUT std_logic; + ff_disp_err_ch0 : OUT std_logic_vector(1 downto 0); + ff_cv_ch0 : OUT std_logic_vector(1 downto 0); + ff_rx_even_ch0 : OUT std_logic_vector(1 downto 0); + ffs_rlos_lo_ch0 : OUT std_logic; + ffs_ls_sync_status_ch0 : OUT std_logic; + ffs_cc_underrun_ch0 : OUT std_logic; + ffs_cc_overrun_ch0 : OUT std_logic; + ffs_txfbfifo_error_ch0 : OUT std_logic; + ffs_rxfbfifo_error_ch0 : OUT std_logic; + ffs_rlol_ch0 : OUT std_logic; + oob_out_ch0 : OUT std_logic; + ff_txfullclk : OUT std_logic; + ff_txhalfclk : OUT std_logic; + refck2core : OUT std_logic; + ffs_plol : OUT std_logic + ); + end component; component serdes_gbe_1 port( @@ -195,6 +242,51 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp_gbe is ); end component; + component serdes_gbe_0_200 + port( + core_txrefclk : IN std_logic; + core_rxrefclk : IN std_logic; + hdinp0 : IN std_logic; + hdinn0 : IN std_logic; + ff_rxiclk_ch0 : IN std_logic; + ff_txiclk_ch0 : IN std_logic; + ff_ebrd_clk_0 : IN std_logic; + ff_txdata_ch0 : IN std_logic_vector(15 downto 0); + ff_tx_k_cntrl_ch0 : IN std_logic_vector(1 downto 0); + ff_xmit_ch0 : IN std_logic_vector(1 downto 0); + ff_correct_disp_ch0 : IN std_logic_vector(1 downto 0); + ffc_rrst_ch0 : IN std_logic; + ffc_lane_tx_rst_ch0 : IN std_logic; + ffc_lane_rx_rst_ch0 : IN std_logic; + ffc_txpwdnb_ch0 : IN std_logic; + ffc_rxpwdnb_ch0 : IN std_logic; + ffc_macro_rst : IN std_logic; + ffc_quad_rst : IN std_logic; + ffc_trst : IN std_logic; + hdoutp0 : OUT std_logic; + hdoutn0 : OUT std_logic; + ff_rxdata_ch0 : OUT std_logic_vector(15 downto 0); + ff_rx_k_cntrl_ch0 : OUT std_logic_vector(1 downto 0); + ff_rxfullclk_ch0 : OUT std_logic; + ff_rxhalfclk_ch0 : OUT std_logic; + ff_disp_err_ch0 : OUT std_logic_vector(1 downto 0); + ff_cv_ch0 : OUT std_logic_vector(1 downto 0); + ff_rx_even_ch0 : OUT std_logic_vector(1 downto 0); + ffs_rlos_lo_ch0 : OUT std_logic; + ffs_ls_sync_status_ch0 : OUT std_logic; + ffs_cc_underrun_ch0 : OUT std_logic; + ffs_cc_overrun_ch0 : OUT std_logic; + ffs_txfbfifo_error_ch0 : OUT std_logic; + ffs_rxfbfifo_error_ch0 : OUT std_logic; + ffs_rlol_ch0 : OUT std_logic; + oob_out_ch0 : OUT std_logic; + ff_txfullclk : OUT std_logic; + ff_txhalfclk : OUT std_logic; + refck2core : OUT std_logic; + ffs_plol : OUT std_logic + ); + end component; + component serdes_gbe_2 port( core_txrefclk : IN std_logic; @@ -507,7 +599,7 @@ refclk2core_out <= refck2core; -- Instantiation of serdes module - gen_serdes_0_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES generate + gen_serdes_0_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES and USE_200_MHZ = c_NO generate THE_SERDES: serdes_gbe_0_extclock port map( refclkp => SD_REFCLK_P_IN, @@ -553,7 +645,53 @@ refclk2core_out <= refck2core; ); end generate; - gen_serdes_0 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO generate + gen_serdes_0_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES and USE_200_MHZ = c_YES generate + THE_SERDES: serdes_gbe_0_200_ext + port map( + refclkp => SD_REFCLK_P_IN, + refclkn => SD_REFCLK_N_IN, + hdinp0 => SD_RXD_P_IN, + hdinn0 => SD_RXD_N_IN, + ff_rxiclk_ch0 => sysclk, + ff_txiclk_ch0 => sysclk, + ff_ebrd_clk_0 => ff_txfullclk, + ff_txdata_ch0 => tx_data, + ff_tx_k_cntrl_ch0 => tx_k, + ff_xmit_ch0 => "00", -- UNKNOWN + ff_correct_disp_ch0 => tx_correct, + ffc_rrst_ch0 => '0', + ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst, + ffc_lane_rx_rst_ch0 => ffc_lane_tx_rst, + ffc_txpwdnb_ch0 => '1', + ffc_rxpwdnb_ch0 => '1', + ffc_macro_rst => '0', + ffc_quad_rst => ffc_quad_rst, + ffc_trst => '0', + hdoutp0 => sd_txd_p_out, + hdoutn0 => sd_txd_n_out, + ff_rxdata_ch0 => comb_rx_data, + ff_rx_k_cntrl_ch0 => comb_rx_k, + ff_rxfullclk_ch0 => open, + ff_rxhalfclk_ch0 => open, + ff_disp_err_ch0 => open, + ff_cv_ch0 => link_error(7 downto 6), + ff_rx_even_ch0 => open, + ffs_rlos_lo_ch0 => link_error(8), + ffs_ls_sync_status_ch0 => link_ok(0), + ffs_cc_underrun_ch0 => link_error(0), + ffs_cc_overrun_ch0 => link_error(1), + ffs_txfbfifo_error_ch0 => link_error(2), + ffs_rxfbfifo_error_ch0 => link_error(3), + ffs_rlol_ch0 => link_error(4), + oob_out_ch0 => open, + ff_txfullclk => ff_txfullclk, + ff_txhalfclk => ff_txhalfclk, + refck2core => refck2core, + ffs_plol => link_error(5) + ); + end generate; + + gen_serdes_0 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_NO generate THE_SERDES: serdes_gbe_0 port map( core_txrefclk => clk, @@ -599,6 +737,52 @@ refclk2core_out <= refck2core; ); end generate; + gen_serdes_0 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES generate + THE_SERDES: serdes_gbe_0_200 + port map( + core_txrefclk => clk, + core_rxrefclk => clk, + hdinp0 => sd_rxd_p_in, + hdinn0 => sd_rxd_n_in, + ff_rxiclk_ch0 => sysclk, + ff_txiclk_ch0 => sysclk, + ff_ebrd_clk_0 => ff_txfullclk, + ff_txdata_ch0 => tx_data, + ff_tx_k_cntrl_ch0 => tx_k, + ff_xmit_ch0 => "00", -- UNKNOWN + ff_correct_disp_ch0 => tx_correct, + ffc_rrst_ch0 => '0', + ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst, + ffc_lane_rx_rst_ch0 => ffc_lane_tx_rst, + ffc_txpwdnb_ch0 => '1', + ffc_rxpwdnb_ch0 => '1', + ffc_macro_rst => '0', + ffc_quad_rst => ffc_quad_rst, + ffc_trst => '0', + hdoutp0 => sd_txd_p_out, + hdoutn0 => sd_txd_n_out, + ff_rxdata_ch0 => comb_rx_data, + ff_rx_k_cntrl_ch0 => comb_rx_k, + ff_rxfullclk_ch0 => open, + ff_rxhalfclk_ch0 => open, + ff_disp_err_ch0 => open, + ff_cv_ch0 => link_error(7 downto 6), + ff_rx_even_ch0 => open, + ffs_rlos_lo_ch0 => link_error(8), + ffs_ls_sync_status_ch0 => link_ok(0), + ffs_cc_underrun_ch0 => link_error(0), + ffs_cc_overrun_ch0 => link_error(1), + ffs_txfbfifo_error_ch0 => link_error(2), + ffs_rxfbfifo_error_ch0 => link_error(3), + ffs_rlol_ch0 => link_error(4), + oob_out_ch0 => open, + ff_txfullclk => ff_txfullclk, + ff_txhalfclk => ff_txhalfclk, + refck2core => refck2core, + ffs_plol => link_error(5) + ); + end generate; + gen_serdes_1 : if SERDES_NUM = 1 generate THE_SERDES: serdes_gbe_1 port map( diff --git a/trb_net16_addresses.vhd b/trb_net16_addresses.vhd index 1d5142a..a2c8043 100644 --- a/trb_net16_addresses.vhd +++ b/trb_net16_addresses.vhd @@ -90,7 +90,7 @@ signal next_state, state : std_logic_vector(c_NUM_WIDTH-1 downto 0); type sending_state_t is (sending_idle, send_uid_1, send_uid_2, send_ack_address); signal sending_state : sending_state_t; signal sending_state_bits : std_logic_vector(1 downto 0); -signal buf_ADDRESS_OUT : std_logic_vector(15 downto 0); +signal buf_ADDRESS_OUT : std_logic_vector(15 downto 0) := INIT_ADDRESS; signal delayed_buf_API_SEND_OUT : std_logic; begin @@ -102,7 +102,7 @@ begin begin if rising_edge(CLK) then if RESET = '1' then - buf_ADDRESS_OUT <= INIT_ADDRESS; +-- buf_ADDRESS_OUT <= INIT_ADDRESS; ram_read_addr1 <= (others => '0'); matching_counter <= (others => '0'); recv_set_address <= '0'; diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 8bd781b..24457aa 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -727,8 +727,8 @@ begin begin if rising_edge(CLK) then if reset_no_link = '1' then - int_trigger_num <= (others => '1'); - elsif TRIGGER_MONITOR_IN = '1' then + int_trigger_num <= (others => '0'); + elsif LVL1_TRG_RECEIVED_OUT_falling = '1' then int_trigger_num <= int_trigger_num + 1; elsif buf_COMMON_CTRL_REG_STROBE(1) = '1' then int_trigger_num <= buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32); @@ -761,7 +761,8 @@ begin if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then got_timing_trigger <= '0'; - elsif TRIGGER_MONITOR_IN = '1' then + elsif TRIGGER_MONITOR_IN = '1' or + (LVL1_TRG_RECEIVED_OUT_rising = '1' and LVL1_TRG_TYPE_OUT >= x"8" and LVL1_TRG_INFORMATION_OUT(7) = '1') then got_timing_trigger <= '1'; end if; end if; diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 03af498..06d0ff5 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -180,13 +180,15 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal HC_READ_IN : std_logic; signal HC_RUN_OUT : std_logic; signal HC_SEQNR_OUT : std_logic_vector (7 downto 0); - signal HC_STAT_REGS : std_logic_vector (2**4*32-1 downto 0); - signal STAT_REG_STROBE : std_logic_vector (2**4-1 downto 0); + signal HC_STAT_REGS : std_logic_vector (64*32-1 downto 0); + signal HUB_SCTRL_ERROR : std_logic_vector (MII_NUMBER-1 downto 0); + signal STAT_REG_STROBE : std_logic_vector (2**6-1 downto 0); + signal reg_STROBES : std_logic_vector (2**6-1 downto 0); signal CTRL_REG_STROBE : std_logic_vector (2**4-1 downto 0); signal HC_CTRL_REGS : std_logic_vector (2**4*32-1 downto 0); signal HC_COMMON_STAT_REGS : std_logic_vector(std_COMSTATREG*32-1 downto 0); signal HC_COMMON_CTRL_REGS : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal buf_HC_STAT_REGS : std_logic_vector (2**4*32-1 downto 0); + signal buf_HC_STAT_REGS : std_logic_vector (64*32-1 downto 0); signal HC_STAT_ack_waiting : std_logic_vector(127 downto 0) := (others => '0'); signal HUB_CTRL_LOCAL_NETWORK_RESET : std_logic_vector(MII_NUMBER-1 downto 0); @@ -197,18 +199,19 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal HUB_CTRL_TIMEOUT_TIME : std_logic_vector (31 downto 0); signal HUB_ADDRESS : std_logic_vector (15 downto 0); signal HUBLOGIC_IPU_STAT_DEBUG : std_logic_vector (31 downto 0); + signal HUB_ERROR_BITS : std_logic_vector (16*4*32-1 downto 0); + signal buf_HUB_ERROR_BITS : std_logic_vector ((16*2**(c_MUX_WIDTH-1))*32-1 downto 0); - signal IOBUF_STAT_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0); - signal IOBUF_IBUF_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0); - signal IOBUF_CTRL_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0); - signal IOBUF_STAT_INIT_OBUF_DEBUG : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0); - signal IOBUF_STAT_REPLY_OBUF_DEBUG : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0); + signal IOBUF_STAT_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0); + signal IOBUF_IBUF_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0); + signal IOBUF_CTRL_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0); + signal IOBUF_STAT_INIT_OBUF_DEBUG : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0); + signal IOBUF_STAT_REPLY_OBUF_DEBUG : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0); signal resync : std_logic_vector(MII_NUMBER-1 downto 0); signal reset_i : std_logic; signal reset_i_mux_io : std_logic_vector(MII_NUMBER-1 downto 0); - attribute syn_keep : boolean; - attribute syn_keep of reset_i : signal is true; + signal combined_resync : std_logic; signal IDRAM_DATA_IN, IDRAM_DATA_OUT : std_logic_vector(15 downto 0); @@ -220,7 +223,7 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal local_time : std_logic_vector(7 downto 0); signal timer_ms_tick : std_logic; signal timer_us_tick : std_logic; - signal stat_ipu_fsm : std_logic_vector(15 downto 0); + signal stat_ipu_fsm : std_logic_vector(31 downto 0); signal DAT_ADDR_OUT : std_logic_vector(16-1 downto 0); signal DAT_READ_ENABLE_OUT : std_logic; @@ -244,8 +247,14 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is attribute syn_keep of m_DATA_IN : signal is true; attribute syn_preserve of m_DATAREADY_IN : signal is true; attribute syn_keep of m_DATAREADY_IN : signal is true; + attribute syn_preserve of m_PACKET_NUM_IN : signal is true; + attribute syn_keep of m_PACKET_NUM_IN : signal is true; + attribute syn_preserve of m_PACKET_NUM_OUT : signal is true; + attribute syn_keep of m_PACKET_NUM_OUT : signal is true; + attribute syn_keep of reset_i : signal is true; - + attribute syn_hier : string; + attribute syn_hier of trb_net16_hub_base_arch : architecture is "firm"; begin @@ -726,7 +735,8 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; STAT_locked => HUB_locked(i), STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32), STAT_TIMEOUT => STAT_TIMEOUT((i+1)*32-1 downto i*32), - STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32), + STAT_ERRORBITS => HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32), + STAT_ALL_ERRORBITS => buf_HUB_ERROR_BITS((i+1)*32*16-1 downto i*32*16), CTRL_TIMEOUT_TIME => HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4), CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32), CTRL_TIMER_TICK(0) => timer_us_tick, @@ -764,7 +774,8 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; STAT_locked => HUB_locked(i), STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32), STAT_TIMEOUT => STAT_TIMEOUT((i+1)*32-1 downto i*32), - STAT_ERRORBITS => open, --HUB_STAT_ERRORBITS(i+1)*32-1 downto i*32), + STAT_ERRORBITS => HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32), + STAT_ALL_ERRORBITS => buf_HUB_ERROR_BITS((i+1)*32*16-1 downto i*32*16), STAT_FSM => stat_ipu_fsm, CTRL_TIMEOUT_TIME => HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4), CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32), @@ -786,6 +797,7 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; HUB_INIT_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0'); HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0'); HUB_INIT_READ_IN(next_point_num-1 downto first_point_num) <= (others => '0'); + buf_HUB_ERROR_BITS((i+1)*32-1 downto i*32) <= (others => '0'); end generate; end generate; end generate; @@ -796,11 +808,11 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; --------------------------------------------------------------------- hub_control : trb_net16_regIO generic map( - NUM_STAT_REGS => 4, + NUM_STAT_REGS => 6, NUM_CTRL_REGS => 4, INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" & x"00000000_00000000_00000000_00000000" & - x"00000000_00000000_00009999_00000000" & + x"00000000_00000000_0000307F_00000000" & x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF", USED_CTRL_REGS => (others => '1'), USED_CTRL_BITMASK => (others => '1'), @@ -978,38 +990,59 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); --Status Registers buf_HC_STAT_REGS(4*32-1 downto 0) <= buf_STAT_POINTS_locked; - buf_HC_STAT_REGS(5*32-1 downto 4*32) <= HUB_MED_CONNECTED; - buf_HC_STAT_REGS(5*32+31 downto 5*32+17) <= (others => '0'); - buf_HC_STAT_REGS(6*32+31 downto 6*32+17) <= (others => '0'); - buf_HC_STAT_REGS(16*32-1 downto 12*32) <= HC_STAT_ack_waiting; + buf_HC_STAT_REGS(4*32+MII_NUMBER-1 downto 4*32) <= HUB_MED_CONNECTED(MII_NUMBER-1 downto 0); + buf_HC_STAT_REGS(5*32-1 downto 4*32+MII_NUMBER) <= (others => '0'); + buf_HC_STAT_REGS(6*32-1 downto 5*32+17) <= (others => '0'); + buf_HC_STAT_REGS(7*32-1 downto 6*32+17) <= (others => '0'); + buf_HC_STAT_REGS(8*32-1 downto 7*32) <= stat_ipu_fsm; + buf_HC_STAT_REGS(16*32-1 downto 12*32) <= HC_STAT_ack_waiting; + buf_HC_STAT_REGS(32*32-1 downto 16*32) <= HUB_ERROR_BITS(16*32-1 downto 0); + buf_HC_STAT_REGS(36*32-1 downto 32*32) <= HUB_STAT_ERRORBITS; loop_links : for i in 0 to 16 generate buf_HC_STAT_REGS(5*32+i) <= '1' when i < MII_NUMBER and MII_IS_UPLINK(i) = 1 else '0'; buf_HC_STAT_REGS(6*32+i) <= '1' when i < MII_NUMBER and MII_IS_DOWNLINK(i) = 1 else '0'; end generate; + loop_links_2 : for i in 0 to 15 generate + HUB_ERROR_BITS(i*32+7 downto i*32+0) <= buf_HUB_ERROR_BITS(i*32+7 downto i*32+0); + HUB_ERROR_BITS(i*32+15 downto i*32+8) <= buf_HUB_ERROR_BITS(i*32+23 downto i*32+16); + HUB_ERROR_BITS(i*32+23 downto i*32+16) <= buf_HUB_ERROR_BITS(i*32+32*16+7 downto i*32+32*16+0); + HUB_ERROR_BITS(i*32+31 downto i*32+24) <= buf_HUB_ERROR_BITS(i*32+32*16+23 downto i*32+32*16+16); + end generate; + PROC_TIMEOUT : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or STAT_REG_STROBE(8) = '1' then - buf_HC_STAT_REGS(8*32+31 downto 8*32) <= (others => '0'); + reg_STROBES <= STAT_REG_STROBE; + if reg_STROBES(8) = '1' then + HC_STAT_REGS(8*32+31 downto 8*32) <= (others => '0'); + else + HC_STAT_REGS(8*32+31 downto 8*32) <= STAT_TIMEOUT(0*32+31 downto 0*32) or buf_HC_STAT_REGS(8*32+31 downto 8*32); + end if; + if reg_STROBES(9) = '1' then + HC_STAT_REGS(9*32+31 downto 9*32) <= (others => '0'); else - buf_HC_STAT_REGS(8*32+31 downto 8*32) <= STAT_TIMEOUT(0*32+31 downto 0*32) or buf_HC_STAT_REGS(8*32+31 downto 8*32); + HC_STAT_REGS(9*32+31 downto 9*32) <= STAT_TIMEOUT(1*32+31 downto 1*32) or buf_HC_STAT_REGS(9*32+31 downto 9*32); end if; - if RESET = '1' or STAT_REG_STROBE(9) = '1' then - buf_HC_STAT_REGS(9*32+31 downto 9*32) <= (others => '0'); + if reg_STROBES(10) = '1' then + HC_STAT_REGS(10*32+31 downto 10*32) <= (others => '0'); else - buf_HC_STAT_REGS(9*32+31 downto 9*32) <= STAT_TIMEOUT(1*32+31 downto 1*32) or buf_HC_STAT_REGS(9*32+31 downto 9*32); + HC_STAT_REGS(10*32+31 downto 10*32) <= STAT_TIMEOUT(2*32+31 downto 2*32) or buf_HC_STAT_REGS(10*32+31 downto 10*32); end if; - if RESET = '1' or STAT_REG_STROBE(10) = '1' then - buf_HC_STAT_REGS(10*32+31 downto 10*32) <= (others => '0'); + if reg_STROBES(11) = '1' then + HC_STAT_REGS(11*32+31 downto 11*32) <= (others => '0'); else - buf_HC_STAT_REGS(10*32+31 downto 10*32) <= STAT_TIMEOUT(2*32+31 downto 2*32) or buf_HC_STAT_REGS(10*32+31 downto 10*32); + HC_STAT_REGS(11*32+31 downto 11*32) <= STAT_TIMEOUT(3*32+31 downto 3*32) or buf_HC_STAT_REGS(11*32+31 downto 11*32); end if; - if RESET = '1' or STAT_REG_STROBE(11) = '1' then - buf_HC_STAT_REGS(11*32+31 downto 11*32) <= (others => '0'); + + if reg_STROBES(36) = '1' then + HC_STAT_REGS(36*32+31 downto 36*32) <= (others => '0'); else - buf_HC_STAT_REGS(11*32+31 downto 11*32) <= STAT_TIMEOUT(3*32+31 downto 3*32) or buf_HC_STAT_REGS(11*32+31 downto 11*32); + for i in 0 to MII_NUMBER-1 loop + HC_STAT_REGS(36*32+i) <= HC_STAT_REGS(36*32+i) or buf_HUB_ERROR_BITS(i*32+48*32+1) or buf_HUB_ERROR_BITS(i*32+48*32+3) or + buf_HUB_ERROR_BITS(i*32+48*32+6); + end loop; end if; end if; end process; @@ -1018,10 +1051,14 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); PROC_REG_STAT_REGS : process(CLK) begin if rising_edge(CLK) then - HC_STAT_REGS <= buf_HC_STAT_REGS; + HC_STAT_REGS(8*32-1 downto 0) <= buf_HC_STAT_REGS(8*32-1 downto 0); + HC_STAT_REGS(31*32-1 downto 12*32) <= buf_HC_STAT_REGS(31*32-1 downto 12*32); + HC_STAT_REGS(36*32-1 downto 32*32) <= buf_HC_STAT_REGS(36*32-1 downto 32*32); end if; end process; + + --Control Registers HUB_CTRL_media_interfaces_off <= HC_CTRL_REGS(2**2*32+31 downto 2**2*32); HUB_CTRL_LOCAL_NETWORK_RESET <= HC_CTRL_REGS(7*32+MII_NUMBER-1 downto 7*32); @@ -1072,7 +1109,7 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); --map regio registers to stat & ctrl outputs COMMON_CTRL_REGS <= HC_COMMON_CTRL_REGS; MY_ADDRESS_OUT <= HUB_ADDRESS; - STAT_REGS <= HC_STAT_REGS; + STAT_REGS <= HC_STAT_REGS(16*32-1 downto 0); STAT_CTRL_REGS <= HC_CTRL_REGS(255 downto 0); HUB_CTRL_TIMEOUT_TIME <= HC_CTRL_REGS(5*32+31 downto 5*32); HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL; diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index bbfb8ea..829cd6b 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -306,7 +306,8 @@ component trb_net16_hub_streaming_port is STAT_POINTS_locked : out std_logic_vector (31 downto 0); STAT_TIMEOUT : out std_logic_vector (31 downto 0); STAT_ERRORBITS : out std_logic_vector (31 downto 0); - STAT_FSM : out std_logic_vector (15 downto 0); + STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); + STAT_FSM : out std_logic_vector (31 downto 0); CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1'); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) @@ -345,6 +346,7 @@ component trb_net16_hub_streaming_port is STAT_POINTS_locked : out std_logic_vector (31 downto 0); STAT_TIMEOUT : out std_logic_vector (31 downto 0); STAT_ERRORBITS : out std_logic_vector (31 downto 0); + STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 6b5536e..c9a8015 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -45,7 +45,8 @@ entity trb_net16_hub_ipu_logic is STAT_POINTS_locked : out std_logic_vector (31 downto 0); STAT_TIMEOUT : out std_logic_vector (31 downto 0); STAT_ERRORBITS : out std_logic_vector (31 downto 0); - STAT_FSM : out std_logic_vector (15 downto 0); + STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); + STAT_FSM : out std_logic_vector (31 downto 0); CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1'); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) @@ -90,13 +91,13 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal real_activepoints : std_logic_vector(POINT_NUMBER-1 downto 0); signal hdrram_write_enable : std_logic_vector(POINT_NUMBER-1 downto 0); signal hdrram_address : std_logic_vector(3*POINT_NUMBER-1 downto 0); - signal current_waiting_for_reply : std_logic_vector(POINT_NUMBER-1 downto 0); - signal next_current_waiting_for_reply : std_logic_vector(POINT_NUMBER-1 downto 0); +-- signal current_waiting_for_reply : std_logic_vector(POINT_NUMBER-1 downto 0); +-- signal next_current_waiting_for_reply : std_logic_vector(POINT_NUMBER-1 downto 0); signal current_reply_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); signal current_reply_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0); signal current_REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0); - signal current_muxed_reading_DAT : std_logic; +-- signal current_muxed_reading_DAT : std_logic; signal reg_current_reply_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0); signal reg_current_REPLY_reading_hdr : std_logic_vector(POINT_NUMBER-1 downto 0); @@ -185,7 +186,7 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal saved_reading_padding : std_logic_vector(POINT_NUMBER-1 downto 0); signal reading_padding : std_logic_vector(POINT_NUMBER-1 downto 0); signal got_all_DHDR : std_logic; - signal got_all_reply_starts : std_logic; +-- signal got_all_reply_starts : std_logic; signal not_reading_HDR : std_logic; signal number_of_replies : unsigned(4 downto 0); signal expected_replies : std_logic_vector(POINT_NUMBER-1 downto 0); @@ -201,7 +202,7 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is type timeout_counter_t is array (POINT_NUMBER-1 downto 0) of unsigned(15 downto 0); signal timeout_counter : timeout_counter_t; - signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0); +-- signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0); signal connection_timed_out : std_logic_vector(POINT_NUMBER-1 downto 0); signal timeout_found : std_logic; signal reg_CTRL_TIMEOUT_TIME : std_logic_vector(3 downto 0); @@ -213,7 +214,7 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal last_REPLY_PACKET_NUM_IN : std_logic_vector(POINT_NUMBER*3-1 downto 0); signal reply_fsm_statebits : std_logic_vector(3 downto 0); - + signal last_locked : std_logic; begin ---------------------------------- @@ -556,7 +557,7 @@ begin timeout_found <= or_all(connection_timed_out); if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = x"F" then timeout_counter(i) <= (others => '0'); - elsif timeout_counter(i)(to_integer(unsigned(reg_CTRL_TIMEOUT_TIME(2 downto 0)&'0'))) = '1' then + elsif timeout_counter(i)(to_integer(unsigned(reg_CTRL_TIMEOUT_TIME(2 downto 0)&'1'))) = '1' then connection_timed_out(i) <= '1'; elsif timer_ms_tick = '1' then timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1); @@ -625,7 +626,9 @@ begin ); reply_adder_val_enable(POINT_NUMBER-1 downto 0) <= (not locking_point and real_activepoints); - reply_adder_val_enable(reply_adder_val_enable'left downto POINT_NUMBER) <= (others => '0'); + gen_other_bits : if POINT_NUMBER < 17 generate + reply_adder_val_enable(reply_adder_val_enable'left downto POINT_NUMBER) <= (others => '0'); + end generate; reply_adder_input(POINT_NUMBER*16-1 downto 0) <= dhdr_data; gen_spare_bits : if POINT_NUMBER < 17 generate @@ -683,11 +686,29 @@ begin end process; end generate; + gen_monitoring_errorbits : process(CLK) + begin + if rising_edge(CLK) then + for i in 0 to POINT_NUMBER-1 loop + if (reply_reading_F1(i) and reg_current_reply_reading_TRM(i)) = '1' then + STAT_ALL_ERRORBITS(i*32+31 downto i*32+16) <= REPLY_DATA_IN(i*16+15 downto i*16); + end if; + if (reply_reading_F2(i) and reg_current_reply_reading_TRM(i)) = '1' then + STAT_ALL_ERRORBITS(i*32+15 downto i*32+0) <= REPLY_DATA_IN(i*16+15 downto i*16); + end if; + end loop; + end if; + end process; + + gen_other_errorbits : for i in POINT_NUMBER to 15 generate + STAT_ALL_ERRORBITS(i*32+31 downto i*32) <= (others => '0'); + end generate; + ---------------------------------- --read overhead data ---------------------------------- - process(RESET, send_reply_trm, REPLY_PACKET_NUM_IN, REPLY_DATAREADY_IN, REPLY_DATA_IN, start_read_padding, + process(reg_current_reply_reading_trm, reply_reading_f0, start_read_padding, saved_reading_padding) begin for i in 0 to POINT_NUMBER-1 loop @@ -912,14 +933,13 @@ begin ---------------------------------- reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter, send_reply_trm, REPLY_combined_trm_F1, REPLY_combined_trm_F2, got_all_DHDR, - comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA, init_locked, not_reading_HDR, - waiting_for_DHDR_word, got_all_reply_starts, - current_waiting_for_reply, locking_point, last_reply_adder_ready, + comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA, init_locked, + waiting_for_DHDR_word, locking_point, last_reply_adder_ready, real_activepoints, locked, MY_ADDRESS_IN, reply_adder_result, - reply_combined_trm_F3, reply_compare_finished, reg_current_reply_reading_hdr, + reply_combined_trm_F3, reply_compare_finished, reg_current_reply_auto_reading_dhdr, reply_adder_final_result, reg_current_reply_reading_dhdr, evt_seqnr, evt_dtype, evt_random_code, evt_number, number_of_replies, - reply_data_counter, current_point_length, enable_packing, + reply_data_counter, current_point_length, enable_packing, reply_arbiter_input, reply_arbiter_result, reply_reading_f2,current_reply_reading_trm) begin release_locked <= '0'; @@ -1002,6 +1022,7 @@ begin comb_REPLY_POOL_DATAREADY <= '1'; next_state <= WAIT_FOR_END_OF_DHDR; end if; + when others => null; end case; when WAIT_FOR_END_OF_DHDR => @@ -1271,15 +1292,32 @@ begin STAT_DEBUG(31 downto 29) <= last_REPLY_PACKET_NUM_IN(5 downto 3); --STAT(15 downto 8) <= data_counter; - STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not got_trm; + + proc_stat_errorbits : process(CLK) + begin + if rising_edge(CLK) then + last_locked <= locked; + if locked = '1' then + STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not got_trm; + else + STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= (others => '0'); + end if; + if locked = '0' and last_locked = '1' then + STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; + end if; + end if; + end process; + STAT_POINTS_locked(31 downto POINT_NUMBER) <= (others => '0'); - STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; - STAT_FSM(7 downto 0) <= reply_fsm_state; - STAT_FSM(8) <= reply_adder_start; - STAT_FSM(9) <= reply_compare_start; + + STAT_FSM(3 downto 0) <= reply_fsm_statebits; + STAT_FSM(7 downto 4) <= x"0"; + STAT_FSM(8) <= reply_adder_start; + STAT_FSM(9) <= reply_compare_start; STAT_FSM(12 downto 10)<= packet_counter; STAT_FSM(15 downto 13)<= dhdr_addr; + STAT_FSM(31 downto 16)<= (others => '0'); STAT_locked <= locked; diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index c30824c..4927496 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -41,6 +41,7 @@ entity trb_net16_hub_logic is STAT_POINTS_locked : out std_logic_vector (31 downto 0); STAT_TIMEOUT : out std_logic_vector (31 downto 0); STAT_ERRORBITS : out std_logic_vector (31 downto 0); + STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); CTRL_TIMEOUT_TIME : in std_logic_vector (3 downto 0); CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1'); CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) @@ -147,6 +148,7 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is signal timer_us_tick : std_logic; signal timer_ms_tick : std_logic; + signal last_locked : std_logic; begin @@ -461,6 +463,24 @@ begin end process; end generate; + gen_monitoring_errorbits : process(CLK) + begin + if rising_edge(CLK) then + for i in 0 to POINT_NUMBER-1 loop + if reading_trmF1(i) = '1' then + STAT_ALL_ERRORBITS(i*32+31 downto i*32+16) <= reply_data_in_i(i*16+15 downto i*16); + end if; + if reading_trmF2(i) = '1' then + STAT_ALL_ERRORBITS(i*32+15 downto i*32+0) <= reply_data_in_i(i*16+15 downto i*16); + end if; + end loop; + end if; + end process; + + gen_other_errorbits : for i in POINT_NUMBER to 15 generate + STAT_ALL_ERRORBITS(i*32+31 downto i*32) <= (others => '0'); + end generate; + ---------------------------------- --Check which of the available ports are active ---------------------------------- @@ -513,7 +533,7 @@ begin timeout_found <= or_all(connection_timed_out); if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' or locking_point(i) = '1' or reg_CTRL_TIMEOUT_TIME = x"F" then timeout_counter(i) <= (others => '0'); - elsif timeout_counter(i)(conv_integer(reg_CTRL_TIMEOUT_TIME(2 downto 0)&'0')) = '1' then + elsif timeout_counter(i)(conv_integer(reg_CTRL_TIMEOUT_TIME(2 downto 0)&'1')) = '1' then connection_timed_out(i) <= '1'; elsif timer_ms_tick = '1' then timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1); @@ -644,7 +664,7 @@ begin --REPLY POOL state machine ---------------------------------- reply_state_machine : process(REPLY_POOL_next_READ, current_state, packet_counter, REPLY_combined_trm_F0, - send_reply_trm, REPLY_combined_trm_F1, REPLY_combined_trm_F2, + send_reply_trm, REPLY_combined_trm_F1, REPLY_combined_trm_F2,connection_timed_out, comb_REPLY_muxed_DATAREADY, comb_REPLY_muxed_DATA, init_locked, comb_REPLY_muxed_PACKET_NUM, waiting_for_init_finish, REPLY_combined_trm_F3) begin @@ -759,9 +779,22 @@ STAT_locked <= locked; STAT(15 downto 10) <= (others => '0'); --STAT(15 downto 8) <= data_counter; - STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not got_trm; STAT_POINTS_locked(31 downto POINT_NUMBER) <= (others => '0'); - STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; + + proc_stat_errorbits : process(CLK) + begin + if rising_edge(CLK) then + last_locked <= locked; + if locked = '1' then + STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not got_trm; + else + STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= (others => '0'); + end if; + if locked = '0' and last_locked = '1' and reset_i = '0' then + STAT_ERRORBITS <= REPLY_combined_trm_F1 & REPLY_combined_trm_F2; + end if; + end if; + end process; end architecture; diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index eecf12a..5460607 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -64,11 +64,12 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); signal sbuf_status : std_logic; + signal real_reading : std_logic_vector(2**c_MUX_WIDTH -1 downto 0); -- Placer Directives - attribute HGROUP : string; + attribute HGROUP : string; -- for whole architecture - attribute HGROUP of trb_net16_io_multiplexer_arch : architecture is "MUX_group"; + attribute HGROUP of trb_net16_io_multiplexer_arch : architecture is "MUX_group"; attribute syn_preserve : boolean; attribute syn_keep : boolean; @@ -80,9 +81,12 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is attribute syn_keep of current_INT_READ_OUT : signal is true; attribute syn_preserve of final_INT_READ_OUT : signal is true; attribute syn_keep of final_INT_READ_OUT : signal is true; - + attribute syn_preserve of mux_read : signal is true; + attribute syn_keep of mux_read : signal is true; + attribute syn_preserve of real_reading : signal is true; + attribute syn_keep of real_reading : signal is true; attribute syn_hier : string; - attribute syn_hier of trb_net16_io_multiplexer_arch : architecture is "firm"; + attribute syn_hier of trb_net16_io_multiplexer_arch : architecture is "flatten, firm"; begin ------------------------------------------------------------------------------- -- DEMUX @@ -318,6 +322,11 @@ ARBITER: trb_net_priority_arbiter end process; mux_enable <= (mux_next_READ); -- or MED_READ_IN - mux_read <= or_all(current_INT_READ_OUT and INT_DATAREADY_IN); + + + gen_mux_read : for i in 0 to 2**c_MUX_WIDTH-1 generate + real_reading(i) <= current_INT_READ_OUT(i) and INT_DATAREADY_IN(i); + end generate; + mux_read <= or_all(real_reading); end architecture; diff --git a/trb_net16_med_16_CC.vhd b/trb_net16_med_16_CC.vhd index da48b81..1023f55 100644 --- a/trb_net16_med_16_CC.vhd +++ b/trb_net16_med_16_CC.vhd @@ -82,8 +82,8 @@ architecture trb_net16_med_16_CC_arch of trb_net16_med_16_CC is signal link_led : std_logic; signal tx_led : std_logic; signal rx_led : std_logic; - signal resync : std_logic; - signal resync_counter : unsigned(4 downto 0); + --signal resync : std_logic; + --signal resync_counter : unsigned(4 downto 0); signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal buf_MED_READ_OUT : std_logic; @@ -138,7 +138,7 @@ begin PROC_RX_COUNTER : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or resync = '1' then + if RESET = '1' then rx_counter <= c_H0; elsif buf_MED_DATAREADY_OUT = '1' and CLK_EN = '1' then if rx_counter = c_max_word_number then @@ -376,7 +376,7 @@ STAT_DEBUG(16) <= reg_DATA_VALID_IN; STAT_DEBUG(17) <= reg_DATA_CTRL_IN; STAT_DEBUG(18) <= resync_received; STAT_DEBUG(22 downto 19)<= std_logic_vector(pattern_counter(3 downto 0)); -STAT_DEBUG(23) <= resync; +STAT_DEBUG(23) <= '0'; STAT_DEBUG(26 downto 24)<= state_bits; STAT_DEBUG(63 downto 27) <= (others => '0'); diff --git a/trb_net16_med_16_IC.vhd b/trb_net16_med_16_IC.vhd index 6509005..1d470ed 100644 --- a/trb_net16_med_16_IC.vhd +++ b/trb_net16_med_16_IC.vhd @@ -40,7 +40,9 @@ end entity; architecture trb_net16_med_16_IC_arch of trb_net16_med_16_IC is - + signal buf_DATA_IN : std_logic_vector(15 downto 0); + signal buf_DATA_VALID_IN : std_logic; + signal buf_DATA_CTRL_IN : std_logic; signal reg_DATA_IN : std_logic_vector(15 downto 0); signal reg_DATA_VALID_IN : std_logic; signal reg_DATA_CTRL_IN : std_logic; @@ -67,6 +69,10 @@ architecture trb_net16_med_16_IC_arch of trb_net16_med_16_IC is signal buf_DATA_CTRL_OUT : std_logic; signal buf_DATA_OUT : std_logic_vector(15 downto 0); + signal reg0_DATA_VALID_IN : std_logic; + signal reg0_DATA_CTRL_IN : std_logic; + signal reg0_DATA_IN : std_logic_vector(15 downto 0); + signal med_error : std_logic_vector(2 downto 0); signal link_led : std_logic; signal link_running : std_logic; @@ -95,28 +101,60 @@ architecture trb_net16_med_16_IC_arch of trb_net16_med_16_IC is signal pattern_valid : std_logic; signal pattern_valid_q : std_logic; + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of trb_net16_med_16_IC_arch : architecture is "media_interface_group"; + begin ------------------------------------------- -- RX Input ------------------------------------------- - THE_INPUT_SYNC : signal_sync - generic map( - DEPTH => 2, - WIDTH => 18 - ) - port map( - RESET => RESET, - D_IN(15 downto 0) => DATA_IN, - D_IN(16) => DATA_VALID_IN, - D_IN(17) => DATA_CTRL_IN, - CLK0 => DATA_CLK_IN, - CLK1 => DATA_CLK_IN, - D_OUT(15 downto 0) => reg_DATA_IN, - D_OUT(16) => reg_DATA_VALID_IN, - D_OUT(17) => reg_DATA_CTRL_IN - ); + THE_INPUT_FF : process(DATA_CLK_IN) + begin + if falling_edge(DATA_CLK_IN) then + buf_DATA_IN <= DATA_IN; + buf_DATA_VALID_IN <= DATA_VALID_IN; + buf_DATA_CTRL_IN <= DATA_CTRL_IN; + end if; + end process; + + + THE_INPUT_SYNC : process(DATA_CLK_IN) + begin + if falling_edge(DATA_CLK_IN) then + reg0_DATA_IN <= buf_DATA_IN; + reg0_DATA_VALID_IN <= buf_DATA_VALID_IN; + reg0_DATA_CTRL_IN <= buf_DATA_CTRL_IN; + end if; + end process; + THE_INPUT_SYNC : process(DATA_CLK_IN) + begin + if rising_edge(DATA_CLK_IN) then + reg_DATA_IN <= reg0_DATA_IN; + reg_DATA_VALID_IN <= reg0_DATA_VALID_IN; + reg_DATA_CTRL_IN <= reg0_DATA_CTRL_IN; + end if; + end process; + +-- THE_INPUT_SYNC : signal_sync +-- generic map( +-- DEPTH => 1, +-- WIDTH => 18 +-- ) +-- port map( +-- RESET => RESET, +-- D_IN(15 downto 0) => buf_DATA_IN, +-- D_IN(16) => buf_DATA_VALID_IN, +-- D_IN(17) => buf_DATA_CTRL_IN, +-- CLK0 => DATA_CLK_IN, +-- CLK1 => DATA_CLK_IN, +-- D_OUT(15 downto 0) => reg_DATA_IN, +-- D_OUT(16) => reg_DATA_VALID_IN, +-- D_OUT(17) => reg_DATA_CTRL_IN +-- ); ------------------------------------------- -- RX Fifo @@ -222,7 +260,7 @@ begin THE_CLK_OUT : ddr_off port map( Clk => CLK, - Data => "01", + Data => "10", Q(0) => DATA_CLK_OUT ); @@ -424,18 +462,17 @@ begin ------------------------------------------- -- Debug ------------------------------------------- - STAT_DEBUG(2 downto 0) <= state_bits; - STAT_DEBUG(3) <= reg_DATA_VALID_IN; - STAT_DEBUG(4) <= reg_DATA_CTRL_IN; - STAT_DEBUG(5) <= make_reset; - STAT_DEBUG(6) <= not_connected; - STAT_DEBUG(7) <= present_sig; - STAT_DEBUG(8) <= last_DATA_CTRL_IN; - STAT_DEBUG(9) <= buf_DATA_VALID_OUT; - STAT_DEBUG(10) <= DATA_CLK_IN; - STAT_DEBUG(11) <= resync_received; - STAT_DEBUG(15 downto 12) <= reg_DATA_IN(3 downto 0); - - STAT_DEBUG(63 downto 16) <= (others => '0'); + STAT_DEBUG(0) <= reg_DATA_VALID_IN; + STAT_DEBUG(1) <= reg_DATA_CTRL_IN; + STAT_DEBUG(2) <= make_reset; + STAT_DEBUG(3) <= MED_DATAREADY_IN; + STAT_DEBUG(4) <= last_DATA_CTRL_IN; + STAT_DEBUG(5) <= buf_DATA_VALID_OUT; + STAT_DEBUG(6) <= buf_MED_READ_OUT; + STAT_DEBUG(7) <= resync_received; + STAT_DEBUG(15 downto 8) <= reg_DATA_IN(7 downto 0); + STAT_DEBUG(31 downto 16) <= buf_DATA_OUT; + + STAT_DEBUG(63 downto 32) <= (others => '0'); end architecture; \ No newline at end of file diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index 79fc69e..414e14f 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -6,6 +6,7 @@ LIBRARY unisim; USE UNISIM.VComponents.all; library work; use work.trb_net_std.all; +use work.trb_net_components.all; entity trb_net16_med_tlk is @@ -44,41 +45,6 @@ end trb_net16_med_tlk; architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is - component trb_net_fifo_16bit_bram_dualport is - generic( - USE_STATUS_FLAGS : integer := c_YES - ); - port ( - read_clock_in: IN std_logic; - write_clock_in: IN std_logic; - read_enable_in: IN std_logic; - write_enable_in: IN std_logic; - fifo_gsr_in: IN std_logic; - write_data_in: IN std_logic_vector(17 downto 0); - read_data_out: OUT std_logic_vector(17 downto 0); - full_out: OUT std_logic; - empty_out: OUT std_logic; - fifostatus_out: OUT std_logic_vector(3 downto 0); --counter for 1/16th of fifo - valid_read_out: OUT std_logic; - almost_empty_out:OUT std_logic; - almost_full_out :OUT std_logic - ); - end component trb_net_fifo_16bit_bram_dualport; - - component signal_sync is - generic( - WIDTH : integer := 1; - DEPTH : integer := 2 - ); - port( - RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register - CLK0 : in std_logic; --clock for first FF - CLK1 : in std_logic; --Clock for other FF - D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input - D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output - ); - end component; - signal fifo_din_a : std_logic_vector(17 downto 0); signal fifo_dout_a : std_logic_vector(17 downto 0); signal fifo_wr_en_a : std_logic; diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 4ca0472..40d2ec3 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -1,8 +1,6 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; use ieee.numeric_std.all; library work; use work.trb_net_std.all; @@ -15,7 +13,7 @@ entity trb_net16_obuf is USE_CHECKSUM : integer range 0 to 1 := c_YES; DATA_COUNT_WIDTH : integer range 1 to 7 := std_DATA_COUNT_WIDTH; -- max used buffer size is 2**DATA_COUNT_WIDTH. - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION + SBUF_VERSION : integer range 0 to 4 := std_SBUF_VERSION ); port( -- Misc @@ -49,6 +47,8 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is attribute HGROUP of trb_net16_obuf_arch : architecture is "OBUF_group"; attribute syn_hier : string; attribute syn_hier of trb_net16_obuf_arch : architecture is "flatten, firm"; + attribute syn_sharing : string; + attribute syn_sharing of trb_net16_obuf_arch : architecture is "off"; signal current_output_data_buffer : STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); @@ -61,10 +61,10 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is signal next_SEND_ACK_IN, reg_SEND_ACK_IN : STD_LOGIC; signal send_ACK, send_EOB, send_DATA : STD_LOGIC; - signal CURRENT_DATA_COUNT : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0); + signal CURRENT_DATA_COUNT : unsigned (DATA_COUNT_WIDTH-1 downto 0); -- signal max_DATA_COUNT, next_max_DATA_COUNT : STD_LOGIC_VECTOR (15 downto 0); - signal max_DATA_COUNT_minus_one : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0); - signal TRANSMITTED_BUFFERS : STD_LOGIC_VECTOR (1 downto 0); + signal max_DATA_COUNT_minus_one : unsigned (DATA_COUNT_WIDTH-1 downto 0); + signal TRANSMITTED_BUFFERS : unsigned (1 downto 0); signal increase_TRANSMITTED_BUFFERS, decrease_TRANSMITTED_BUFFERS : STD_LOGIC; signal SEND_BUFFER_SIZE_IN : STD_LOGIC_VECTOR (3 downto 0); @@ -89,7 +89,7 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal sbuf_status : std_logic; signal crc_match : std_logic; - signal buffer_number : std_logic_vector(15 downto 0); + signal buffer_number : unsigned(15 downto 0); signal buf_INT_READ_OUT : std_logic; signal int_dataready_in_i : std_logic; @@ -102,6 +102,18 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is signal wait_for_ack_max_bit : std_logic_vector(2 downto 0); signal timer_tick : std_logic; + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_preserve of wait_for_ack_timeout : signal is true; + attribute syn_preserve of wait_for_ack_counter : signal is true; + attribute syn_preserve of wait_for_ack_max_bit : signal is true; + attribute syn_preserve of timer_tick : signal is true; + attribute syn_keep of wait_for_ack_timeout : signal is true; + attribute syn_keep of wait_for_ack_counter : signal is true; + attribute syn_keep of wait_for_ack_max_bit : signal is true; + attribute syn_keep of timer_tick : signal is true; + + begin INT_READ_OUT <= buf_INT_READ_OUT; @@ -185,10 +197,10 @@ begin send_DATA <= not TRANSMITTED_BUFFERS(1); send_EOB <= '1' when (CURRENT_DATA_COUNT = max_DATA_COUNT_minus_one and saved_packet_type /= TYPE_TRM) else '0'; -- buffer registers - STAT_BUFFER(1 downto 0) <= TRANSMITTED_BUFFERS; + STAT_BUFFER(1 downto 0) <= std_logic_vector(TRANSMITTED_BUFFERS); STAT_BUFFER(14 downto 2) <= (others => '0'); STAT_BUFFER(15) <= send_DATA; - STAT_BUFFER(20 downto 16) <= CURRENT_DATA_COUNT(4 downto 0); + STAT_BUFFER(20 downto 16) <= std_logic_vector(CURRENT_DATA_COUNT(4 downto 0)); STAT_BUFFER(31 downto 21) <= (others => '0'); SEND_BUFFER_SIZE_IN <= CTRL_BUFFER(3 downto 0); REC_BUFFER_SIZE_IN <= CTRL_BUFFER(7 downto 4); @@ -206,7 +218,8 @@ begin max_DATA_COUNT_minus_one <= (others => '0'); end generate; - GENERATE_WORDS : process (transfer_counter, saved_packet_type, int_data_in_i, CRC, buffer_number, CTRL_BUFFER) + GENERATE_WORDS : process (transfer_counter, saved_packet_type, int_data_in_i, CRC, buffer_number, + CTRL_BUFFER, send_buffer_size_in, current_data_count) begin current_NOP_word <= (others => '0'); current_ACK_word <= (others => '0'); @@ -220,9 +233,9 @@ begin elsif transfer_counter = c_F1 then current_ACK_word(3 downto 0) <= SEND_BUFFER_SIZE_IN; elsif transfer_counter = c_F2 then - current_EOB_word(DATA_COUNT_WIDTH-1 downto 0) <= CURRENT_DATA_COUNT; + current_EOB_word(DATA_COUNT_WIDTH-1 downto 0) <= std_logic_vector(CURRENT_DATA_COUNT); elsif transfer_counter = c_F3 then - current_EOB_word(15 downto 0) <= buffer_number; + current_EOB_word(15 downto 0) <= std_logic_vector(buffer_number); current_ACK_word(15 downto 0) <= CTRL_BUFFER(31 downto 16); elsif transfer_counter = c_H0 then current_NOP_word(2 downto 0) <= TYPE_ILLEGAL; @@ -240,7 +253,7 @@ begin if transfer_counter = c_max_word_number then transfer_counter <= (others => '0'); else - transfer_counter <= transfer_counter + 1; + transfer_counter <= std_logic_vector(unsigned(transfer_counter) + to_unsigned(1,1)); end if; end if; end if; @@ -281,13 +294,13 @@ begin --full buffers (despite the sbuf) can only occur on the last packet. COMB_NEXT_TRANSFER : process(comb_dataready, transfer_counter, current_NOP_word, int_dataready_in_i, reg_INT_READ_OUT, - buf_INT_READ_OUT, saved_packet_type, sending_state, + saved_packet_type, sending_state, current_DATA_word, send_ACK, send_EOB, sbuf_free, RESET, current_ACK_word, current_EOB_word, int_packet_num_in_i, TRANSMITTED_BUFFERS, send_DATA, comb_next_read) begin current_output_data_buffer <= current_NOP_word; - current_output_num_buffer <= transfer_counter; + current_output_num_buffer <= std_logic_vector(transfer_counter); next_INT_READ_OUT <= '1'; increase_TRANSMITTED_BUFFERS <= '0'; increase_DATA_COUNT <= '0'; @@ -421,11 +434,11 @@ begin begin if rising_edge(CLK) then case REC_BUFFER_SIZE_IN(2 downto 0) is - when "010" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(2, DATA_COUNT_WIDTH); - when "011" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(4, DATA_COUNT_WIDTH); - when "110" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(100, DATA_COUNT_WIDTH); - when "111" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(100, DATA_COUNT_WIDTH); - when others => max_DATA_COUNT_minus_one <= conv_std_logic_vector(1, DATA_COUNT_WIDTH); + when "010" => max_DATA_COUNT_minus_one <= to_unsigned(2, DATA_COUNT_WIDTH); + when "011" => max_DATA_COUNT_minus_one <= to_unsigned(4, DATA_COUNT_WIDTH); + when "110" => max_DATA_COUNT_minus_one <= to_unsigned(100, DATA_COUNT_WIDTH); + when "111" => max_DATA_COUNT_minus_one <= to_unsigned(100, DATA_COUNT_WIDTH); + when others => max_DATA_COUNT_minus_one <= to_unsigned(1, DATA_COUNT_WIDTH); end case; end if; end process; @@ -443,7 +456,7 @@ begin TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS -1; end if; if increase_TRANSMITTED_BUFFERS = '1' then - buffer_number <= buffer_number + 1; + buffer_number <= buffer_number + to_unsigned(1,1); end if; end if; end if; @@ -463,9 +476,9 @@ begin begin if rising_edge(CLK) then wait_for_ack_timeout <= '0'; - if TRANSMITTED_BUFFERS(1) = '0' or wait_for_ack_max_bit = x"0" then + if TRANSMITTED_BUFFERS(1) = '0' or wait_for_ack_max_bit = "000" then wait_for_ack_counter <= (others => '0'); - elsif wait_for_ack_counter(conv_integer(wait_for_ack_max_bit)+1) = '1' then + elsif wait_for_ack_counter(to_integer(unsigned(wait_for_ack_max_bit)+to_unsigned(1,1))) = '1' then wait_for_ack_timeout <= '1'; elsif timer_tick = '1' then wait_for_ack_counter <= wait_for_ack_counter + to_unsigned(1,1); @@ -474,16 +487,16 @@ begin end process; -STAT_DEBUG(0) <= comb_dataready; -STAT_DEBUG(3 downto 1) <= transfer_counter; -STAT_DEBUG(4) <= buf_MED_DATAREADY_OUT; -STAT_DEBUG(7 downto 5) <= buf_MED_PACKET_NUM_OUT; -STAT_DEBUG(8) <= sbuf_free; -STAT_DEBUG(9) <= comb_next_read; -STAT_DEBUG(10) <= SEND_ACK_IN; -STAT_DEBUG(11) <= reg_SEND_ACK_IN; -STAT_DEBUG(12) <= RESET; -STAT_DEBUG(14 downto 13) <= TRANSMITTED_BUFFERS; +STAT_DEBUG(0) <= '0'; --comb_dataready; +STAT_DEBUG(3 downto 1) <= "000"; --transfer_counter; +STAT_DEBUG(4) <= '0'; --buf_MED_DATAREADY_OUT; +STAT_DEBUG(7 downto 5) <= "000"; --buf_MED_PACKET_NUM_OUT; +STAT_DEBUG(8) <= '0'; --sbuf_free; +STAT_DEBUG(9) <= '0'; --comb_next_read; +STAT_DEBUG(10) <= '0'; --SEND_ACK_IN; +STAT_DEBUG(11) <= '0'; --reg_SEND_ACK_IN; +STAT_DEBUG(12) <= '0'; --RESET; +STAT_DEBUG(14 downto 13) <= std_logic_vector(TRANSMITTED_BUFFERS); STAT_DEBUG(17 downto 15) <= REC_BUFFER_SIZE_IN(2 downto 0); STAT_DEBUG(19 downto 18) <= transfer_counter(1 downto 0); --used in hub monitoring! STAT_DEBUG(20) <= wait_for_ack_timeout; --used in hub monitoring diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 12c6741..391e689 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -250,7 +250,7 @@ begin buf_API_SEND_OUT, next_packet_counter, buf_API_DATA_OUT, buf_API_SHORT_TRANSFER_OUT, REGISTERS_IN, buf_REGISTERS_OUT, reg_enable_pattern, DAT_NO_MORE_DATA_IN, DAT_DATAREADY_IN, buf_DAT_DATA_IN, ADR_REJECTED, timeout_counter, nomoredata, - ADR_READ_OUT, ADR_DATAREADY_OUT, ADR_DATA_OUT, length, dont_understand, + ADR_DATAREADY_OUT, length, dont_understand, buf_rom_read_addr, ADR_SEND_OUT, rom_read_dout, COMMON_STAT_REG_IN, buf_COMMON_CTRL_REG_OUT, timeout, unknown, addr_counter_enable, DAT_UNKNOWN_ADDR_IN, dat_data_counter, DAT_WRITE_ACK_IN, DAT_DATAREADY_IN_before, ADR_DONT_UNDERSTAND, diff --git a/trb_net16_sbuf.vhd b/trb_net16_sbuf.vhd index 8b8041f..a324532 100644 --- a/trb_net16_sbuf.vhd +++ b/trb_net16_sbuf.vhd @@ -5,6 +5,7 @@ USE IEEE.STD_LOGIC_UNSIGNED.ALL; library work; use work.trb_net_std.all; +use work.trb_net_components.all; ------------------------------------------------------------------------------- @@ -12,11 +13,11 @@ use work.trb_net_std.all; -- The sbuf can be connected to a combinatorial logic (as an output buffer) -- to provide the synchronous logic -- --- 2 versions are provided --- VERSION=0 is the fast version, so double buffering is done --- VERSION=1 is half data rate: After data has beed written to the sbuf, --- the input read signal is stalled until the buffer is empty. --- Maybe enough for trigger and slow control channels +-- 4 versions are provided +-- VERSION=0 standard sbuf, 2 stages, read is combinatorial +-- VERSION=2 8 words deep fifo +-- VERSION=3 3 register stages, no combinatorial path +-- VERSION=4 1 stage, combinatorial read, uses different port logic! -- -- This is a wrapper for the normal sbuf that provides two data ports sharing -- the same logic. @@ -50,27 +51,6 @@ end entity; architecture trb_net16_sbuf_arch of trb_net16_sbuf is - component trb_net_sbuf is - generic ( - DATA_WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH; - VERSION: integer := VERSION); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN: in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_DATAREADY_OUT: out STD_LOGIC; - SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word - SYN_READ_IN: in STD_LOGIC; - STAT_BUFFER: out STD_LOGIC - ); - end component; - signal comb_in, syn_out : std_logic_vector (c_DATA_WIDTH + c_NUM_WIDTH - 1 downto 0); begin @@ -79,19 +59,86 @@ begin SYN_DATA_OUT <= syn_out(c_DATA_WIDTH - 1 downto 0); SYN_PACKET_NUM_OUT <= syn_out(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH); - sbuf: trb_net_sbuf - port map( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - COMB_DATAREADY_IN => COMB_DATAREADY_IN, - COMB_next_READ_OUT => COMB_next_READ_OUT, - COMB_READ_IN => COMB_READ_IN, - COMB_DATA_IN => comb_in, - SYN_DATAREADY_OUT => SYN_DATAREADY_OUT, - SYN_DATA_OUT => syn_out, - SYN_READ_IN => SYN_READ_IN, - STAT_BUFFER => STAT_BUFFER - ); + + gen_version_0 : if VERSION = 0 generate + sbuf: trb_net_sbuf + generic map( + DATA_WIDTH => 19 + ) + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => COMB_DATAREADY_IN, + COMB_next_READ_OUT => COMB_next_READ_OUT, + COMB_READ_IN => COMB_READ_IN, + COMB_DATA_IN => comb_in, + SYN_DATAREADY_OUT => SYN_DATAREADY_OUT, + SYN_DATA_OUT => syn_out, + SYN_READ_IN => SYN_READ_IN, + STAT_BUFFER => STAT_BUFFER + ); + end generate; + + gen_version_2 : if VERSION = 2 generate + sbuf: trb_net_sbuf2 + generic map( + DATA_WIDTH => 19 + ) + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => COMB_DATAREADY_IN, + COMB_next_READ_OUT => COMB_next_READ_OUT, + COMB_READ_IN => COMB_READ_IN, + COMB_DATA_IN => comb_in, + SYN_DATAREADY_OUT => SYN_DATAREADY_OUT, + SYN_DATA_OUT => syn_out, + SYN_READ_IN => SYN_READ_IN, + STAT_BUFFER => STAT_BUFFER + ); + end generate; + + gen_version_3 : if VERSION = 3 generate + sbuf: trb_net_sbuf3 + generic map( + DATA_WIDTH => 19 + ) + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => COMB_DATAREADY_IN, + COMB_next_READ_OUT => COMB_next_READ_OUT, + COMB_READ_IN => COMB_READ_IN, + COMB_DATA_IN => comb_in, + SYN_DATAREADY_OUT => SYN_DATAREADY_OUT, + SYN_DATA_OUT => syn_out, + SYN_READ_IN => SYN_READ_IN, + STAT_BUFFER => STAT_BUFFER + ); + end generate; + + gen_version_4 : if VERSION = 4 generate + sbuf: trb_net_sbuf4 + generic map( + DATA_WIDTH => 19 + ) + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => COMB_DATAREADY_IN, + COMB_next_READ_OUT => COMB_next_READ_OUT, + COMB_READ_IN => COMB_READ_IN, + COMB_DATA_IN => comb_in, + SYN_DATAREADY_OUT => SYN_DATAREADY_OUT, + SYN_DATA_OUT => syn_out, + SYN_READ_IN => SYN_READ_IN, + STAT_BUFFER => STAT_BUFFER + ); + end generate; + end architecture; diff --git a/trb_net16_term_buf.vhd b/trb_net16_term_buf.vhd index 66388e9..d485793 100644 --- a/trb_net16_term_buf.vhd +++ b/trb_net16_term_buf.vhd @@ -41,7 +41,9 @@ architecture trb_net16_term_buf_arch of trb_net16_term_buf is attribute HGROUP of trb_net16_term_buf_arch : architecture is "TRMBUF_group"; attribute syn_hier : string; - attribute syn_hier of trb_net16_term_buf_arch : architecture is "firm"; + attribute syn_hier of trb_net16_term_buf_arch : architecture is "flatten, firm"; + attribute syn_sharing : string; + attribute syn_sharing of trb_net16_term_buf_arch : architecture is "off"; signal INIT_SEQNR, next_INIT_SEQNR : std_logic_vector(7 downto 0); signal saved_packet_type : std_logic_vector(3 downto 0); @@ -56,14 +58,17 @@ architecture trb_net16_term_buf_arch of trb_net16_term_buf is signal buf_MED_REPLY_DATA_OUT, next_MED_REPLY_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal send_REPLY_trm : std_logic; signal next_send_REPLY_trm : std_logic; + signal init_real_reading : std_logic; + signal reply_real_reading : std_logic; attribute syn_preserve : boolean; attribute syn_keep : boolean; - attribute syn_sharing : string; - attribute syn_sharing of trb_net16_term_buf_arch : architecture is "off"; attribute syn_preserve of saved_packet_type : signal is true; attribute syn_keep of saved_packet_type : signal is true; - + attribute syn_preserve of init_real_reading : signal is true; + attribute syn_keep of init_real_reading : signal is true; + attribute syn_preserve of reply_real_reading : signal is true; + attribute syn_keep of reply_real_reading : signal is true; begin MED_READ_OUT <= '1'; @@ -132,13 +137,16 @@ begin end process; +init_real_reading <= buf_MED_INIT_DATAREADY_OUT and MED_INIT_READ_IN; +reply_real_reading <= buf_MED_REPLY_DATAREADY_OUT and MED_REPLY_READ_IN; + --count packets REG_INIT_TRANSFER_COUNTER : process(CLK) begin if rising_edge(CLK) then if RESET = '1' then INIT_transfer_counter <= c_H0; - elsif buf_MED_INIT_DATAREADY_OUT = '1' and MED_INIT_READ_IN = '1' then + elsif init_real_reading = '1' then if INIT_transfer_counter = c_max_word_number then INIT_transfer_counter <= (others => '0'); else diff --git a/trb_net_components.vhd b/trb_net_components.vhd index f0651b7..120070a 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -255,7 +255,15 @@ package trb_net_components is end component; - + component dll_in200_out100 is + port ( + clk: in std_logic; + aluhold: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic + ); + end component; component trb_net16_dummy_fifo is @@ -300,7 +308,7 @@ package trb_net_components is --standard values for output registers REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); --set to 0 for unused ctrl registers to save resources - REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := "00000001"; + REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := "0000000000000001"; --set to 0 for each unused bit in a register REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port @@ -1008,7 +1016,8 @@ package trb_net_components is component trb_net16_med_ecp_sfp_gbe is generic( SERDES_NUM : integer range 0 to 3 := 0; - EXT_CLOCK : integer range 0 to 1 := c_NO + EXT_CLOCK : integer range 0 to 1 := c_NO; + USE_200_MHZ : integer range 0 to 1 := c_NO ); port( CLK : in std_logic; -- SerDes clock @@ -1349,6 +1358,15 @@ package trb_net_components is + component pll_in200_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic + ); + end component; + + component pll25 is port( CLK : in std_logic; @@ -1655,7 +1673,68 @@ package trb_net_components is end component; + component trb_net_sbuf2 is + generic ( + DATA_WIDTH : integer := 18 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); + end component; + component trb_net_sbuf3 is + generic ( + DATA_WIDTH : integer := 18 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); + end component; + + component trb_net_sbuf4 is + generic ( + DATA_WIDTH : integer := 18 + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- port to combinatorial logic + COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word + COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle + COMB_READ_IN: in STD_LOGIC; --comb logic IS reading + COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_DATAREADY_OUT: out STD_LOGIC; + SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); + SYN_READ_IN: in STD_LOGIC; + STAT_BUFFER: out STD_LOGIC + ); + end component; diff --git a/trb_net_onewire.vhd b/trb_net_onewire.vhd index f95d934..6f0020f 100644 --- a/trb_net_onewire.vhd +++ b/trb_net_onewire.vhd @@ -73,7 +73,7 @@ begin bitcounter_vector <= conv_std_logic_vector(bitcounter,7); - process(state, timecounter, bitcounter_vector, input, + process(state, timecounter, bitcounter_vector, input, readout_enable_in, send_bit, output_tmp, skip_rom, recv_bit, conv_temp, reading_temp, send_rom) begin next_state <= state; diff --git a/trb_net_sbuf.vhd b/trb_net_sbuf.vhd index 62d90de..cd12b08 100644 --- a/trb_net_sbuf.vhd +++ b/trb_net_sbuf.vhd @@ -36,9 +36,6 @@ entity trb_net_sbuf is COMB_READ_IN : in STD_LOGIC; --comb logic IS reading -- the COMB_next_READ_OUT should be connected via comb. logic to a register -- to provide COMB_READ_IN (feedback path with 1 cycle delay) - -- The "REAL" READ_OUT can be constructed in the comb via COMB_next_READ_ - -- OUT and the READ_IN: If one of these is ='1', no problem to read in next - -- step. COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word -- Port to synchronous output. SYN_DATAREADY_OUT : out STD_LOGIC; @@ -66,12 +63,43 @@ architecture trb_net_sbuf_arch of trb_net_sbuf is signal combined_COMB_DATAREADY_IN: std_logic; signal use_current_b1_buffer: std_logic; + signal syn_real_reading : std_logic; + signal syn_wait_for_read : std_logic; + signal buf_SYN_READ_IN : std_logic; + + signal both_active : std_logic; + signal syn_only : std_logic; + signal comb_only : std_logic; + signal both_idle : std_logic; + signal not_syn_read: std_logic; + + attribute syn_preserve : boolean; attribute syn_keep : boolean; attribute syn_preserve of current_SYN_DATAREADY_OUT : signal is true; attribute syn_keep of current_SYN_DATAREADY_OUT : signal is true; attribute syn_preserve of current_next_READ_OUT : signal is true; attribute syn_keep of current_next_READ_OUT : signal is true; + attribute syn_preserve of combined_COMB_DATAREADY_IN : signal is true; + attribute syn_keep of combined_COMB_DATAREADY_IN : signal is true; + attribute syn_preserve of syn_real_reading : signal is true; + attribute syn_keep of syn_real_reading : signal is true; + attribute syn_preserve of syn_wait_for_read : signal is true; + attribute syn_keep of syn_wait_for_read : signal is true; + attribute syn_preserve of buf_SYN_READ_IN : signal is true; + attribute syn_keep of buf_SYN_READ_IN : signal is true; + attribute syn_preserve of both_active : signal is true; + attribute syn_keep of both_active : signal is true; + attribute syn_preserve of both_idle : signal is true; + attribute syn_keep of both_idle : signal is true; + attribute syn_preserve of comb_only : signal is true; + attribute syn_keep of comb_only : signal is true; + attribute syn_preserve of syn_only : signal is true; + attribute syn_keep of syn_only : signal is true; + attribute syn_preserve of not_syn_read : signal is true; + attribute syn_keep of not_syn_read : signal is true; + + attribute syn_hier : string; attribute syn_hier of trb_net_sbuf_arch : architecture is "flatten, firm"; @@ -96,9 +124,9 @@ begin end process; - COMB: process (current_buffer_state, SYN_READ_IN, COMB_DATA_IN, + COMB: process (current_buffer_state, COMB_DATA_IN, combined_comb_dataready_in, current_SYN_DATAREADY_OUT, current_got_overflow, - combined_COMB_DATAREADY_IN) + both_active, comb_only, syn_only) begin -- process COMB next_buffer_state <= current_buffer_state; next_next_READ_OUT <= '1'; @@ -120,12 +148,12 @@ begin end if; elsif current_buffer_state = BUFFER_B2_FULL then current_buffer_state_int <= "01"; - if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then + if combined_COMB_DATAREADY_IN = '1' and buf_SYN_READ_IN = '1' then --both_active = '1' -- COMB logic is writing into the sbuf -- at the same time syn port is reading move_b2_buffer <= '1'; next_SYN_DATAREADY_OUT <= '1'; - elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then + elsif combined_COMB_DATAREADY_IN = '1' and buf_SYN_READ_IN = '0' then -- ONLY COMB logic is writing into the sbuf -- this is the case when we should use the additional -- buffer @@ -133,7 +161,7 @@ begin next_next_READ_OUT <= '0'; --PLEASE stop writing move_b1_buffer <= '1'; next_SYN_DATAREADY_OUT <= '1'; - elsif combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1' then + elsif combined_COMB_DATAREADY_IN = '0' and buf_SYN_READ_IN = '1' then next_buffer_state <= BUFFER_EMPTY; next_SYN_DATAREADY_OUT <= '0'; else --if combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '0' then @@ -145,16 +173,16 @@ begin next_SYN_DATAREADY_OUT <= '1'; next_next_READ_OUT <= '0'; - if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then + if combined_COMB_DATAREADY_IN = '1' and buf_SYN_READ_IN = '1' then -- COMB logic is writing into the sbuf -- at the same time syn port is reading use_current_b1_buffer <= '1'; move_b1_buffer <= '1'; move_b2_buffer <= '1'; - elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then + elsif combined_COMB_DATAREADY_IN = '1' and buf_SYN_READ_IN = '0' then -- ONLY COMB logic is writing into the sbuf FATAL ERROR next_got_overflow <= '1'; - elsif combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1' then + elsif combined_COMB_DATAREADY_IN = '0' and buf_SYN_READ_IN = '1' then next_buffer_state <= BUFFER_B2_FULL; next_next_READ_OUT <= '1'; --? use_current_b1_buffer <= '1'; @@ -173,12 +201,12 @@ begin -- the SYN reader may release the RD signal at any point -- if this is the case, BREAK --combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1' - EM_STOP : process(current_next_READ_OUT, SYN_READ_IN, current_SYN_DATAREADY_OUT, + EM_STOP : process(current_next_READ_OUT, syn_real_reading, syn_wait_for_read, current_buffer_state) begin - if SYN_READ_IN = '0' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B2_FULL then + if current_SYN_DATAREADY_OUT = '1' and buf_SYN_READ_IN = '0' and current_buffer_state = BUFFER_B2_FULL then COMB_next_READ_OUT <= '0'; - elsif SYN_READ_IN = '1' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B1_FULL then + elsif current_SYN_DATAREADY_OUT = '1' and buf_SYN_READ_IN = '1' and current_buffer_state = BUFFER_B1_FULL then COMB_next_READ_OUT <= '1'; else COMB_next_READ_OUT <= current_next_READ_OUT; @@ -221,8 +249,17 @@ begin end if; end process; +-- syn_real_reading <= not not_syn_read and current_SYN_DATAREADY_OUT; +-- syn_wait_for_read <= not_syn_read and current_SYN_DATAREADY_OUT; + buf_SYN_READ_IN <= SYN_READ_IN; +-- both_active <= combined_COMB_DATAREADY_IN and not not_syn_read; +-- syn_only <= not combined_COMB_DATAREADY_IN and not not_syn_read; +-- comb_only <= combined_COMB_DATAREADY_IN and not_syn_read; +-- both_idle <= not combined_COMB_DATAREADY_IN and not_syn_read; +-- +-- not_syn_read <= not buf_SYN_READ_IN or RESET; end trb_net_sbuf_arch;