From: Jan Michel Date: Tue, 13 May 2014 16:41:43 +0000 (+0200) Subject: added table for IncludedFeatures registers X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d043b4aa9790ec8fb16355a8df3510934f4da0d0;p=daqdocu.git added table for IncludedFeatures registers --- diff --git a/trb3/IncludedFeaturesTable.tex b/trb3/IncludedFeaturesTable.tex new file mode 100644 index 0000000..7c299ef --- /dev/null +++ b/trb3/IncludedFeaturesTable.tex @@ -0,0 +1,40 @@ +\begin{longtable}{|p{0.10\textwidth}|p{0.08\textwidth}|p{0.13\textwidth}|X|} +\hline +\textbf{Table} & \textbf{Bit} & \textbf{Name} & \textbf{Description} \\ +\hline\hline +0 & 0 & Undefined & The feature table is not implemented in the design \\ +\hline +1\newline Central + & \multicolumn{3}{l|}{For a normal central FPGA design with Cts and/or GbE}\\ + & 3 -- 0 & ExtModule & Type of external trigger module (0: none, 1: CBM MBS, 2: Mainz M2)\\ + & 7 -- 4 & CtsTdc & Number of TDC channels included. Usually connected to the first trigger inputs of the CTS. +If a trigger module is present, the first channel will connect to its async output signal \\ + & 8 & CtsTdcX & The connection of TDC channels is non-standard. Refer to documentation. \\ + & 15 & CTS & The design contains a CTS module. A complete list of components can be obtained from the +CTS registers. \\ + & 16 & GbeData & Event data is sent via GbE \\ + & 17 & GbeCtrl & FPGA accepts slow-control messages via GbE \\ + & 19 -- 18 & GbeDataBuf & Size of the buffer for event data. 1: 64 kB \\ + & 21 -- 20 & GbeCtrlBuf & Size of the buffer for sctrl data. 1: 4 kB, 2: 64 kB \\ + & 22 & GbeMultBuf & GbE sctrl data can be split to multiple packets\\ + + & 26 -- 24 & Sfp & Number of SFP configured for TrbNet connections\\ + & 43 & Uart & Uart on RJ45\_CLOCK(4) (TTL)\\ + & 47 -- 44 & InpMonitor & Monitoring of input signals. See register 0xcf8f for number of channels and number of fifos +\\ + & 51 -- 48 & TrgModule & Type of trigger module 0: none, 1: simple or, 2: edge detect \\ + & 55 -- 52 & Clock & Main clock source: 0: onboard 200 MHz, 1: onboard 125 MHz, 2: 200 MHz RX clock on SFP1, 3: +125 MHz RX clock on SFP1, 4: external clock input 200 MHz, 5: external clock input 125 MHz\\ +\hline +2\newline TDC + & \multicolumn{3}{l|}{For TDC designs. Detailed information about the TDC setup can be found in register 0xc8xx}\\ + & 7 -- 0 & Pinout & Which pin-out is being used for the TDC inputs. 0: flexible by multiplexers, 1: default +1-to-1, 2: every second input (e.g. Padiwa Amps fast-only), 3: every fourth input (HPTDC very high speed mode)\\ + & 11 -- 8 & DoubleEdge & Double edge setup: 0: single edge only, 1: same channel, 2: alternating channels, 3: same +channel with stretcher \\ + & 42 & Spi & Contains SPI on all relevant I/Os depending on AddOn board design\\ + & 47 -- 44 & InpMonitor & See table 1. Pinout should match the one of the TDC\\ + & 51 -- 48 & TrgModule & See table 1. Pinout should match the one of the TDC\\ + & 55 -- 52 & Clock & See table 1\\ +\hline +\end{longtable} \ No newline at end of file diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex index 33d042a..571b2af 100644 --- a/trb3/Trb3GeneralRemarks.tex +++ b/trb3/Trb3GeneralRemarks.tex @@ -68,7 +68,11 @@ The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (reg \item[9300] design for CBM Tof \end{description*} -The lower 16 Bit are used to identify the contents of the design and the AddOn boards they should be used with. Combine as many values as you like by logical or. +The lower 16 Bit are used to identify the contents of the design and the AddOn boards they should be used with. Combine +as many values as you like by logical or. +Please note that these values have been partly superseded by the IncludedFeatures register described below. This +register should only be used to describe hardware-related features, like the needed AddOn Board. + \begin{description*} \item[Central FPGA]~ \begin{description*} @@ -93,18 +97,28 @@ The lower 16 Bit are used to identify the contents of the design and the AddOn b \item[6XXX] use with Nxyter \item[7XXX] use with 32PinAddOn \item[9XXX] use with ADC AddOn - \item[X0nX] contains $2^n$ TDC channels, single edge, n<8 - \item[X1nX] contains $2^n$ TDC channels, double edge, n<8 - \item[X2XX] contains a network hub - \item[X4XX] SPI interface on AddOn connector - \item[X8XX] Double edge TDC realized with two single edge channels - \item[XX8X] Non-TDC (because of bad choice of encoding) + \item[X0nX] {\color{darkgray}contains $2^n$ TDC channels, single edge, n<8} + \item[X1nX] {\color{darkgray}contains $2^n$ TDC channels, double edge, n<8} + \item[X2XX] {\color{darkgray}contains a network hub} + \item[X4XX] {\color{darkgray}SPI interface on AddOn connector} + \item[X8XX] {\color{darkgray}Double edge TDC realized with two single edge channels} + \item[XX8X] {\color{darkgray}Non-TDC (because of bad choice of encoding)} \item[XX9X] for MVD converter board 2013 - \item[XXX1] uses RX clock as main internal clock + \item[XXX1] {\color{darkgray}uses RX clock as main internal clock} \end{description*} \end{description*} -Software versions can be stored in the generic \signal{Regio\_Compile\_Version} (register 0x41). +\subsection{Included Features} +Basic Information about included features should be put to a generic setting named IncludedFeatures. This should be set +in the config.vhd file of each project according to the following table. The values are available from registers 0x41 +(lower 32 Bit) and 0x43 (upper 32 Bit) on TrbNet. The uppermost 8 Bit define a set of definitions that defines the +meaning of the remaining 56 Bit in the word. + +Fields marked as ``version'' should be increased after any bigger change in the design or major bug fixes. + +\begin{center} + \LTXtable{\textwidth}{IncludedFeaturesTable} +\end{center} \subsection{Network Addresses} The network addresses in a TRB3 set-up (not in HADES) follow a simple scheme: @@ -124,14 +138,11 @@ All boards of a given type are accessible by a broadcast address at the same tim \begin{itemize*} \item 0x40 for the central FPGA \item 0x45 for the peripheral FPGA - \item 0x41 for a design for FPGA 1 only - \item 0x42 for a design for FPGA 2 only - \item 0x43 for a design for FPGA 3 only - \item 0x44 for a design for FPGA 4 only \item 0x48 TDC design for peripheral FPGA \item 0x49 peripheral FPGA with Nxyter AddOn \item 0x4b peripheral FPGA with ADC AddOn \item 0x4d peripheral FPGA for MAPS read-out + \item 0x4e peripheral FPGA for Hades Start detector \item 0x50 CBM-Rich \end{itemize*} diff --git a/trb3/main.tex b/trb3/main.tex index 18cde0c..fe47d0b 100644 --- a/trb3/main.tex +++ b/trb3/main.tex @@ -34,6 +34,7 @@ \usepackage[update,prepend]{epstopdf} \definecolor{darkblue}{rgb}{.1,.1,.6} +\definecolor{darkgray}{rgb}{.5,.5,.5} \usepackage[linkbordercolor={0 0 0}, pdfborder={0 0 0}, bookmarks,