From: Andreas Neiser Date: Wed, 17 Jun 2015 11:44:02 +0000 (+0200) Subject: Revert to Diamond 2.1 and TDC v1.6.3 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d0971cde640bbcea1e0de28613bb1cc187652e08;p=trb3.git Revert to Diamond 2.1 and TDC v1.6.3 --- diff --git a/ADC/compile_constraints.pl b/ADC/compile_constraints.pl index 5c0b8c8..d7a00c5 100755 --- a/ADC/compile_constraints.pl +++ b/ADC/compile_constraints.pl @@ -70,6 +70,24 @@ close FILE; $lpf =~ s#THE_TDC/#GEN_TDC.THE_TDC/#g; + +# make the LPF diamond 2.1 compatible +# we assume that generate loops are all named with "gen_" +#$lpf =~ s#(gen_)(\w+?)\.#$1$2_#gi; +#$lpf =~ s#(gen_)(\w+?)(\d+)\.#$1$2$3_#gi; +#$lpf =~ s#(gen_)(\w+?)(\*)\.#$1$2$3_#gi; +#$lpf =~ s#SimAdder##g; +sub replace_dot { + my @m = @_; + $m[1] =~ s/\./_/g; + return join("", @m); +} +$lpf =~ s#(BLKNAME\s+)(.+?)([;\s])#replace_dot($1,$2,$3)#eg; +$lpf =~ s#(CELL\s+")(.+?)(")#replace_dot($1,$2,$3)#eg; +$lpf =~ s#(NET\s+")(.+?)(")#replace_dot($1,$2,$3)#eg; +$lpf =~ s#ff_array_en#ff_array_en_i#g; + + open FILE, ">$workdir/$TOPNAME.lpf" or die "Couldnt open file: $!"; print FILE $lpf; close FILE; diff --git a/ADC/compile_periph_gsi.pl b/ADC/compile_periph_gsi.pl index 80c3d64..05fb11e 100755 --- a/ADC/compile_periph_gsi.pl +++ b/ADC/compile_periph_gsi.pl @@ -9,9 +9,9 @@ use FileHandle; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_adc"; #Name of top-level entity -my $lattice_path = '/opt/lattice/diamond/3.4_x64'; +my $lattice_path = '/opt/lattice/diamond/2.1_x64'; my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed -my $synplify_path = '/opt/synplicity/J-2014.09-SP2'; +my $synplify_path = '/opt/synplicity/F-2012.03-SP1'; my $lm_license_file_for_synplify = '27000@lxcad01.gsi.de'; my $lm_license_file_for_par = '1702@hadeb05.gsi.de'; ################################################################################### diff --git a/ADC/config.vhd b/ADC/config.vhd index b3db5e1..138db8d 100644 --- a/ADC/config.vhd +++ b/ADC/config.vhd @@ -37,7 +37,7 @@ package config is constant ADC_TRIGGER_LOGIC : integer := c_YES; -- ADC channels may be 48 or 36, the latter for enabling compilation -- with TDC and lattice diamond version >2.1 - constant ADC_CHANNELS : integer := 36; + constant ADC_CHANNELS : integer := 48; --Include the TDC (only useful for CFD readout mode) constant INCLUDE_TDC : integer := c_YES; @@ -50,10 +50,14 @@ package config is constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 0; --> change names in constraints file - --ring buffer size: 32,64,96,128,dyn - constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 + --ring buffer size: 32,64,96,128,dyn + --for TDC v1.6.3, only 0,1,3 are valid + constant RING_BUFFER_SIZE : integer range 0 to 7 := 3; --ring buffer size: 0, 1, 2, 3, 7 + constant TDC_CONTROL_REG_NR : integer := 6; + + ------------------------------------------------------------------------------ --End of design configuration ------------------------------------------------------------------------------ diff --git a/ADC/tdc_release b/ADC/tdc_release index 043eaed..3f0371b 120000 --- a/ADC/tdc_release +++ b/ADC/tdc_release @@ -1 +1 @@ -../../tdc/releases/tdc_v2.1.3/ \ No newline at end of file +../../tdc/releases/tdc_v1.6.3 \ No newline at end of file diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd index 4d0fd22..87cc009 100644 --- a/ADC/trb3_periph_adc.vhd +++ b/ADC/trb3_periph_adc.vhd @@ -182,7 +182,6 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is signal tdc_inputs : std_logic_vector(TDC_CHANNEL_NUMBER-2 downto 0); - constant TDC_CONTROL_REG_NR : integer := 8; type tdc_ctrl_reg_arr_t is array (0 to TDC_CONTROL_REG_NR-1) of std_logic_vector(31 downto 0); signal tdc_ctrl_reg_arr : tdc_ctrl_reg_arr_t; signal tdc_ctrl_reg : std_logic_vector(TDC_CONTROL_REG_NR*32-1 downto 0); @@ -593,7 +592,7 @@ LED_YELLOW <= not med_stat_op(11); CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input HIT_IN => tdc_inputs, -- Channel start signals - HIT_CAL_IN => osc_int, --clk_20_i, -- Hits for calibrating the TDC + HIT_CALIBRATION => osc_int, --clk_20_i, -- Hits for calibrating the TDC TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width --