From: Jan Michel <j.michel@gsi.de>
Date: Fri, 30 May 2014 15:48:48 +0000 (+0200)
Subject: latest firmware version
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d19a046410d315915c41e02b042ab80b7832d664;p=electronics.git

latest firmware version
---

diff --git a/Power/firmware/PowerSwitch.c b/Power/firmware/PowerSwitch.c
index 6a67b21..99a5db1 100755
--- a/Power/firmware/PowerSwitch.c
+++ b/Power/firmware/PowerSwitch.c
@@ -34,10 +34,11 @@
 #define STARTTX(i) txcnt = (i);UCSR1B |= (1<< UDRIE1)
 #define ISMYADDR() (rxbuf[1] == '0' && (rxbuf[2] == '0' || rxbuf[2] == '1'))
 
-
-uint8_t  output_enable = 0;
+volatile uint8_t settings_changed = 0;
+uint8_t  output_enable = 0x3;
 uint8_t  output_error = 0;
 uint16_t adc[2];
+uint16_t avgadc[2] = {0,0};
 
 uint8_t rxcnt = 0, txcnt = 0, txpoint = 0;
 uint8_t rxbuf[7];
@@ -91,17 +92,20 @@ void send_answer_chars(uint8_t a, uint8_t b, uint8_t c) {
 void switchoutput(uint8_t chan, int8_t to) {
   if(to == -1)
     output_enable ^= (1<<chan);
-  else if (to == 0) {
+  else if (to == 0 || to == -2) {
     output_enable &= ~(1<<chan);
-    output_error  &= ~(1<<chan);
     }
-  else if (to == 1)
-    output_enable |= (1<<chan);
-    
-  uint8_t en1 = ((output_enable & 1) && !(output_error & 1))?1:0;
-  uint8_t en2 = ((output_enable & 2) && !(output_error & 2))?1:0;
-  PORTA = (PORTA & ~(1<<3)) | ((en1&1)<<3);
-  PORTA = (PORTA & ~(1<<2)) | ((en2&1)<<2);
+  else if (to == 1) {
+    output_enable |=  (1<<chan);
+	output_error  &= ~(1<<chan);
+	}
+
+  if(to >= -1) {settings_changed = 3;}
+  
+  uint8_t en1 = ((output_enable & 1) && !(output_error & 1))?0:1;
+  uint8_t en2 = ((output_enable & 2) && !(output_error & 2))?0:1;
+  PORTA = (PORTA & ~(3<<2)) | ((en1&1)<<3) | ((en2&1)<<2);
+
   }
 
 ISR(TIMER0_OVF_vect) {
@@ -109,10 +113,11 @@ ISR(TIMER0_OVF_vect) {
   if(!(PINA & 0x40)) {dwncnt[0]++;} else {dwncnt[0] = 0;}
   if(!(PINB & 0x04)) {dwncnt[1]++;} else {dwncnt[1] = 0;}
 	  
-  if(dwncnt[0] == 100) {switchoutput(0,-1);}	  
-  if(dwncnt[1] == 100) {switchoutput(1,-1);}
+  if(dwncnt[0] == 50) {switchoutput(0,-1);}	  
+  if(dwncnt[1] == 50) {switchoutput(1,-1);}
 	  
   ADCSRA |= (1<<ADSC);  
+  asm volatile("wdr");
   }
 
 ISR(ADC_vect) {
@@ -122,16 +127,21 @@ ISR(ADC_vect) {
     ADMUXA = 1;  
     ADCSRA |= (1<<ADSC); 
     channel = 1;
-    if(limit[0]<adc[0]) {
-      output_error |= 2;
+    avgadc[0] -= avgadc[0]/8;
+    avgadc[0] += adc[0];
+    if(limit[0]*8<avgadc[0]) {
+      output_error |= 1;
       switchoutput(0,-2);
       }  
     }
-  if(channel == 1) { 
+  else if(channel == 1) { 
     adc[1] = ADC; 
     ADMUXA = 7;  
+//    ADCSRA |= (1<<ADSC); 
     channel = 0;
-    if(limit[1]<adc[1]) {
+    avgadc[1] -= avgadc[1]/8;
+    avgadc[1] += adc[1];
+    if(limit[1]*8<avgadc[1]) {
       output_error |= 2;
       switchoutput(1,-2);
       }    
@@ -142,13 +152,14 @@ ISR(USART1_UDRE_vect) {
   UDR1 = txbuf[txpoint++];
   if(--txcnt == 0 || txpoint > 7) {  
     txpoint = 0;
+    txcnt = 0;
     UCSR1B &= ~(1<< UDRIE1);
     }
   }
   
 ISR(USART1_RX_vect) {
   uint8_t buf = UDR1;
-  if (rxcnt != 0 || (buf == 'S' || buf == 'A' || buf == 'L' || buf == 'C')) {
+  if (rxcnt != 0 || (buf == 'S' || buf == 'A' || buf == 'L' || buf == 'C' || buf == 'D')) {
     rxbuf[rxcnt++] = buf;
     }
   //Forward any incoming 4 letter answer
@@ -159,8 +170,8 @@ ISR(USART1_RX_vect) {
       // }
     if(rxcnt == 5) {
       if (rxbuf[0] == 'A') {
-        memcpy ((uint8_t*)txbuf,(uint8_t*)rxbuf,4);
-        STARTTX(4);
+        memcpy ((uint8_t*)txbuf,(uint8_t*)rxbuf,5);
+        STARTTX(5);
         }
     //Four letter 'switch' command  
       if (rxbuf[0] == 'S') {  
@@ -186,6 +197,16 @@ ISR(USART1_RX_vect) {
           forward_msg(5);
           }
         }
+    //Read average current command
+    if (rxbuf[0] == 'D') {
+	    if (ISMYADDR()) {
+		    if (rxbuf[3] == '?')
+		    send_answer_hex(avgadc[rxbuf[2]-'0']/8);
+	    }
+	    else {
+		    forward_msg(5);
+	    }
+    }
     //Read current limit    
       if (rxbuf[0] == 'L' && rxbuf[3] == '?') {
         if (ISMYADDR()) {
@@ -204,7 +225,8 @@ ISR(USART1_RX_vect) {
           uint16_t lim = hex_to_int(rxbuf[3])*256 + hex_to_int(rxbuf[4])*16 + hex_to_int(rxbuf[5]);
           limit[rxbuf[2]] = lim;
           }
-        send_answer_hex(limit[rxbuf[2]]);   
+        send_answer_hex(limit[rxbuf[2]]); 
+        settings_changed = rxbuf[2]+1;        
         }
       else {
         forward_msg(7);
@@ -216,18 +238,44 @@ ISR(USART1_RX_vect) {
     
 } 
 
+void eeprom_write(uint8_t addr, uint8_t data){
+  while(EECR & (1<<EEPE));
+  EECR = (0<<EEPM0);
+  EEARL = addr;
+  EEDR = data;
+  cli();
+  EECR |= (1<<EEMPE);
+  EECR |= (1<<EEPE);
+  sei();      
+  }
 
+uint8_t eeprom_read(uint8_t addr) {
+  while(EECR & (1<<EEPE));
+  EEARL = addr;
+  EECR |= (1<<EERE);
+  return EEDR;
+  }
+  
 __attribute__((naked)) int main(void) {
 	// Configure ports
+	
+  PUEA  = 0b01011100;
+  PUEB  = 0b00001100;
+  
   DDRA  = 0b00101100; 
   DDRB  = 0b00000000;
   
-  PORTA = 0b00000000;
+  PORTA = 0b00001100;
   PORTB = 0b00000000;
-
-  PUEA  = 0b01011100;
-  PUEB  = 0b00001100;  
-  	
+  
+  output_enable = eeprom_read(0x14);
+  switchoutput(0,-3); 
+  limit[0]  = eeprom_read(0x11)<<8;
+  limit[0] |= eeprom_read(0x10);
+  limit[1]  = eeprom_read(0x13)<<8;
+  limit[1] |= eeprom_read(0x12);  
+  
+  //CCP = 0xD8;  	//allow writing of CLKPR
   CLKPR = (0 << CLKPS0); // no prescaler  
   PRR   =  (1 << PRTWI)  | (0 << PRUSART1) | (1 << PRUSART0) | (1 << PRSPI) 
           |(1 << PRTIM2) | (1 << PRTIM1)   | (0 << PRTIM0)   | (0 << PRADC);  
@@ -235,21 +283,39 @@ __attribute__((naked)) int main(void) {
   TCCR0B = (4 << CS00);  //prescaler 256 -> 6M/256*256 = 91.5 Hz
   TIMSK0 = (1 << TOIE0); //Overflow interrupt`
   
-  ADMUXA = 1;  //(1 (Out2),7 (Out1))
+  ADMUXA = 7;  //(1 (Out2),7 (Out1))
   ADMUXB = (6 << REFS0);   //2.2V reference, with capacitor
-  ADCSRA = (1 << ADEN) | (1 << ADSC) | (1 << ADIE) | (7 << ADPS0); //enable, start, irq, /128
+  ADCSRA = (1 << ADEN) | (1 << ADSC) | (1 << ADIE) | (6 << ADPS0); //enable, start, irq, /128
   ADCSRB = 0;
   DIDR0  = (1<<ADC1D) | (1<< ADC7D); //disable digital inputs
   
   UCSR1A = (1 << U2X1);
   UCSR1B = (1 << RXCIE1) | (0 << TXCIE1) | (0 << RXEN1) | (1 << TXEN1);
   UCSR1C = (3 << UCSZ10); //8 Bit
-  UBRR1  = 0x26; //19200
+  UBRR1  = 0x0C; //57600
   
   _delay_ms(100);
   UCSR1B |= (1 << RXEN1);
+
+  CCP = 0xD8;
+  WDTCSR = (1<<WDE) | (5<<WDP0);  //Watchdog at .5 seconds
   sei();  
+  
+  
   while(1) {
-    
+    if (settings_changed == 1) {
+      settings_changed = 0;
+      eeprom_write(0x10,limit[0]&0xFF);
+      eeprom_write(0x11,(limit[0]>>8)&0xFF);
+      }
+    if (settings_changed == 2) {
+      settings_changed = 0;
+      eeprom_write(0x12,limit[1]&0xFF);
+      eeprom_write(0x13,(limit[1]>>8)&0xFF);
+      }
+    if (settings_changed == 3) {
+      settings_changed = 0;
+      eeprom_write(0x14,output_enable);
+      }
     }
   }
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