From: Tobias Weber Date: Wed, 11 Jul 2018 11:53:28 +0000 (+0200) Subject: Merge branch 'master' into Mupix8ReadoutRework X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d1f81f81f80b933d562d2c2596155315716e8780;p=trb3.git Merge branch 'master' into Mupix8ReadoutRework --- d1f81f81f80b933d562d2c2596155315716e8780 diff --cc mupix/Mupix8/tb/PixCtrlTest.vhd index b36e54a,825f7dc..59edd1b --- a/mupix/Mupix8/tb/PixCtrlTest.vhd +++ b/mupix/Mupix8/tb/PixCtrlTest.vhd @@@ -10,122 -10,199 +10,198 @@@ entity PixCtrlTest i end entity PixCtrlTest; architecture simulation of PixCtrlTest is - - component PixelControl - generic( - fpga_clk_speed : integer := 1e8; - spi_clk_speed : integer := 1e4 - ); - port( - clk : in std_logic; --clock - reset : in std_logic; --reset - mupixslctrl : out MupixSlowControl; - ctrl_dout : in std_logic; --serial data from mupix - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic - ); - end component PixelControl; - - component MupixShiftReg - generic( - pixeldac_shift_length : integer := 64 - ); - port( - clk1 : in std_logic; - clk2 : in std_logic; - sin : in std_logic; - sout : out std_logic); - end component MupixShiftReg; - - signal clk : std_logic; - signal reset : std_logic := '0'; - signal sout : std_logic := '0'; - signal mupix_ctrl : MupixSlowControl; - signal SLV_READ_IN : std_logic := '0'; - signal SLV_WRITE_IN : std_logic := '0'; - signal SLV_DATA_OUT : std_logic_vector(31 downto 0); - signal SLV_DATA_IN : std_logic_vector(31 downto 0) := (others => '0'); - signal SLV_ADDR_IN : std_logic_vector(15 downto 0) := (others => '0'); - signal SLV_ACK_OUT : std_logic; - signal SLV_NO_MORE_DATA_OUT : std_logic; - signal SLV_UNKNOWN_ADDR_OUT : std_logic; - - constant clk_period : time := 10 ns; - constant c_shiftregister_length : integer := 80; - constant c_time_per_word : time := 32*clk_period*1e8/1e7; - + + component PixelControl + generic( + fpga_clk_speed : integer := 1e8; + spi_clk_speed : integer := 1e4; + config_bits : integer := 3200 + ); + port( + clk : in std_logic; --clock + reset : in std_logic; --reset + mupixslctrl : out MupixSlowControl; + ctrl_dout : in std_logic; --serial data from mupix + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); + end component PixelControl; + + component MupixShiftReg + generic( + pixeldac_shift_length : integer := 64 + ); + port( + clk1 : in std_logic; + clk2 : in std_logic; + sin : in std_logic; + sout : out std_logic); + end component MupixShiftReg; + + signal clk : std_logic; + signal reset : std_logic := '0'; + signal sout : std_logic := '0'; + signal mupix_ctrl : MupixSlowControl; + signal SLV_READ_IN : std_logic := '0'; + signal SLV_WRITE_IN : std_logic := '0'; + signal SLV_DATA_OUT : std_logic_vector(31 downto 0); + signal SLV_DATA_IN : std_logic_vector(31 downto 0) := (others => '0'); + signal SLV_ADDR_IN : std_logic_vector(15 downto 0) := (others => '0'); + signal SLV_ACK_OUT : std_logic; + signal SLV_NO_MORE_DATA_OUT : std_logic; + signal SLV_UNKNOWN_ADDR_OUT : std_logic; + + constant clk_period : time := 10 ns; + constant c_shiftregister_length : integer := 80; + constant c_time_per_word : time := 32*clk_period*1e8/1e7; + constant c_testdata : std_logic_vector(c_shiftregister_length - 1 downto 0) := x"AAAAAAAABBBBBBBBCCCC"; + + -- send load signal to mupix using external slow control + procedure MupixLoad( + signal slv_write_in : out std_logic; + signal slv_data_in : out std_logic_vector(31 downto 0); + signal slv_addr_in : out std_logic_vector(15 downto 0); + constant clk_period : in time := 10 ns) is + begin + TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, x"00000018", x"0083"); + wait for 5*clk_period; + TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, x"00000000", x"0083"); + end procedure MupixLoad; + + -- reset of crc checksums and readback + procedure MupixReset ( + signal slv_write_in : out std_logic; + signal slv_data_in : out std_logic_vector(31 downto 0); + signal slv_addr_in : out std_logic_vector(15 downto 0); + constant clk_period : in time := 10 ns) is + begin + TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, x"0000000f", x"0084"); + TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, x"00000060", x"0083"); + end procedure MupixReset; + + -- purpose: write bit to mupix 8 + procedure WriteMupixSlow ( + signal slv_write_in : out std_logic; + signal slv_data_in : out std_logic_vector(31 downto 0); + signal slv_addr_in : out std_logic_vector(15 downto 0); + constant sin : in std_logic; + constant clk_period : in time := 10 ns) is + begin -- procedure WriteMupixSlow + slv_write_in <= '1'; + slv_addr_in <= x"0083"; + slv_data_in(4 downto 0) <= "1000" & sin; + wait for clk_period; + slv_write_in <= '0'; + wait for 100 ns; + slv_write_in <= '1'; + slv_addr_in <= x"0083"; + slv_data_in(4 downto 0) <= "1001" & sin; + wait for clk_period; + slv_write_in <= '0'; + wait for 100 ns; + slv_write_in <= '1'; + slv_addr_in <= x"0083"; + slv_data_in(4 downto 0) <= "1010" & sin; + wait for clk_period; + slv_write_in <= '0'; + wait for 100 ns; + slv_write_in <= '1'; + slv_addr_in <= x"0083"; + slv_data_in(4 downto 0) <= "1000" & "0"; + wait for clk_period; + slv_write_in <= '0'; + slv_data_in <= (others => '0'); + slv_addr_in <= (others => '0'); + wait for clk_period; + end procedure WriteMupixSlow; + begin - - dut : entity work.PixelControl - generic map( - fpga_clk_speed => 1e8, - spi_clk_speed => 1e7 - ) - port map( - clk => clk, - reset => reset, - ctrl_dout => sout, - mupixslctrl => mupix_ctrl, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_NO_MORE_DATA_OUT => SLV_NO_MORE_DATA_OUT, - SLV_UNKNOWN_ADDR_OUT => SLV_UNKNOWN_ADDR_OUT - ); - - mupix : entity work.MupixShiftReg - generic map( - pixeldac_shift_length => c_shiftregister_length - ) - port map( - clk1 => mupix_ctrl.clk1, - clk2 => mupix_ctrl.clk2, - sin => mupix_ctrl.sin, - sout => sout - ); - - clk_gen : process is - begin - clk <= '1'; - wait for clk_period/2; - clk <= '0'; - wait for clk_period/2; - end process clk_gen; - - stimulus_gen : process is - begin - wait for 100 ns; - --test control through trb slow control - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000011",x"0083"); - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000013",x"0083"); - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000014",x"0083"); - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000",x"0083"); - wait for 300 ns; - --test programming with data from FIFO via FPGA state machine - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, std_logic_vector(to_unsigned(c_shiftregister_length, 16)) & x"0000", x"0083"); - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"AAAAAAAA",x"0080"); - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"BBBBBBBB",x"0080"); - wait for 3*c_time_per_word; - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"CCCC0000",x"0080"); - --test of crc checksum computation - wait for 1.5*c_time_per_word; - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, std_logic_vector(to_unsigned(c_shiftregister_length, 16)) & x"0060", x"0083"); - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, std_logic_vector(to_unsigned(c_shiftregister_length, 16)) & x"0000", x"0083"); - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"AAAAAAAA",x"0080"); - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"BBBBBBBB",x"0080"); - TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"CCCC0000",x"0080"); - - wait; - end process stimulus_gen; - - + + dut : entity work.PixelControl + generic map( + fpga_clk_speed => 1e8, + spi_clk_speed => 1e7, + config_bits => 80 + ) + port map( + clk => clk, + reset => reset, + ctrl_dout => sout, + mupixslctrl => mupix_ctrl, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_NO_MORE_DATA_OUT => SLV_NO_MORE_DATA_OUT, + SLV_UNKNOWN_ADDR_OUT => SLV_UNKNOWN_ADDR_OUT + ); + + mupix : entity work.MupixShiftReg + generic map( + pixeldac_shift_length => c_shiftregister_length + ) + port map( + clk1 => mupix_ctrl.clk1, + clk2 => mupix_ctrl.clk2, + sin => mupix_ctrl.sin, + sout => sout + ); + + clk_gen : process is + begin + clk <= '1'; + wait for clk_period/2; + clk <= '0'; + wait for clk_period/2; + end process clk_gen; + + stimulus_gen : process is + begin + wait for 100 ns; + --test control through trb slow control + --first pass + for i in c_shiftregister_length - 1 downto 0 loop + WriteMupixSlow(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, c_testdata(i)); + end loop; + MupixLoad(slv_write_in, slv_data_in, slv_addr_in); + wait for 100 ns; + MupixReset(slv_write_in, slv_data_in, slv_addr_in); + wait for 1 us; + --second pass to test checksum and readback + for i in c_shiftregister_length - 1 downto 0 loop + WriteMupixSlow(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, c_testdata(i)); + end loop; -- send load and reset the readback + MupixLoad(slv_write_in, slv_data_in, slv_addr_in); + wait for 100 ns; + MupixReset(slv_write_in, slv_data_in, slv_addr_in); + wait for 1 us; + --read from readback memeory + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000002", x"0085"); + TRBRegisterRead(SLV_READ_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000000", x"0085"); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"00000005", x"0085"); + --test programming with data from FIFO via FPGA state machine + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, std_logic_vector(to_unsigned(c_shiftregister_length, 16)) & x"0000", x"0083"); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"AAAAAAAA", x"0080"); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"BBBBBBBB", x"0080"); + wait for 3*c_time_per_word; + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"CCCC0000", x"0080"); + --test of crc checksum computation + wait for 1.5*c_time_per_word; + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, std_logic_vector(to_unsigned(c_shiftregister_length, 16)) & x"0060", x"0083"); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, std_logic_vector(to_unsigned(c_shiftregister_length, 16)) & x"0000", x"0083"); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"AAAAAAAA", x"0080"); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"BBBBBBBB", x"0080"); + TRBRegisterWrite(SLV_WRITE_IN, SLV_DATA_IN, SLV_ADDR_IN, x"CCCC0000", x"0080"); + + wait; + end process stimulus_gen; + - end architecture simulation;