From: Cahit Date: Fri, 18 Apr 2014 06:33:37 +0000 (+0200) Subject: 64 word FIFO is used as the ring buffer X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=d21e0303793840c0e4625efbf2cdd4f324b869f2;p=trb3.git 64 word FIFO is used as the ring buffer --- diff --git a/32PinAddOn/config.vhd b/32PinAddOn/config.vhd index eae6e56..ac166dd 100644 --- a/32PinAddOn/config.vhd +++ b/32PinAddOn/config.vhd @@ -16,7 +16,7 @@ package config is constant USE_DOUBLE_EDGE : integer := c_YES; --Include SPI on AddOn connector - constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_SPI : integer := c_NO; --Add logic to generate configurable trigger signal from input signals. constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; @@ -27,6 +27,9 @@ package config is --number of real inputs to the FPGA constant PHYSICAL_INPUTS : integer := 32; +--Use 64 word ringbuffer instead of 128 word ringbuffer in TDC channels + constant USE_64_FIFO : integer := c_YES; + --Run wih 125 MHz instead of 100 MHz constant USE_125_MHZ : integer := c_NO; --not implemented yet! diff --git a/32PinAddOn/trb3_periph_32PinAddOn.prj b/32PinAddOn/trb3_periph_32PinAddOn.prj index 68f3916..dffe62a 100644 --- a/32PinAddOn/trb3_periph_32PinAddOn.prj +++ b/32PinAddOn/trb3_periph_32PinAddOn.prj @@ -163,6 +163,7 @@ add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd" add_file -vhdl -lib "work" "currentRelease/hit_mux.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd" add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x64_OutReg.vhd" add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd" add_file -vhdl -lib "work" "../base/code/input_statistics.vhd" add_file -vhdl -lib "work" "../base/code/sedcheck.vhd" diff --git a/tdc_releases/tdc_v1.6/Channel_200.vhd b/tdc_releases/tdc_v1.6/Channel_200.vhd index 67b8686..097eeb5 100644 --- a/tdc_releases/tdc_v1.6/Channel_200.vhd +++ b/tdc_releases/tdc_v1.6/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2014-04-09 +-- Last update: 2014-04-18 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -280,8 +280,25 @@ begin -- Channel_200 BINARY_CODE_OUT => encoder_data_out_i, ENCODER_DEBUG => encoder_debug_i); - FIFO : FIFO_DC_36x128_OutReg - port map ( + RingBuffer: if USE_64_FIFO = c_NO generate + FIFO : FIFO_DC_36x128_OutReg + port map ( + Data => fifo_data_in_i, + WrClock => CLK_200, + RdClock => CLK_100, + WrEn => fifo_wr_en_i, + RdEn => fifo_rd_en_i, + Reset => RESET_100, + RPReset => RESET_200, + Q => fifo_data_out_i, + Empty => fifo_empty_i, + Full => fifo_full_i, + AlmostFull => fifo_almost_full_i); + end generate RingBuffer; + + RingBuffer: if USE_64_FIFO = c_YES generate + FIFO : FIFO_DC_36x64_OutReg + port map ( Data => fifo_data_in_i, WrClock => CLK_200, RdClock => CLK_100, @@ -293,6 +310,7 @@ begin -- Channel_200 Empty => fifo_empty_i, Full => fifo_full_i, AlmostFull => fifo_almost_full_i); + end generate RingBuffer; fifo_almost_full_sync <= fifo_almost_full_i when rising_edge(CLK_100); fifo_rd_en_i <= fifo_rd_data_i or fifo_almost_full_sync when rising_edge(CLK_100);